From: pengcheng chen Date: Fri, 2 Mar 2018 07:41:39 +0000 (+0800) Subject: osd: add viu2 support for g12a X-Git-Tag: khadas-vims-v0.9.6-release~2386 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b9144dde6721e1aed40251e4557c450109751e03;p=platform%2Fkernel%2Flinux-amlogic.git osd: add viu2 support for g12a PD#156734: osd: add viu2 support for g12a Change-Id: If225bdd08a0357960ca307ca7614131211b9aed1 Signed-off-by: pengcheng chen --- diff --git a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts index daf1700..b7ac388 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts @@ -490,9 +490,10 @@ dev_name = "meson-fb"; status = "okay"; interrupts = <0 3 1 + 0 56 1 0 89 1>; - interrupt-names = "viu-vsync", "rdma"; - mem_size = <0x00800000 0x1980000 0x100000 0x100000>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ display_mode_default = "1080p60hz"; scale_mode = <1>; @@ -502,6 +503,8 @@ pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ mem_alloc = <1>; logo_addr = "0x3f800000"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; }; /* Audio Related start */ diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts index a72adec..8fbea5b 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts @@ -943,9 +943,10 @@ dev_name = "meson-fb"; status = "okay"; interrupts = <0 3 1 + 0 56 1 0 89 1>; - interrupt-names = "viu-vsync", "rdma"; - mem_size = <0x00800000 0x1980000 0x100000 0x100000>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ display_mode_default = "1080p60hz"; scale_mode = <1>; @@ -955,6 +956,8 @@ pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ mem_alloc = <0>; logo_addr = "0x3f800000"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; }; /* Audio Related start */ diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt_buildroot.dts b/arch/arm64/boot/dts/amlogic/g12a_skt_buildroot.dts index 3e0f463..2967d53 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_skt_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_skt_buildroot.dts @@ -1027,18 +1027,21 @@ dev_name = "meson-fb"; status = "disable"; interrupts = <0 3 1 + 0 56 1 0 89 1>; - interrupt-names = "viu-vsync", "rdma"; - mem_size = <0x00800000 0x1980000 0x100000 0x100000>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ display_mode_default = "1080p60hz"; scale_mode = <1>; /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ display_size_default = <1920 1080 1920 2160 32>; /*1920*1080*4*3 = 0x17BB000*/ - pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ mem_alloc = <1>; logo_addr = "0x3f800000"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; }; /* Audio Related start */ diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h index 162ef85..d85be70 100644 --- a/drivers/amlogic/clk/g12a/g12a.h +++ b/drivers/amlogic/clk/g12a/g12a.h @@ -58,6 +58,7 @@ #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ +#define HHI_VPU_CLKC_CNTL 0x1b4 /* 0x6d offset in data sheet */ #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ diff --git a/drivers/amlogic/clk/g12a/g12a_clk_media.c b/drivers/amlogic/clk/g12a/g12a_clk_media.c index d0d5aee..e5fe74b 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk_media.c +++ b/drivers/amlogic/clk/g12a/g12a_clk_media.c @@ -830,6 +830,118 @@ static struct clk_gate vpu_clkb_gate = { }, }; +static const char * const vpu_clkc_parent_names[] = { "fclk_div4", + "fclk_div3", "fclk_div5", "fclk_div7", "null", "null", + "null", "null"}; + +/* cts_clkc */ +static struct clk_mux vpu_clkc_p0_mux = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .mask = 0x7, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vpu_clkc_p0_mux", + .ops = &clk_mux_ops, + .parent_names = vpu_clkc_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider vpu_clkc_p0_div = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vpu_clkc_p0_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "vpu_clkc_p0_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate vpu_clkc_p0_gate = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "vpu_clkc_p0_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "vpu_clkc_p0_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux vpu_clkc_p1_mux = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .mask = 0x7, + .shift = 25, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vpu_clkc_p1_mux", + .ops = &clk_mux_ops, + .parent_names = vpu_clkc_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider vpu_clkc_p1_div = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vpu_clkc_p1_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "vpu_clkc_p1_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate vpu_clkc_p1_gate = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "vpu_clkc_p1_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "vpu_clkc_p1_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux vpu_clkc_mux = { + .reg = (void *)HHI_VPU_CLKC_CNTL, + .mask = 0x1, + .shift = 31, + .lock = &clk_lock, + .flags = CLK_PARENT_ALTERNATE, + .hw.init = &(struct clk_init_data){ + .name = "vpu_clkc_mux", + .ops = &meson_clk_mux_ops, + .parent_names = (const char *[]){ "vpu_clkc_p0_composite", + "vpu_clkc_p1_composite"}, + .num_parents = 2, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_hw *vpu_clkc_hws[] = { + [CLKID_VPU_CLKC_P0_MUX - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_p0_mux.hw, + [CLKID_VPU_CLKC_P0_DIV - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_p0_div.hw, + [CLKID_VPU_CLKC_P0_GATE - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_p0_gate.hw, + [CLKID_VPU_CLKC_P1_MUX - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_p1_mux.hw, + [CLKID_VPU_CLKC_P1_DIV - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_p1_div.hw, + [CLKID_VPU_CLKC_P1_GATE - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_p1_gate.hw, + [CLKID_VPU_CLKC_MUX - CLKID_VPU_CLKC_P0_MUX] = &vpu_clkc_mux.hw, +}; void meson_g12a_media_init(void) @@ -902,6 +1014,15 @@ void meson_g12a_media_init(void) vpu_clkb_div.reg = clk_base + (u64)(vpu_clkb_div.reg); vpu_clkb_gate.reg = clk_base + (u64)(vpu_clkb_gate.reg); + /* cts_vpu_clkc */ + vpu_clkc_p0_mux.reg = clk_base + (u64)(vpu_clkc_p0_mux.reg); + vpu_clkc_p0_div.reg = clk_base + (u64)(vpu_clkc_p0_div.reg); + vpu_clkc_p0_gate.reg = clk_base + (u64)(vpu_clkc_p0_gate.reg); + vpu_clkc_p1_mux.reg = clk_base + (u64)(vpu_clkc_p1_mux.reg); + vpu_clkc_p1_div.reg = clk_base + (u64)(vpu_clkc_p1_div.reg); + vpu_clkc_p1_gate.reg = clk_base + (u64)(vpu_clkc_p1_gate.reg); + vpu_clkc_mux.reg = clk_base + (u64)(vpu_clkc_mux.reg); + clks[CLKID_DSI_MEAS_COMP] = clk_register_composite(NULL, "dsi_meas_composite", g12a_meas_parent_names, 8, @@ -1145,6 +1266,38 @@ void meson_g12a_media_init(void) panic("%s: %d clk_register_composite vpu_clkb_composite error\n", __func__, __LINE__); + /* cts_vpu_clkc */ + clks[CLKID_VPU_CLKC_P0_COMP] = clk_register_composite(NULL, + "vpu_clkc_p0_composite", + vpu_clkc_parent_names, 8, + vpu_clkc_hws[CLKID_VPU_CLKC_P0_MUX - CLKID_VPU_CLKC_P0_MUX], + &clk_mux_ops, + vpu_clkc_hws[CLKID_VPU_CLKC_P0_DIV - CLKID_VPU_CLKC_P0_MUX], + &clk_divider_ops, + vpu_clkc_hws[CLKID_VPU_CLKC_P0_GATE - CLKID_VPU_CLKC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_VPU_CLKC_P0_COMP])) + panic("%s: %d clk_register_composite vpu_clkc_p0_composite error\n", + __func__, __LINE__); + + clks[CLKID_VPU_CLKC_P1_COMP] = clk_register_composite(NULL, + "vpu_clkc_p1_composite", + vpu_clkc_parent_names, 8, + vpu_clkc_hws[CLKID_VPU_CLKC_P1_MUX - CLKID_VPU_CLKC_P0_MUX], + &clk_mux_ops, + vpu_clkc_hws[CLKID_VPU_CLKC_P1_DIV - CLKID_VPU_CLKC_P0_MUX], + &clk_divider_ops, + vpu_clkc_hws[CLKID_VPU_CLKC_P1_GATE - CLKID_VPU_CLKC_P0_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_VPU_CLKC_P1_COMP])) + panic("%s: %d clk_register_composite vpu_clkc_p1_composite error\n", + __func__, __LINE__); + + clks[CLKID_VPU_CLKC_MUX] = clk_register(NULL, + vpu_clkc_hws[CLKID_VPU_CLKC_MUX - CLKID_VPU_CLKC_P0_MUX]); + if (IS_ERR(clks[CLKID_VPU_CLKC_MUX])) + panic("%s: %d clk_register vpu_clkc_mux error\n", + __func__, __LINE__); pr_info("%s: register meson media clk\n", __func__); } diff --git a/drivers/amlogic/drm/meson_drv.c b/drivers/amlogic/drm/meson_drv.c index 9ffc0d3..1538274 100644 --- a/drivers/amlogic/drm/meson_drv.c +++ b/drivers/amlogic/drm/meson_drv.c @@ -88,6 +88,7 @@ static struct osd_device_data_s osd_gxbb = { .osd_fifo_len = 32, .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_gxl = { @@ -102,6 +103,7 @@ static struct osd_device_data_s osd_gxl = { .osd_fifo_len = 32, .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_gxm = { @@ -116,6 +118,7 @@ static struct osd_device_data_s osd_gxm = { .osd_fifo_len = 32, .vpp_fifo_len = 0xfff, .dummy_data = 0x00202000,/* dummy data is different */ + .has_viu2 = 0, }; static struct osd_device_data_s osd_txl = { @@ -130,6 +133,7 @@ static struct osd_device_data_s osd_txl = { .osd_fifo_len = 64, .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_txlx = { @@ -144,6 +148,7 @@ static struct osd_device_data_s osd_txlx = { .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_axg = { @@ -159,6 +164,7 @@ static struct osd_device_data_s osd_axg = { .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ .vpp_fifo_len = 0x400, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_g12a = { @@ -173,6 +179,7 @@ static struct osd_device_data_s osd_g12a = { .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ .vpp_fifo_len = 0xfff,/* 2048 */ .dummy_data = 0x00808000, + .has_viu2 = 1, }; static const struct of_device_id meson_drm_dt_match[] = { diff --git a/drivers/amlogic/drm/meson_registers.h b/drivers/amlogic/drm/meson_registers.h index 6adf9c1..a632401 100644 --- a/drivers/amlogic/drm/meson_registers.h +++ b/drivers/amlogic/drm/meson_registers.h @@ -23,124 +23,11 @@ writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) /* vpp2 */ -#define VPP2_DUMMY_DATA 0x1900 -#define VPP2_LINE_IN_LENGTH 0x1901 -#define VPP2_PIC_IN_HEIGHT 0x1902 -#define VPP2_SCALE_COEF_IDX 0x1903 -#define VPP2_SCALE_COEF 0x1904 -#define VPP2_VSC_REGION12_STARTP 0x1905 -#define VPP2_VSC_REGION34_STARTP 0x1906 -#define VPP2_VSC_REGION4_ENDP 0x1907 -#define VPP2_VSC_START_PHASE_STEP 0x1908 -#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 -#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a -#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b -#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c -#define VPP2_VSC_PHASE_CTRL 0x190d -#define VPP2_VSC_INI_PHASE 0x190e -#define VPP2_HSC_REGION12_STARTP 0x1910 -#define VPP2_HSC_REGION34_STARTP 0x1911 -#define VPP2_HSC_REGION4_ENDP 0x1912 -#define VPP2_HSC_START_PHASE_STEP 0x1913 -#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 -#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 -#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 -#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 -#define VPP2_HSC_PHASE_CTRL 0x1918 -#define VPP2_SC_MISC 0x1919 -#define VPP2_PREBLEND_VD1_H_START_END 0x191a -#define VPP2_PREBLEND_VD1_V_START_END 0x191b -#define VPP2_POSTBLEND_VD1_H_START_END 0x191c -#define VPP2_POSTBLEND_VD1_V_START_END 0x191d -#define VPP2_PREBLEND_H_SIZE 0x1920 -#define VPP2_POSTBLEND_H_SIZE 0x1921 -#define VPP2_HOLD_LINES 0x1922 -#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 -#define VPP2_PREBLEND_CURRENT_XY 0x1924 -#define VPP2_POSTBLEND_CURRENT_XY 0x1925 -#define VPP2_MISC 0x1926 -#define VPP2_OFIFO_SIZE 0x1927 -#define VPP2_FIFO_STATUS 0x1928 -#define VPP2_SMOKE_CTRL 0x1929 -#define VPP2_SMOKE1_VAL 0x192a -#define VPP2_SMOKE2_VAL 0x192b -#define VPP2_SMOKE1_H_START_END 0x192d -#define VPP2_SMOKE1_V_START_END 0x192e -#define VPP2_SMOKE2_H_START_END 0x192f -#define VPP2_SMOKE2_V_START_END 0x1930 -#define VPP2_SCO_FIFO_CTRL 0x1933 -#define VPP2_HSC_PHASE_CTRL1 0x1934 -#define VPP2_HSC_INI_PAT_CTRL 0x1935 -#define VPP2_VADJ_CTRL 0x1940 -#define VPP2_VADJ1_Y 0x1941 -#define VPP2_VADJ1_MA_MB 0x1942 -#define VPP2_VADJ1_MC_MD 0x1943 -#define VPP2_VADJ2_Y 0x1944 -#define VPP2_VADJ2_MA_MB 0x1945 -#define VPP2_VADJ2_MC_MD 0x1946 -#define VPP2_MATRIX_PROBE_COLOR 0x195c -#define VPP2_MATRIX_HL_COLOR 0x195d -#define VPP2_MATRIX_PROBE_POS 0x195e -#define VPP2_MATRIX_CTRL 0x195f -#define VPP2_MATRIX_COEF00_01 0x1960 -#define VPP2_MATRIX_COEF02_10 0x1961 -#define VPP2_MATRIX_COEF11_12 0x1962 -#define VPP2_MATRIX_COEF20_21 0x1963 -#define VPP2_MATRIX_COEF22 0x1964 -#define VPP2_MATRIX_OFFSET0_1 0x1965 -#define VPP2_MATRIX_OFFSET2 0x1966 -#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 -#define VPP2_MATRIX_PRE_OFFSET2 0x1968 -#define VPP2_DUMMY_DATA1 0x1969 -#define VPP2_GAINOFF_CTRL0 0x196a -#define VPP2_GAINOFF_CTRL1 0x196b -#define VPP2_GAINOFF_CTRL2 0x196c -#define VPP2_GAINOFF_CTRL3 0x196d -#define VPP2_GAINOFF_CTRL4 0x196e -#define VPP2_CHROMA_ADDR_PORT 0x1970 -#define VPP2_CHROMA_DATA_PORT 0x1971 -#define VPP2_GCLK_CTRL0 0x1972 -#define VPP2_GCLK_CTRL1 0x1973 -#define VPP2_SC_GCLK_CTRL 0x1974 -#define VPP2_MISC1 0x1976 -#define VPP2_DNLP_CTRL_00 0x1981 -#define VPP2_DNLP_CTRL_01 0x1982 -#define VPP2_DNLP_CTRL_02 0x1983 -#define VPP2_DNLP_CTRL_03 0x1984 -#define VPP2_DNLP_CTRL_04 0x1985 -#define VPP2_DNLP_CTRL_05 0x1986 -#define VPP2_DNLP_CTRL_06 0x1987 -#define VPP2_DNLP_CTRL_07 0x1988 -#define VPP2_DNLP_CTRL_08 0x1989 -#define VPP2_DNLP_CTRL_09 0x198a -#define VPP2_DNLP_CTRL_10 0x198b -#define VPP2_DNLP_CTRL_11 0x198c -#define VPP2_DNLP_CTRL_12 0x198d -#define VPP2_DNLP_CTRL_13 0x198e -#define VPP2_DNLP_CTRL_14 0x198f -#define VPP2_DNLP_CTRL_15 0x1990 -#define VPP2_VE_ENABLE_CTRL 0x19a1 -#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 -#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 -#define VPP2_VE_H_V_SIZE 0x19a4 -#define VPP2_VDO_MEAS_CTRL 0x19a8 -#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 -#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa -#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 -#define VPP2_OSD_VSC_INI_PHASE 0x19c1 -#define VPP2_OSD_VSC_CTRL0 0x19c2 -#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 -#define VPP2_OSD_HSC_INI_PHASE 0x19c4 -#define VPP2_OSD_HSC_CTRL0 0x19c5 -#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 -#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 -#define VPP2_OSD_SC_CTRL0 0x19c8 -#define VPP2_OSD_SCI_WH_M1 0x19c9 -#define VPP2_OSD_SCO_H_START_END 0x19ca -#define VPP2_OSD_SCO_V_START_END 0x19cb -#define VPP2_OSD_SCALE_COEF_IDX 0x19cc -#define VPP2_OSD_SCALE_COEF 0x19cd -#define VPP2_INT_LINE_NUM 0x19ce +#define VPP2_MISC 0x1e26 +#define VPP2_OFIFO_SIZE 0x1e27 +#define VPP2_INT_LINE_NUM 0x1e20 +#define VPP2_OFIFO_URG_CTRL 0x1e21 + /* viu */ #define VIU_ADDR_START 0x1a00 diff --git a/drivers/amlogic/media/common/vpu/vpu.c b/drivers/amlogic/media/common/vpu/vpu.c index a422ddb..19e5ad60 100644 --- a/drivers/amlogic/media/common/vpu/vpu.c +++ b/drivers/amlogic/media/common/vpu/vpu.c @@ -1398,7 +1398,6 @@ static int vpu_probe(struct platform_device *pdev) set_vpu_clk(vpu_conf.clk_level); if (ret) vpu_power_init(); - creat_vpu_debug_class(); VPUPR("%s OK\n", __func__); diff --git a/drivers/amlogic/media/common/vpu/vpu_reg.h b/drivers/amlogic/media/common/vpu/vpu_reg.h index e734195..7fb946e 100644 --- a/drivers/amlogic/media/common/vpu/vpu_reg.h +++ b/drivers/amlogic/media/common/vpu/vpu_reg.h @@ -41,6 +41,7 @@ #define HHI_VPU_MEM_PD_REG1 0x42 #define HHI_VPU_MEM_PD_REG2 0x4d +#define HHI_VPU_CLKC_CNTL 0x6d #define HHI_VPU_CLK_CNTL 0x6f #define HHI_VPU_CLKB_CNTL 0x83 #define HHI_VAPBCLK_CNTL 0x7d diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h index 74cb00e..6935b20 100644 --- a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h @@ -225,124 +225,11 @@ #define G12_VD1_IF0_GEN_REG3 0x3216 #define G12_VD2_IF0_GEN_REG3 0x3236 -#define VPP2_DUMMY_DATA 0x1900 -#define VPP2_LINE_IN_LENGTH 0x1901 -#define VPP2_PIC_IN_HEIGHT 0x1902 -#define VPP2_SCALE_COEF_IDX 0x1903 -#define VPP2_SCALE_COEF 0x1904 -#define VPP2_VSC_REGION12_STARTP 0x1905 -#define VPP2_VSC_REGION34_STARTP 0x1906 -#define VPP2_VSC_REGION4_ENDP 0x1907 -#define VPP2_VSC_START_PHASE_STEP 0x1908 -#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 -#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a -#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b -#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c -#define VPP2_VSC_PHASE_CTRL 0x190d -#define VPP2_VSC_INI_PHASE 0x190e -#define VPP2_HSC_REGION12_STARTP 0x1910 -#define VPP2_HSC_REGION34_STARTP 0x1911 -#define VPP2_HSC_REGION4_ENDP 0x1912 -#define VPP2_HSC_START_PHASE_STEP 0x1913 -#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 -#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 -#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 -#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 -#define VPP2_HSC_PHASE_CTRL 0x1918 -#define VPP2_SC_MISC 0x1919 -#define VPP2_PREBLEND_VD1_H_START_END 0x191a -#define VPP2_PREBLEND_VD1_V_START_END 0x191b -#define VPP2_POSTBLEND_VD1_H_START_END 0x191c -#define VPP2_POSTBLEND_VD1_V_START_END 0x191d -#define VPP2_PREBLEND_H_SIZE 0x1920 -#define VPP2_POSTBLEND_H_SIZE 0x1921 -#define VPP2_HOLD_LINES 0x1922 -#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 -#define VPP2_PREBLEND_CURRENT_XY 0x1924 -#define VPP2_POSTBLEND_CURRENT_XY 0x1925 -#define VPP2_MISC 0x1926 -#define VPP2_OFIFO_SIZE 0x1927 -#define VPP2_FIFO_STATUS 0x1928 -#define VPP2_SMOKE_CTRL 0x1929 -#define VPP2_SMOKE1_VAL 0x192a -#define VPP2_SMOKE2_VAL 0x192b -#define VPP2_SMOKE1_H_START_END 0x192d -#define VPP2_SMOKE1_V_START_END 0x192e -#define VPP2_SMOKE2_H_START_END 0x192f -#define VPP2_SMOKE2_V_START_END 0x1930 -#define VPP2_SCO_FIFO_CTRL 0x1933 -#define VPP2_HSC_PHASE_CTRL1 0x1934 -#define VPP2_HSC_INI_PAT_CTRL 0x1935 -#define VPP2_VADJ_CTRL 0x1940 -#define VPP2_VADJ1_Y 0x1941 -#define VPP2_VADJ1_MA_MB 0x1942 -#define VPP2_VADJ1_MC_MD 0x1943 -#define VPP2_VADJ2_Y 0x1944 -#define VPP2_VADJ2_MA_MB 0x1945 -#define VPP2_VADJ2_MC_MD 0x1946 -#define VPP2_MATRIX_PROBE_COLOR 0x195c -#define VPP2_MATRIX_HL_COLOR 0x195d -#define VPP2_MATRIX_PROBE_POS 0x195e -#define VPP2_MATRIX_CTRL 0x195f -#define VPP2_MATRIX_COEF00_01 0x1960 -#define VPP2_MATRIX_COEF02_10 0x1961 -#define VPP2_MATRIX_COEF11_12 0x1962 -#define VPP2_MATRIX_COEF20_21 0x1963 -#define VPP2_MATRIX_COEF22 0x1964 -#define VPP2_MATRIX_OFFSET0_1 0x1965 -#define VPP2_MATRIX_OFFSET2 0x1966 -#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 -#define VPP2_MATRIX_PRE_OFFSET2 0x1968 -#define VPP2_DUMMY_DATA1 0x1969 -#define VPP2_GAINOFF_CTRL0 0x196a -#define VPP2_GAINOFF_CTRL1 0x196b -#define VPP2_GAINOFF_CTRL2 0x196c -#define VPP2_GAINOFF_CTRL3 0x196d -#define VPP2_GAINOFF_CTRL4 0x196e -#define VPP2_CHROMA_ADDR_PORT 0x1970 -#define VPP2_CHROMA_DATA_PORT 0x1971 -#define VPP2_GCLK_CTRL0 0x1972 -#define VPP2_GCLK_CTRL1 0x1973 -#define VPP2_SC_GCLK_CTRL 0x1974 -#define VPP2_MISC1 0x1976 -#define VPP2_DNLP_CTRL_00 0x1981 -#define VPP2_DNLP_CTRL_01 0x1982 -#define VPP2_DNLP_CTRL_02 0x1983 -#define VPP2_DNLP_CTRL_03 0x1984 -#define VPP2_DNLP_CTRL_04 0x1985 -#define VPP2_DNLP_CTRL_05 0x1986 -#define VPP2_DNLP_CTRL_06 0x1987 -#define VPP2_DNLP_CTRL_07 0x1988 -#define VPP2_DNLP_CTRL_08 0x1989 -#define VPP2_DNLP_CTRL_09 0x198a -#define VPP2_DNLP_CTRL_10 0x198b -#define VPP2_DNLP_CTRL_11 0x198c -#define VPP2_DNLP_CTRL_12 0x198d -#define VPP2_DNLP_CTRL_13 0x198e -#define VPP2_DNLP_CTRL_14 0x198f -#define VPP2_DNLP_CTRL_15 0x1990 -#define VPP2_VE_ENABLE_CTRL 0x19a1 -#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 -#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 -#define VPP2_VE_H_V_SIZE 0x19a4 -#define VPP2_VDO_MEAS_CTRL 0x19a8 -#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 -#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa -#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 -#define VPP2_OSD_VSC_INI_PHASE 0x19c1 -#define VPP2_OSD_VSC_CTRL0 0x19c2 -#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 -#define VPP2_OSD_HSC_INI_PHASE 0x19c4 -#define VPP2_OSD_HSC_CTRL0 0x19c5 -#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 -#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 -#define VPP2_OSD_SC_CTRL0 0x19c8 -#define VPP2_OSD_SCI_WH_M1 0x19c9 -#define VPP2_OSD_SCO_H_START_END 0x19ca -#define VPP2_OSD_SCO_V_START_END 0x19cb -#define VPP2_OSD_SCALE_COEF_IDX 0x19cc -#define VPP2_OSD_SCALE_COEF 0x19cd -#define VPP2_INT_LINE_NUM 0x19ce +#define VPP2_MISC 0x1e26 +#define VPP2_OFIFO_SIZE 0x1e27 +#define VPP2_INT_LINE_NUM 0x1e20 +#define VPP2_OFIFO_URG_CTRL 0x1e21 + #define VIU_OSD1_BLK0_CFG_W0 0x1a1b #define VIU_OSD1_MATRIX_CTRL 0x1a90 diff --git a/drivers/amlogic/media/osd/osd.h b/drivers/amlogic/media/osd/osd.h index 8162dfa..e8c903c 100644 --- a/drivers/amlogic/media/osd/osd.h +++ b/drivers/amlogic/media/osd/osd.h @@ -107,7 +107,7 @@ enum color_index_e { #define KEYCOLOR_FLAG_ONHOLD 2 #define KEYCOLOR_FLAG_CURRENT 4 -#define HW_OSD_COUNT 3 +#define HW_OSD_COUNT 4 #define OSD_BLEND_LAYERS 4 /* OSD block definition */ #define HW_OSD_BLOCK_COUNT 4 @@ -146,7 +146,8 @@ enum color_index_e { enum osd_index_e { OSD1 = 0, OSD2, - OSD3 + OSD3, + OSD4, }; enum osd_enable_e { @@ -215,6 +216,7 @@ enum osd_dev_e { DEV_OSD0 = 0, DEV_OSD1, DEV_OSD2, + DEV_OSD3, DEV_ALL, DEV_MAX }; @@ -410,6 +412,8 @@ struct osd_device_data_s { u8 osd_fifo_len; u32 vpp_fifo_len; u32 dummy_data; + u32 has_viu2; + struct clk *vpu_clkc; }; struct hw_osd_reg_s { @@ -498,6 +502,7 @@ struct hw_para_s { u32 color_key[HW_OSD_COUNT]; u32 color_key_enable[HW_OSD_COUNT]; u32 enable[HW_OSD_COUNT]; + u32 powered[HW_OSD_COUNT]; u32 reg_status_save; #ifdef FIQ_VSYNC bridge_item_t fiq_handle_item; @@ -556,7 +561,7 @@ struct hw_para_s { u32 afbc_status_err_reset; u32 afbc_use_latch; u32 hwc_enable; - u32 osd_use_latch; + u32 osd_use_latch[HW_OSD_COUNT]; u32 hw_cursor_en; u32 hw_rdma_en; }; diff --git a/drivers/amlogic/media/osd/osd_debug.c b/drivers/amlogic/media/osd/osd_debug.c index 76776ce..c9150bb 100644 --- a/drivers/amlogic/media/osd/osd_debug.c +++ b/drivers/amlogic/media/osd/osd_debug.c @@ -199,6 +199,8 @@ static void osd_debug_dump_register_all(void) osd_log_info("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg)); } + if (!osd_hw.powered[count - 1]) + count--; for (index = 0; index < count; index++) { osd_reg = &hw_osd_reg_array[index]; reg = osd_reg->osd_fifo_ctrl_stat; diff --git a/drivers/amlogic/media/osd/osd_drm.c b/drivers/amlogic/media/osd/osd_drm.c index 9193c8d..69289e4 100644 --- a/drivers/amlogic/media/osd/osd_drm.c +++ b/drivers/amlogic/media/osd/osd_drm.c @@ -350,7 +350,7 @@ static ssize_t osd_reverse_write_file(struct file *file, ret = kstrtoint(buf, 0, &osd_reverse); if (osd_reverse >= REVERSE_MAX) osd_reverse = REVERSE_FALSE; - osd_set_reverse_hw(osd_id, osd_reverse); + osd_set_reverse_hw(osd_id, osd_reverse, 1); return count; } diff --git a/drivers/amlogic/media/osd/osd_fb.c b/drivers/amlogic/media/osd/osd_fb.c index 4def52d..3a1e410 100644 --- a/drivers/amlogic/media/osd/osd_fb.c +++ b/drivers/amlogic/media/osd/osd_fb.c @@ -45,6 +45,7 @@ #include #include #include +#include /* Amlogic Headers */ #include #include @@ -61,6 +62,8 @@ static __u32 var_screeninfo[5]; static struct osd_device_data_s osd_meson_dev; +#define MAX_VPU_CLKC_CLK 500000000 +#define CUR_VPU_CLKC_CLK 200000000 struct osd_info_s osd_info = { .index = 0, .osd_reverse = 0, @@ -295,6 +298,35 @@ static struct fb_var_screeninfo fb_def_var[] = { .sync = 0, .vmode = FB_VMODE_NONINTERLACED, .rotate = 0, + }, + { + .xres = 32, + .yres = 32, + .xres_virtual = 32, + .yres_virtual = 32, + .xoffset = 0, + .yoffset = 0, + .bits_per_pixel = 32, + .grayscale = 0, + .red = {0, 0, 0}, + .green = {0, 0, 0}, + .blue = {0, 0, 0}, + .transp = {0, 0, 0}, + .nonstd = 0, + .activate = FB_ACTIVATE_NOW, + .height = -1, + .width = -1, + .accel_flags = 0, + .pixclock = 0, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 0, + .vsync_len = 0, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .rotate = 0, } }; @@ -325,6 +357,7 @@ static int osd_shutdown_flag; unsigned int osd_log_level; int int_viu_vsync = -ENXIO; +int int_viu2_vsync = -ENXIO; int int_rdma = INT_RDMA; struct osd_fb_dev_s *gp_fbdev_list[OSD_COUNT] = {}; static u32 fb_memsize[HW_OSD_COUNT + 1]; @@ -795,7 +828,7 @@ static int osd_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) case FBIOPUT_OSD_REVERSE: if (arg >= REVERSE_MAX) arg = REVERSE_FALSE; - osd_set_reverse_hw(info->node, arg); + osd_set_reverse_hw(info->node, arg, 1); break; case FBIOPUT_OSD_ROTATE_ON: break; @@ -1074,6 +1107,7 @@ static int malloc_osd_memory(struct fb_info *info) struct platform_device *pdev = NULL; phys_addr_t base = 0; unsigned long size = 0; + unsigned long fb_memsize_total = 0; #ifdef CONFIG_CMA struct cma *cma = NULL; #endif @@ -1106,10 +1140,11 @@ static int malloc_osd_memory(struct fb_info *info) var = &info->var; if (!fb_ion_client) fb_ion_client = meson_ion_client_create(-1, "meson-fb"); + for (j = 0; j <= osd_meson_dev.osd_count; j++) + fb_memsize_total += fb_memsize[j]; /* read cma/fb-reserved memory first */ if ((b_reserved_mem == true) && - ((fb_memsize[0] + fb_memsize[1] + - fb_memsize[2] + fb_memsize[3] <= size) && + ((fb_memsize_total <= size) && (fb_memsize[fb_index + 1] > 0))) { fb_rmem_size[fb_index] = fb_memsize[fb_index + 1]; if (fb_index == DEV_OSD0) @@ -1120,6 +1155,10 @@ static int malloc_osd_memory(struct fb_info *info) } else if (fb_index == DEV_OSD2) { fb_rmem_paddr[fb_index] = base + fb_memsize[0] + fb_memsize[1] + fb_memsize[2]; + } else if (fb_index == DEV_OSD3) { + fb_rmem_paddr[fb_index] = base + fb_memsize[0] + + fb_memsize[1] + fb_memsize[2] + + fb_memsize[3]; } pr_info("%s, %d, fb_index=%d,fb_rmem_size=%ld\n", __func__, __LINE__, fb_index, @@ -1354,6 +1393,18 @@ static int osd_open(struct fb_info *info, int arg) return 0; fb_index = fbdev->fb_index; + if ((osd_meson_dev.has_viu2) + && (fb_index == OSD4)) { + int vpu_clkc_rate; + + /* select mux0, if select mux1, mux0 must be set */ + clk_prepare_enable(osd_meson_dev.vpu_clkc); + clk_set_rate(osd_meson_dev.vpu_clkc, CUR_VPU_CLKC_CLK); + vpu_clkc_rate = clk_get_rate(osd_meson_dev.vpu_clkc); + osd_log_info("vpu clkc clock is %d MHZ\n", + vpu_clkc_rate/1000000); + osd_init_viu2(); + } if (osd_meson_dev.osd_count <= fb_index) return -1; if (b_alloc_mem) { @@ -1550,6 +1601,8 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, } osd_log_info("current vmode=%s, cmd: 0x%lx\n", vinfo->name, cmd); + if (!strcmp(vinfo->name, "invalid")) + return -1; switch (cmd) { case VOUT_EVENT_MODE_CHANGE: set_osd_logo_freescaler(); @@ -1569,6 +1622,7 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, else if (osd_meson_dev.osd_ver == OSD_HIGH_ONE) osd_set_antiflicker_hw(i, vinfo, gp_fbdev_list[i]->fb_info->var.yres); + osd_reg_write(VPP_POSTBLEND_H_SIZE, vinfo->width); console_unlock(); } break; @@ -1627,10 +1681,98 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, return 0; } +int osd_notify_callback_viu2(struct notifier_block *block, unsigned long cmd, + void *para) +{ + struct vinfo_s *vinfo = NULL; + struct osd_fb_dev_s *fb_dev; + int i, blank; + struct disp_rect_s *disp_rect; + +#ifdef CONFIG_AMLOGIC_VOUT2_SERVE + vinfo = get_current_vinfo2(); +#endif + + if (!vinfo) { + osd_log_err("current vinfo NULL\n"); + return -1; + } + osd_log_info("current vmode=%s, cmd: 0x%lx\n", + vinfo->name, cmd); + if (!strcmp(vinfo->name, "invalid")) + return -1; + i = osd_meson_dev.osd_count - 1; + switch (cmd) { + case VOUT_EVENT_MODE_CHANGE: + fb_dev = gp_fbdev_list[i]; + set_default_display_axis(&fb_dev->fb_info->var, + &fb_dev->osd_ctl, vinfo); + console_lock(); + osddev_update_disp_axis(fb_dev, 1); + osd_set_antiflicker_hw(i, vinfo, + gp_fbdev_list[i]->fb_info->var.yres); + osd_reg_write(VPP2_POSTBLEND_H_SIZE, vinfo->width); + console_unlock(); + break; + case VOUT_EVENT_OSD_BLANK: + blank = *(int *)para; + fb_dev = gp_fbdev_list[i]; + console_lock(); + osd_blank(blank, fb_dev->fb_info); + console_unlock(); + break; + case VOUT_EVENT_OSD_DISP_AXIS: + disp_rect = (struct disp_rect_s *)para; + if (!disp_rect) + break; + fb_dev = gp_fbdev_list[i]; + /* + * if osd layer preblend, + * it's position is controlled by vpp. + * if (fb_dev->preblend_enable) + * break; + */ + fb_dev->osd_ctl.disp_start_x = disp_rect->x; + fb_dev->osd_ctl.disp_start_y = disp_rect->y; + osd_log_dbg("set disp axis: x:%d y:%d w:%d h:%d\n", + disp_rect->x, disp_rect->y, + disp_rect->w, disp_rect->h); + if (disp_rect->x + disp_rect->w > vinfo->width) + fb_dev->osd_ctl.disp_end_x = vinfo->width - 1; + else + fb_dev->osd_ctl.disp_end_x = + fb_dev->osd_ctl.disp_start_x + + disp_rect->w - 1; + if (disp_rect->y + disp_rect->h > vinfo->height) + fb_dev->osd_ctl.disp_end_y = vinfo->height - 1; + else + fb_dev->osd_ctl.disp_end_y = + fb_dev->osd_ctl.disp_start_y + + disp_rect->h - 1; + disp_rect++; + osd_log_dbg("new disp axis: x0:%d y0:%d x1:%d y1:%d\n", + fb_dev->osd_ctl.disp_start_x, + fb_dev->osd_ctl.disp_start_y, + fb_dev->osd_ctl.disp_end_x, + fb_dev->osd_ctl.disp_end_y); + console_lock(); + osddev_update_disp_axis(fb_dev, 0); + console_unlock(); + break; + } + return 0; +} + static struct notifier_block osd_notifier_nb = { .notifier_call = osd_notify_callback, }; +#ifdef CONFIG_AMLOGIC_VOUT2_SERVE +static struct notifier_block osd_notifier_nb2 = { + .notifier_call = osd_notify_callback_viu2, +}; +#endif + static ssize_t store_enable_3d(struct device *device, struct device_attribute *attr, const char *buf, size_t count) @@ -2189,7 +2331,7 @@ static ssize_t store_osd_reverse(struct device *device, osd_reverse = res; if (osd_reverse >= REVERSE_MAX) osd_reverse = REVERSE_FALSE; - osd_set_reverse_hw(fb_info->node, osd_reverse); + osd_set_reverse_hw(fb_info->node, osd_reverse, 1); return count; } @@ -2797,7 +2939,51 @@ static struct device_attribute osd_attrs[] = { show_osd_hwc_enalbe, store_osd_hwc_enalbe), __ATTR(osd_do_hwc, 0220, NULL, store_do_hwc), +}; +static struct device_attribute osd_attrs_viu2[] = { + __ATTR(color_key, 0644, + show_color_key, store_color_key), + __ATTR(enable_key, 0664, + show_enable_key, store_enable_key), + __ATTR(enable_key_onhold, 0664, + show_enable_key_onhold, store_enable_key_onhold), + __ATTR(block_windows, 0644, + show_block_windows, store_block_windows), + __ATTR(block_mode, 0664, + show_block_mode, store_block_mode), + __ATTR(debug, 0644, + show_debug, store_debug), + __ATTR(log_level, 0644, + show_log_level, store_log_level), + __ATTR(flush_rate, 0444, + show_flush_rate, NULL), + __ATTR(osd_reverse, 0644, + show_osd_reverse, store_osd_reverse), + __ATTR(osd_antiflicker, 0644, + show_antiflicker, store_antiflicker), + __ATTR(ver_clone, 0644, + show_ver_clone, store_ver_clone), + __ATTR(ver_update_pan, 0220, + NULL, store_ver_update_pan), + __ATTR(osd_afbcd, 0664, + show_afbcd, store_afbcd), + __ATTR(osd_clear, 0220, + NULL, osd_clear), + __ATTR(reset_status, 0444, + show_reset_status, NULL), + __ATTR(osd_fps, 0644, + show_osd_fps, store_osd_fps), + __ATTR(osd_reg, 0220, + NULL, store_osd_reg), + __ATTR(osd_display_debug, 0644, + show_osd_display_debug, store_osd_display_debug), + __ATTR(osd_background_size, 0644, + show_osd_background_size, store_osd_background_size), + __ATTR(osd_afbc_debug, 0644, + show_osd_afbc_debug, store_osd_afbc_debug), + __ATTR(osd_afbc_format, 0644, + show_osd_afbc_format, store_osd_afbc_format), }; #ifdef CONFIG_PM @@ -2953,6 +3139,7 @@ static struct osd_device_data_s osd_gxbb = { .osd_fifo_len = 32, .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_gxtvbb = { @@ -2967,6 +3154,7 @@ static struct osd_device_data_s osd_gxtvbb = { .osd_fifo_len = 32, .vpp_fifo_len = 0xfff, .dummy_data = 0x0, + .has_viu2 = 0, }; static struct osd_device_data_s osd_gxl = { @@ -2981,6 +3169,7 @@ static struct osd_device_data_s osd_gxl = { .osd_fifo_len = 32, .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_gxm = { @@ -2995,6 +3184,7 @@ static struct osd_device_data_s osd_gxm = { .osd_fifo_len = 32, .vpp_fifo_len = 0xfff, .dummy_data = 0x00202000,/* dummy data is different */ + .has_viu2 = 0, }; static struct osd_device_data_s osd_txl = { @@ -3009,6 +3199,7 @@ static struct osd_device_data_s osd_txl = { .osd_fifo_len = 64, .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_txlx = { @@ -3023,6 +3214,7 @@ static struct osd_device_data_s osd_txlx = { .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ .vpp_fifo_len = 0x77f, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_axg = { @@ -3038,13 +3230,14 @@ static struct osd_device_data_s osd_axg = { .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ .vpp_fifo_len = 0x400, .dummy_data = 0x00808000, + .has_viu2 = 0, }; static struct osd_device_data_s osd_g12a = { .cpu_id = __MESON_CPU_MAJOR_ID_G12A, .osd_ver = OSD_HIGH_ONE, .afbc_type = MALI_AFBC, - .osd_count = 3, + .osd_count = 4, .has_deband = 1, .has_lut = 1, .has_rdma = 1, @@ -3052,6 +3245,7 @@ static struct osd_device_data_s osd_g12a = { .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ .vpp_fifo_len = 0xfff,/* 2048 */ .dummy_data = 0x00808000, + .has_viu2 = 1, }; static const struct of_device_id meson_fb_dt_match[] = { @@ -3140,6 +3334,15 @@ static int osd_probe(struct platform_device *pdev) goto failed1; } else osd_log_info("viu vsync irq: %d\n", int_viu_vsync); + if (osd_hw.osd_meson_dev.has_viu2) { + int_viu2_vsync = platform_get_irq_byname(pdev, "viu2-vsync"); + if (int_viu2_vsync == -ENXIO) { + osd_log_err("cannot get viu2 irq resource\n"); + goto failed1; + } else + osd_log_info("viu2 vsync irq: %d\n", int_viu2_vsync); + } + if (osd_meson_dev.has_rdma) { int_rdma = platform_get_irq_byname(pdev, "rdma"); if (int_viu_vsync == -ENXIO) { @@ -3147,12 +3350,21 @@ static int osd_probe(struct platform_device *pdev) goto failed1; } } + if (osd_meson_dev.has_viu2) { + osd_meson_dev.vpu_clkc = devm_clk_get(&pdev->dev, "vpu_clkc"); + if (IS_ERR(osd_meson_dev.vpu_clkc)) { + osd_log_err("cannot get vpu_clkc\n"); + osd_meson_dev.vpu_clkc = NULL; + ret = -ENOENT; + goto failed1; + } + } + ret = osd_io_remap(osd_meson_dev.osd_ver == OSD_SIMPLE); if (!ret) { osd_log_err("osd_io_remap failed\n"); goto failed1; } - /* init osd logo */ ret = logo_work_init(); if (ret == 0) @@ -3230,6 +3442,8 @@ static int osd_probe(struct platform_device *pdev) vinfo = get_current_vinfo(); for (index = 0; index < osd_meson_dev.osd_count; index++) { /* register frame buffer memory */ + if (!fb_memsize[index + 1]) + continue; fbi = framebuffer_alloc(sizeof(struct osd_fb_dev_s), &pdev->dev); if (!fbi) { @@ -3310,8 +3524,15 @@ static int osd_probe(struct platform_device *pdev) /* register frame buffer */ register_framebuffer(fbi); /* create device attribute files */ - for (i = 0; i < ARRAY_SIZE(osd_attrs); i++) - ret = device_create_file(fbi->dev, &osd_attrs[i]); + if (index <= DEV_OSD2) { + for (i = 0; i < ARRAY_SIZE(osd_attrs); i++) + ret = device_create_file( + fbi->dev, &osd_attrs[i]); + } else if ((osd_meson_dev.osd_ver == OSD_HIGH_ONE) && + (index == DEV_OSD3)) { + for (i = 0; i < ARRAY_SIZE(osd_attrs_viu2); i++) + ret = device_create_file(fbi->dev, &osd_attrs_viu2[i]); + } } #ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING; @@ -3322,12 +3543,19 @@ static int osd_probe(struct platform_device *pdev) /* init osd reverse */ if (osd_info.index == DEV_ALL) { - for (i = 0; i < osd_meson_dev.osd_count; i++) - osd_set_reverse_hw(i, osd_info.osd_reverse); - } else - osd_set_reverse_hw(osd_info.index, osd_info.osd_reverse); + for (i = 0; i < osd_meson_dev.osd_count - 1; i++) + osd_set_reverse_hw(i, osd_info.osd_reverse, 1); + osd_set_reverse_hw(i, osd_info.osd_reverse, 0); + } else if (osd_info.index <= DEV_OSD2) + osd_set_reverse_hw(osd_info.index, osd_info.osd_reverse, 1); + else if (osd_info.index == DEV_OSD3) + osd_set_reverse_hw(osd_info.index, osd_info.osd_reverse, 0); /* register vout client */ vout_register_client(&osd_notifier_nb); +#ifdef CONFIG_AMLOGIC_VOUT2_SERVE + if (osd_meson_dev.has_viu2) + vout2_register_client(&osd_notifier_nb2); +#endif INIT_DELAYED_WORK(&osd_dwork, mem_free_work); schedule_delayed_work(&osd_dwork, msecs_to_jiffies(60 * 1000)); @@ -3352,6 +3580,10 @@ static int osd_remove(struct platform_device *pdev) unregister_early_suspend(&early_suspend); #endif vout_unregister_client(&osd_notifier_nb); +#ifdef CONFIG_AMLOGIC_VOUT2_SERVE + if (osd_meson_dev.has_viu2) + vout2_unregister_client(&osd_notifier_nb2); +#endif for (i = 0; i < osd_meson_dev.osd_count; i++) { int j; @@ -3359,8 +3591,16 @@ static int osd_remove(struct platform_device *pdev) struct osd_fb_dev_s *fbdev = gp_fbdev_list[i]; fbi = fbdev->fb_info; - for (j = 0; j < ARRAY_SIZE(osd_attrs); j++) - device_remove_file(fbi->dev, &osd_attrs[j]); + if (i <= DEV_OSD2) { + for (j = 0; j < ARRAY_SIZE(osd_attrs); j++) + device_remove_file( + fbi->dev, &osd_attrs[j]); + } else if ((osd_meson_dev.osd_ver == OSD_HIGH_ONE) && + (i == DEV_OSD3)) { + for (j = 0; j < ARRAY_SIZE(osd_attrs_viu2); j++) + device_remove_file( + fbi->dev, &osd_attrs_viu2[j]); + } iounmap(fbdev->fb_mem_vaddr); if (osd_get_afbc(i)) { for (j = 1; j < OSD_MAX_BUF_NUM; j++) diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c index 8af26bb..3202e13 100644 --- a/drivers/amlogic/media/osd/osd_hw.c +++ b/drivers/amlogic/media/osd/osd_hw.c @@ -248,6 +248,55 @@ struct hw_osd_reg_s hw_osd_reg_array[HW_OSD_COUNT] = { VPU_MAFBC_OUTPUT_BUF_STRIDE_S2, VPU_MAFBC_PREFETCH_CFG_S2, }, + { + VIU2_OSD1_CTRL_STAT, + VIU2_OSD1_CTRL_STAT2, + VIU2_OSD1_COLOR_ADDR, + VIU2_OSD1_COLOR, + VIU2_OSD1_TCOLOR_AG0, + VIU2_OSD1_TCOLOR_AG1, + VIU2_OSD1_TCOLOR_AG2, + VIU2_OSD1_TCOLOR_AG3, + VIU2_OSD1_BLK0_CFG_W0, + VIU2_OSD1_BLK0_CFG_W1, + VIU2_OSD1_BLK0_CFG_W2, + VIU2_OSD1_BLK0_CFG_W3, + VIU2_OSD1_BLK0_CFG_W4, + VIU2_OSD1_BLK1_CFG_W4, + VIU2_OSD1_BLK2_CFG_W4, + VIU2_OSD1_FIFO_CTRL_STAT, + VIU2_OSD1_TEST_RDDATA, + VIU2_OSD1_PROT_CTRL, + VIU2_OSD1_MALI_UNPACK_CTRL, + VIU2_OSD1_DIMM_CTRL, + + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + VIU2_OSD1_UNSUPPORT, + } }; #endif @@ -485,6 +534,7 @@ static void osd_vpu_power_on(void) switch_vpu_mem_pd_vmod(VPU_VIU_OSD2, VPU_MEM_POWER_ON); switch_vpu_mem_pd_vmod(VPU_VIU_OSD_SCALE, VPU_MEM_POWER_ON); if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { + switch_vpu_mem_pd_vmod( VPU_VD2_OSD2_SCALE, VPU_MEM_POWER_ON); @@ -505,6 +555,24 @@ static void osd_vpu_power_on(void) #endif } +static void osd_vpu_power_on_viu2(void) +{ +#ifdef CONFIG_AMLOGIC_VPU + if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { + u32 val; + + switch_vpu_mem_pd_vmod(VPU_VIU2_OSD1, + VPU_MEM_POWER_ON); + switch_vpu_mem_pd_vmod(VPU_VIU2_OFIFO, + VPU_MEM_POWER_ON); + val = osd_reg_read(VPU_CLK_GATE); + val = val | 0x30000; + osd_log_info("VPU_CLK_GATE val=%x\n", val); + osd_reg_write(VPU_CLK_GATE, val); + } +#endif +} + #ifdef CONFIG_AMLOGIC_MEDIA_FB_OSD_SYNC_FENCE static inline int find_buf_num(u32 yres, u32 yoffset) { @@ -636,6 +704,12 @@ int osd_sync_request_render(u32 index, u32 yres, fence_map->dst_h = request->dst_h; fence_map->byte_stride = request->byte_stride; fence_map->pxiel_stride = request->pxiel_stride; + fence_map->background_w = request->background_w; + fence_map->background_h = request->background_h; + fence_map->zorder = request->zorder; + fence_map->premult_en = request->premult_en; + fence_map->afbc_en = request->afbc_en; + fence_map->afbc_inter_format = request->afbc_inter_format; fence_map->reserve = request->reserve; } fence_map->compose_type = request->type; @@ -924,6 +998,7 @@ void osd_update_scan_mode(void) osd_hw.scan_mode[OSD1] = SCAN_MODE_PROGRESSIVE; osd_hw.scan_mode[OSD2] = SCAN_MODE_PROGRESSIVE; osd_hw.scan_mode[OSD3] = SCAN_MODE_PROGRESSIVE; + osd_hw.scan_mode[OSD4] = SCAN_MODE_PROGRESSIVE; switch (output_type) { case VOUT_ENCP: if (osd_reg_read(ENCP_VIDEO_MODE) & (1 << 12)) { @@ -1193,6 +1268,22 @@ static irqreturn_t vsync_isr(int irq, void *dev_id) #endif } +#ifdef FIQ_VSYNC +static irqreturn_t vsync_viu2_isr(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static void osd_viu2_fiq_isr(void) +#else +static irqreturn_t vsync_viu2_isr(int irq, void *dev_id) +#endif +{ +#ifndef FIQ_VSYNC + return IRQ_HANDLED; +#endif +} + void osd_set_pxp_mode(u32 mode) { pxp_mode = mode; @@ -1200,6 +1291,7 @@ void osd_set_pxp_mode(u32 mode) void osd_set_afbc(u32 index, u32 enable) { if (osd_hw.osd_meson_dev.afbc_type) + if (index != OSD4) osd_hw.osd_afbcd[index].enable = enable; osd_log_info("afbc_type=%d,enable=%d\n", osd_hw.osd_meson_dev.afbc_type, @@ -1564,11 +1656,8 @@ void osd_setup_hw(u32 index, for (i = 0; i < OSD_MAX_BUF_NUM; i++) osd_hw.osd_afbcd[index].addr[i] = (u32)afbc_fbmem[i]; - if (pxp_mode) - osd_hw.osd_afbcd[index].phy_addr = - osd_hw.osd_afbcd[index].addr[0]; - else - osd_hw.osd_afbcd[index].phy_addr = 0; + osd_hw.osd_afbcd[index].phy_addr = + osd_hw.osd_afbcd[index].addr[0]; /* we need update geometry * and color mode for afbc mode * update_geometry = 1; @@ -1713,6 +1802,7 @@ static void osd_set_free_scale_enable_mode1(u32 index, u32 enable) unsigned int v_enable = 0; int ret = 0; + osd_log_info("osd_set_free_scale_enable_mode1\n"); if (osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE) return; h_enable = (enable & 0xffff0000 ? 1 : 0); @@ -1748,7 +1838,7 @@ static void osd_set_free_scale_enable_mode1(u32 index, u32 enable) void osd_set_free_scale_enable_hw(u32 index, u32 enable) { - if (osd_hw.free_scale_mode[index]) + if (osd_hw.free_scale_mode[index] && (index != OSD4)) osd_set_free_scale_enable_mode1(index, enable); else if (enable) osd_log_info( @@ -1979,7 +2069,7 @@ void osd_enable_hw(u32 index, u32 enable) spin_unlock_irqrestore(&osd_lock, lock_flags); osd_afbc_dec_enable = 0; - + osd_log_info("set color format\n"); add_to_update_list(index, OSD_COLOR_MODE); add_to_update_list(index, OSD_GBL_ALPHA); add_to_update_list(index, DISP_GEOMETRY); @@ -2156,14 +2246,16 @@ void osd_get_clone_hw(u32 index, u32 *clone) *clone = osd_hw.clone[index]; } -void osd_set_reverse_hw(u32 index, u32 reverse) +void osd_set_reverse_hw(u32 index, u32 reverse, u32 update) { char *str[4] = {"NONE", "ALL", "X_REV", "Y_REV"}; osd_hw.osd_reverse[index] = reverse; pr_info("set osd%d reverse as %s\n", index, str[reverse]); - add_to_update_list(index, DISP_OSD_REVERSE); - osd_wait_vsync_hw(); + if (update) { + add_to_update_list(index, DISP_OSD_REVERSE); + osd_wait_vsync_hw(); + } } void osd_get_reverse_hw(u32 index, u32 *reverse) @@ -3653,6 +3745,7 @@ static void osd_update_coef(u32 index) int use_v_filter_mode, use_h_filter_mode; int OSD_SCALE_COEF_IDX, OSD_SCALE_COEF; + osd_log_info("osd_update_coef\n"); if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { OSD_SCALE_COEF_IDX = hw_osd_reg_array[index].osd_scale_coef_idx; @@ -3751,6 +3844,7 @@ static void osd_update_color_mode(u32 index) u32 data32 = 0; struct hw_osd_reg_s *osd_reg = &hw_osd_reg_array[index]; + osd_log_info("osd_update_color_mode\n"); if (osd_hw.color_info[index] != NULL) { enum color_index_e idx = osd_hw.color_info[index]->color_index; @@ -3911,7 +4005,7 @@ static void osd_update_enable(u32 index) { u32 temp_val = 0; struct hw_osd_reg_s *osd_reg = &hw_osd_reg_array[index]; - + osd_log_info("osd_update_enable,index=%d\n", index); /* if (!osd_hw.buffer_alloc[index]) return; @@ -4221,7 +4315,7 @@ static int get_available_layers(void) int i; int available_layer = 0; - for (i = 0 ; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0 ; i < osd_hw.osd_meson_dev.osd_count - 1; i++) { if (osd_hw.enable[i]) available_layer++; } @@ -4234,7 +4328,7 @@ static int check_order_continuous(u32 *order) int save_order[3] = {0, 0, 0}; bool continuous = false; - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_hw.osd_meson_dev.osd_count - 1; i++) { if (order[i]) { save_order[j] = order[i]; j++; @@ -4387,7 +4481,7 @@ static void adjust_freescale_para(struct hw_osd_blending_s *blending) static void generate_blend_din_table(struct hw_osd_blending_s *blending) { int i = 0; - int osd_count = osd_hw.osd_meson_dev.osd_count; + int osd_count = osd_hw.osd_meson_dev.osd_count - 1; /* reorder[i] = osd[i]'s display layer */ for (i = 0; i < OSD_BLEND_LAYERS; i++) @@ -4492,7 +4586,7 @@ static void adjust_blend_din_table(struct hw_osd_blending_s *blending) /* reorder[i] = osd[i]'s display layer */ /* tow osd_x input to vpp, default osd2 is top */ blending->din_reoder_sel = 0; - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_hw.osd_meson_dev.osd_count - 1; i++) { switch (blending->reorder[i]) { /* blend_din1 is top, blend_din(3 4) is bottom layer */ case LAYER_1: @@ -4732,22 +4826,23 @@ static int osd_setting_order(void) int osd_blend_mode = 0; bool b_exchange = false, b_continuous = false; u32 blend_hsize, blend_vsize; + u32 osd_count = osd_hw.osd_meson_dev.osd_count - 1; /* number largest is top layer */ - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_count; i++) { org_order[i] = osd_hw.order[i]; if (!osd_hw.enable[i]) org_order[i] = 0; order[i] = org_order[i]; } - insert_sort(order, osd_hw.osd_meson_dev.osd_count); + insert_sort(order, osd_count); b_continuous = check_order_continuous(order); osd_log_dbg("after sort:zorder:%d,%d,%d\n", order[0], order[1], order[2]); /* reorder[i] = osd[i]'s display layer */ - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { - for (j = 0; j < osd_hw.osd_meson_dev.osd_count; j++) { + for (i = 0; i < osd_count; i++) { + for (j = 0; j < osd_count; j++) { if (order[i] == org_order[j]) { if (osd_hw.enable[j]) osd_blending.reorder[j] = LAYER_1 + i; @@ -5007,7 +5102,7 @@ static int osd_setting_order(void) postbld_osd2_premult); //spin_lock_irqsave(&osd_lock, lock_flags); - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_count; i++) { adjust_freescale_para(&osd_blending); osd_hw.free_scale[i].h_enable = 1; osd_hw.free_scale[i].v_enable = 1; @@ -5062,7 +5157,7 @@ static int osd_setting_order(void) VSYNCOSD_WR_MPEG_REG_BITS(DOLBY_PATH_CTRL, 0xf, 0, 4); #endif - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_count; i++) { if (osd_hw.enable[i]) ret = osd_setting_blending_scope(i); } @@ -5205,6 +5300,7 @@ static void osd_basic_update_disp_geometry(u32 index) u32 data32; u32 buffer_w, buffer_h; + osd_log_info("osd_basic_update_disp_geometry\n"); data32 = (osd_hw.dispdata[index].x_start & 0xfff) | (osd_hw.dispdata[index].x_end & 0xfff) << 16; VSYNCOSD_WR_MPEG_REG( @@ -5781,7 +5877,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, /* fifo_depth_val: 32 or 64 *8 = 256 or 512 */ data32 |= (osd_hw.osd_meson_dev.osd_fifo_len & 0xfffffff) << 12; - for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count; idx++) + for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count - 1; idx++) osd_reg_write( hw_osd_reg_array[idx].osd_fifo_ctrl_stat, data32); /* osd_reg_write(VIU_OSD2_FIFO_CTRL_STAT, data32_); */ @@ -5800,7 +5896,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, /* just disable osd to avoid booting hang up */ data32 = 0x1 << 0; data32 |= OSD_GLOBAL_ALPHA_DEF << 12; - for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count; idx++) + for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count - 1; idx++) osd_reg_write( hw_osd_reg_array[idx].osd_ctrl_stat, data32); } @@ -5836,21 +5932,29 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, osd_hw.osd_afbcd[idx].afbc_start = 0; osd_hw.afbc_start_in_vsync = 0; osd_hw.afbc_force_reset = 1; - /* TODO: temp set at here, need move it to uboot */ - osd_reg_set_bits( + if (idx < osd_hw.osd_meson_dev.osd_count - 1) { + /* TODO: temp set at here, + * need move it to uboot + */ + osd_reg_set_bits( hw_osd_reg_array[idx].osd_fifo_ctrl_stat, 1, 31, 1); - osd_reg_set_bits( + osd_reg_set_bits( hw_osd_reg_array[idx].osd_fifo_ctrl_stat, 1, 10, 2); - /* TODO: temp set at here, need check for logo */ - if (idx > 0) - osd_reg_set_bits( + /* TODO: temp set at here, + * need check for logo + */ + if (idx > 0) + osd_reg_set_bits( hw_osd_reg_array[idx].osd_ctrl_stat, 0, 0, 1); + osd_hw.powered[idx] = 1; + } else + osd_hw.powered[idx] = 0; #if 0 /* enable for latch */ - osd_hw.osd_use_latch = 1; + osd_hw.osd_use_latch[idx] = 1; data32 = 0; data32 = osd_reg_read( hw_osd_reg_array[idx].osd_ctrl_stat); @@ -5920,11 +6024,12 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, */ osd_set_dummy_data(idx, 0xff); } - osd_hw.fb_gem[OSD1].canvas_idx = OSD1_CANVAS_INDEX; osd_hw.fb_gem[OSD2].canvas_idx = OSD2_CANVAS_INDEX; - if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) + if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { osd_hw.fb_gem[OSD3].canvas_idx = OSD3_CANVAS_INDEX; + osd_hw.fb_gem[OSD4].canvas_idx = OSD4_CANVAS_INDEX; + } osd_extra_canvas_alloc(); osd_hw.antiflicker_mode = 0; osd_hw.osd_deband_enable = 1; @@ -5948,21 +6053,103 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, osd_hw.fiq_handle_item.key = (u32)vsync_isr; osd_hw.fiq_handle_item.name = "osd_vsync"; if (register_fiq_bridge_handle(&osd_hw.fiq_handle_item)) + osd_log_err("can't request irq for vsync,err_num=%d\n", + -err_num); #else err_num = request_irq(int_viu_vsync, &vsync_isr, IRQF_SHARED, "osd-vsync", osd_setup_hw); if (err_num) -#endif osd_log_err("can't request irq for vsync,err_num=%d\n", -err_num); + if (osd_hw.osd_meson_dev.has_viu2) { + err_num = request_irq(int_viu2_vsync, &vsync_viu2_isr, + IRQF_SHARED, "osd-vsync-viu2", osd_setup_hw); + if (err_num) + osd_log_err("can't request irq for vsync,err_num=%d\n", + -err_num); + } +#endif #ifdef FIQ_VSYNC request_fiq(INT_VIU_VSYNC, &osd_fiq_isr); + request_fiq(INT_VIU_VSYNC, &osd_viu2_fiq_isr); #endif } if (osd_hw.hw_rdma_en) osd_rdma_enable(1); } +void osd_init_viu2(void) +{ + u32 idx, data32; + + osd_vpu_power_on_viu2(); + + /* here we will init default value ,these value only set once . */ + /* init vpu fifo control register */ + osd_reg_write(VPP2_OFIFO_SIZE, 0x7ff00800); + /* init osd fifo control register + * set DDR request priority to be urgent + */ + data32 = 1; + data32 |= 4 << 5; /* hold_fifo_lines */ + /* burst_len_sel: 3=64, g12a = 5 */ + if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { + data32 |= 1 << 10; + data32 |= 1 << 31; + } else + data32 |= 3 << 10; + /* + * bit 23:22, fifo_ctrl + * 00 : for 1 word in 1 burst + * 01 : for 2 words in 1 burst + * 10 : for 4 words in 1 burst + * 11 : reserved + */ + data32 |= 2 << 22; + /* bit 28:24, fifo_lim */ + data32 |= 2 << 24; + /* data32_ = data32; */ + /* fifo_depth_val: 32 or 64 *8 = 256 or 512 */ + data32 |= (osd_hw.osd_meson_dev.osd_fifo_len + & 0xfffffff) << 12; + idx = osd_hw.osd_meson_dev.osd_count - 1; + osd_reg_write( + hw_osd_reg_array[idx].osd_fifo_ctrl_stat, data32); + /* osd_reg_write(VIU_OSD2_FIFO_CTRL_STAT, data32_); */ + /* just disable osd to avoid booting hang up */ + data32 = 0x1 << 0; + data32 |= OSD_GLOBAL_ALPHA_DEF << 12; + osd_reg_write( + hw_osd_reg_array[idx].osd_ctrl_stat, data32); + /* TODO: temp set at here, need move it to uboot */ + osd_reg_set_bits( + hw_osd_reg_array[idx].osd_fifo_ctrl_stat, + 1, 31, 1); + osd_reg_set_bits( + hw_osd_reg_array[idx].osd_fifo_ctrl_stat, + 1, 10, 2); + /* TODO: temp set at here, need check for logo */ + if (idx > 0) + osd_reg_set_bits( + hw_osd_reg_array[idx].osd_ctrl_stat, + 0, 0, 1); + /* enable for latch */ + osd_hw.osd_use_latch[idx] = 1; + data32 = 0; + data32 = osd_reg_read( + hw_osd_reg_array[idx].osd_ctrl_stat); + data32 |= 0x80000000; + osd_reg_write( + hw_osd_reg_array[idx].osd_ctrl_stat, data32); + + /* init osd reverse */ + osd_get_reverse_hw(idx, &data32); + if (data32) + osd_set_reverse_hw(idx, data32, 1); + osd_hw.powered[idx] = 1; + +} + void osd_cursor_hw(u32 index, s16 x, s16 y, s16 xstart, s16 ystart, u32 osd_w, u32 osd_h) { diff --git a/drivers/amlogic/media/osd/osd_hw.h b/drivers/amlogic/media/osd/osd_hw.h index 19b5b75..7ad5aee 100644 --- a/drivers/amlogic/media/osd/osd_hw.h +++ b/drivers/amlogic/media/osd/osd_hw.h @@ -28,6 +28,7 @@ #include "osd_rdma.h" extern int int_viu_vsync; +extern int int_viu2_vsync; extern struct hw_para_s osd_hw; #ifdef CONFIG_HIBERNATION @@ -95,7 +96,7 @@ extern void osd_enable_3d_mode_hw(u32 index, u32 enable); extern void osd_set_2x_scale_hw(u32 index, u16 h_scale_enable, u16 v_scale_enable); extern void osd_get_flush_rate_hw(u32 *break_rate); -extern void osd_set_reverse_hw(u32 index, u32 reverse); +extern void osd_set_reverse_hw(u32 index, u32 reverse, u32 update); extern void osd_get_reverse_hw(u32 index, u32 *reverse); extern void osd_set_antiflicker_hw(u32 index, struct vinfo_s *vinfo, u32 yres); extern void osd_get_antiflicker_hw(u32 index, u32 *on_off); @@ -125,6 +126,7 @@ extern void osd_resume_hw(void); extern void osd_shutdown_hw(void); extern void osd_init_hw(u32 logo_loaded, u32 osd_probe, struct osd_device_data_s *osd_meson); +extern void osd_init_viu2(void); extern void osd_init_scan_mode(void); extern void osd_set_logo_index(int index); extern int osd_get_logo_index(void); diff --git a/drivers/amlogic/media/osd/osd_hw_def.h b/drivers/amlogic/media/osd/osd_hw_def.h index 1a29b5c..a0685cc 100644 --- a/drivers/amlogic/media/osd/osd_hw_def.h +++ b/drivers/amlogic/media/osd/osd_hw_def.h @@ -67,7 +67,7 @@ static update_func_t hw_func_array[HW_REG_INDEX_MAX] = { spin_lock_irqsave(&osd_lock, lock_flags); \ raw_local_save_flags(fiq_flag); \ local_fiq_disable(); \ - if (osd_hw.hw_rdma_en || osd_hw.osd_use_latch) \ + if (osd_hw.hw_rdma_en || osd_hw.osd_use_latch[osd_idx]) \ osd_hw.reg[cmd_idx].update_func(osd_idx); \ else \ osd_hw.updated[osd_idx] |= (1<= 0x1e10) && (addr <= 0x1e50)) + rdma_en = 0; + else + rdma_en = 1; + return rdma_en; +} + static inline u32 read_reg_internal(u32 addr) { int i; u32 val = 0; + u32 rdma_en = 0; - if (rdma_enable) { + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; + + if (rdma_en) { for (i = (int)(item_count - 1); i >= 0; i--) { if (addr == rdma_table[i].addr) { @@ -329,8 +346,14 @@ static inline u32 read_reg_internal(u32 addr) static inline int wrtie_reg_internal(u32 addr, u32 val) { struct rdma_table_item request_item; + u32 rdma_en = 0; + + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; - if (!rdma_enable) { + if (!rdma_en) { osd_reg_write(addr, val); return 0; } @@ -363,8 +386,14 @@ u32 VSYNCOSD_RD_MPEG_REG(u32 addr) bool find = false; u32 val = 0; unsigned long flags; + u32 rdma_en = 0; + + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; - if (rdma_enable) { + if (rdma_en) { spin_lock_irqsave(&rdma_lock, flags); /* 1st, read from rdma table */ for (i = (int)(item_count - 1); @@ -391,8 +420,14 @@ EXPORT_SYMBOL(VSYNCOSD_RD_MPEG_REG); int VSYNCOSD_WR_MPEG_REG(u32 addr, u32 val) { int ret = 0; + u32 rdma_en = 0; - if (rdma_enable) + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; + + if (rdma_en) ret = update_table_item(addr, val, 0); else osd_reg_write(addr, val); @@ -405,8 +440,14 @@ int VSYNCOSD_WR_MPEG_REG_BITS(u32 addr, u32 val, u32 start, u32 len) unsigned long read_val; unsigned long write_val; int ret = 0; + u32 rdma_en = 0; - if (rdma_enable) { + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; + + if (rdma_en) { read_val = VSYNCOSD_RD_MPEG_REG(addr); write_val = (read_val & ~(((1L << (len)) - 1) << (start))) | ((unsigned int)(val) << (start)); @@ -422,8 +463,14 @@ int VSYNCOSD_SET_MPEG_REG_MASK(u32 addr, u32 _mask) unsigned long read_val; unsigned long write_val; int ret = 0; + u32 rdma_en = 0; + + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; - if (rdma_enable) { + if (rdma_en) { read_val = VSYNCOSD_RD_MPEG_REG(addr); write_val = read_val | _mask; ret = update_table_item(addr, write_val, 0); @@ -438,8 +485,14 @@ int VSYNCOSD_CLR_MPEG_REG_MASK(u32 addr, u32 _mask) unsigned long read_val; unsigned long write_val; int ret = 0; + u32 rdma_en = 0; + + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; - if (rdma_enable) { + if (rdma_en) { read_val = VSYNCOSD_RD_MPEG_REG(addr); write_val = read_val & (~_mask); ret = update_table_item(addr, write_val, 0); @@ -452,8 +505,14 @@ EXPORT_SYMBOL(VSYNCOSD_CLR_MPEG_REG_MASK); int VSYNCOSD_IRQ_WR_MPEG_REG(u32 addr, u32 val) { int ret = 0; + u32 rdma_en = 0; + + if (!is_rdma_reg(addr)) + rdma_en = 0; + else + rdma_en = rdma_enable; - if (rdma_enable) + if (rdma_en) ret = update_table_item(addr, val, 1); else osd_reg_write(addr, val); diff --git a/drivers/amlogic/media/osd/osd_reg.h b/drivers/amlogic/media/osd/osd_reg.h index 36f3182..9e11f87 100644 --- a/drivers/amlogic/media/osd/osd_reg.h +++ b/drivers/amlogic/media/osd/osd_reg.h @@ -19,124 +19,11 @@ #define _OSD_REG_H_ /* vpp2 */ -#define VPP2_DUMMY_DATA 0x1900 -#define VPP2_LINE_IN_LENGTH 0x1901 -#define VPP2_PIC_IN_HEIGHT 0x1902 -#define VPP2_SCALE_COEF_IDX 0x1903 -#define VPP2_SCALE_COEF 0x1904 -#define VPP2_VSC_REGION12_STARTP 0x1905 -#define VPP2_VSC_REGION34_STARTP 0x1906 -#define VPP2_VSC_REGION4_ENDP 0x1907 -#define VPP2_VSC_START_PHASE_STEP 0x1908 -#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 -#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a -#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b -#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c -#define VPP2_VSC_PHASE_CTRL 0x190d -#define VPP2_VSC_INI_PHASE 0x190e -#define VPP2_HSC_REGION12_STARTP 0x1910 -#define VPP2_HSC_REGION34_STARTP 0x1911 -#define VPP2_HSC_REGION4_ENDP 0x1912 -#define VPP2_HSC_START_PHASE_STEP 0x1913 -#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 -#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 -#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 -#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 -#define VPP2_HSC_PHASE_CTRL 0x1918 -#define VPP2_SC_MISC 0x1919 -#define VPP2_PREBLEND_VD1_H_START_END 0x191a -#define VPP2_PREBLEND_VD1_V_START_END 0x191b -#define VPP2_POSTBLEND_VD1_H_START_END 0x191c -#define VPP2_POSTBLEND_VD1_V_START_END 0x191d -#define VPP2_PREBLEND_H_SIZE 0x1920 +#define VPP2_MISC 0x1e26 +#define VPP2_OFIFO_SIZE 0x1e27 +#define VPP2_INT_LINE_NUM 0x1e20 +#define VPP2_OFIFO_URG_CTRL 0x1e21 #define VPP2_POSTBLEND_H_SIZE 0x1921 -#define VPP2_HOLD_LINES 0x1922 -#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 -#define VPP2_PREBLEND_CURRENT_XY 0x1924 -#define VPP2_POSTBLEND_CURRENT_XY 0x1925 -#define VPP2_MISC 0x1926 -#define VPP2_OFIFO_SIZE 0x1927 -#define VPP2_FIFO_STATUS 0x1928 -#define VPP2_SMOKE_CTRL 0x1929 -#define VPP2_SMOKE1_VAL 0x192a -#define VPP2_SMOKE2_VAL 0x192b -#define VPP2_SMOKE1_H_START_END 0x192d -#define VPP2_SMOKE1_V_START_END 0x192e -#define VPP2_SMOKE2_H_START_END 0x192f -#define VPP2_SMOKE2_V_START_END 0x1930 -#define VPP2_SCO_FIFO_CTRL 0x1933 -#define VPP2_HSC_PHASE_CTRL1 0x1934 -#define VPP2_HSC_INI_PAT_CTRL 0x1935 -#define VPP2_VADJ_CTRL 0x1940 -#define VPP2_VADJ1_Y 0x1941 -#define VPP2_VADJ1_MA_MB 0x1942 -#define VPP2_VADJ1_MC_MD 0x1943 -#define VPP2_VADJ2_Y 0x1944 -#define VPP2_VADJ2_MA_MB 0x1945 -#define VPP2_VADJ2_MC_MD 0x1946 -#define VPP2_MATRIX_PROBE_COLOR 0x195c -#define VPP2_MATRIX_HL_COLOR 0x195d -#define VPP2_MATRIX_PROBE_POS 0x195e -#define VPP2_MATRIX_CTRL 0x195f -#define VPP2_MATRIX_COEF00_01 0x1960 -#define VPP2_MATRIX_COEF02_10 0x1961 -#define VPP2_MATRIX_COEF11_12 0x1962 -#define VPP2_MATRIX_COEF20_21 0x1963 -#define VPP2_MATRIX_COEF22 0x1964 -#define VPP2_MATRIX_OFFSET0_1 0x1965 -#define VPP2_MATRIX_OFFSET2 0x1966 -#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 -#define VPP2_MATRIX_PRE_OFFSET2 0x1968 -#define VPP2_DUMMY_DATA1 0x1969 -#define VPP2_GAINOFF_CTRL0 0x196a -#define VPP2_GAINOFF_CTRL1 0x196b -#define VPP2_GAINOFF_CTRL2 0x196c -#define VPP2_GAINOFF_CTRL3 0x196d -#define VPP2_GAINOFF_CTRL4 0x196e -#define VPP2_CHROMA_ADDR_PORT 0x1970 -#define VPP2_CHROMA_DATA_PORT 0x1971 -#define VPP2_GCLK_CTRL0 0x1972 -#define VPP2_GCLK_CTRL1 0x1973 -#define VPP2_SC_GCLK_CTRL 0x1974 -#define VPP2_MISC1 0x1976 -#define VPP2_DNLP_CTRL_00 0x1981 -#define VPP2_DNLP_CTRL_01 0x1982 -#define VPP2_DNLP_CTRL_02 0x1983 -#define VPP2_DNLP_CTRL_03 0x1984 -#define VPP2_DNLP_CTRL_04 0x1985 -#define VPP2_DNLP_CTRL_05 0x1986 -#define VPP2_DNLP_CTRL_06 0x1987 -#define VPP2_DNLP_CTRL_07 0x1988 -#define VPP2_DNLP_CTRL_08 0x1989 -#define VPP2_DNLP_CTRL_09 0x198a -#define VPP2_DNLP_CTRL_10 0x198b -#define VPP2_DNLP_CTRL_11 0x198c -#define VPP2_DNLP_CTRL_12 0x198d -#define VPP2_DNLP_CTRL_13 0x198e -#define VPP2_DNLP_CTRL_14 0x198f -#define VPP2_DNLP_CTRL_15 0x1990 -#define VPP2_VE_ENABLE_CTRL 0x19a1 -#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 -#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 -#define VPP2_VE_H_V_SIZE 0x19a4 -#define VPP2_VDO_MEAS_CTRL 0x19a8 -#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 -#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa -#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 -#define VPP2_OSD_VSC_INI_PHASE 0x19c1 -#define VPP2_OSD_VSC_CTRL0 0x19c2 -#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 -#define VPP2_OSD_HSC_INI_PHASE 0x19c4 -#define VPP2_OSD_HSC_CTRL0 0x19c5 -#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 -#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 -#define VPP2_OSD_SC_CTRL0 0x19c8 -#define VPP2_OSD_SCI_WH_M1 0x19c9 -#define VPP2_OSD_SCO_H_START_END 0x19ca -#define VPP2_OSD_SCO_V_START_END 0x19cb -#define VPP2_OSD_SCALE_COEF_IDX 0x19cc -#define VPP2_OSD_SCALE_COEF 0x19cd -#define VPP2_INT_LINE_NUM 0x19ce /* viu */ #define VIU_ADDR_START 0x1a00 @@ -541,102 +428,47 @@ #define VIU2_ADDR_START 0x1e00 #define VIU2_ADDR_END 0x1eff #define VIU2_SW_RESET 0x1e01 -#define VIU2_OSD1_CTRL_STAT 0x1e10 -#define VIU2_OSD1_CTRL_STAT2 0x1e2d -#define VIU2_OSD1_COLOR_ADDR 0x1e11 -#define VIU2_OSD1_COLOR 0x1e12 -#define VIU2_OSD1_TCOLOR_AG0 0x1e17 -#define VIU2_OSD1_TCOLOR_AG1 0x1e18 -#define VIU2_OSD1_TCOLOR_AG2 0x1e19 -#define VIU2_OSD1_TCOLOR_AG3 0x1e1a -#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b -#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f -#define VIU2_OSD1_BLK2_CFG_W0 0x1e23 -#define VIU2_OSD1_BLK3_CFG_W0 0x1e27 -#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c -#define VIU2_OSD1_BLK1_CFG_W1 0x1e20 -#define VIU2_OSD1_BLK2_CFG_W1 0x1e24 -#define VIU2_OSD1_BLK3_CFG_W1 0x1e28 -#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d -#define VIU2_OSD1_BLK1_CFG_W2 0x1e21 -#define VIU2_OSD1_BLK2_CFG_W2 0x1e25 -#define VIU2_OSD1_BLK3_CFG_W2 0x1e29 -#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e -#define VIU2_OSD1_BLK1_CFG_W3 0x1e22 -#define VIU2_OSD1_BLK2_CFG_W3 0x1e26 -#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a -#define VIU2_OSD1_BLK0_CFG_W4 0x1e13 -#define VIU2_OSD1_BLK1_CFG_W4 0x1e14 -#define VIU2_OSD1_BLK2_CFG_W4 0x1e15 -#define VIU2_OSD1_BLK3_CFG_W4 0x1e16 -#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b -#define VIU2_OSD1_TEST_RDDATA 0x1e2c -#define VIU2_OSD1_PROT_CTRL 0x1e2e -#define VIU2_OSD2_CTRL_STAT 0x1e30 -#define VIU2_OSD2_CTRL_STAT2 0x1e4d -#define VIU2_OSD2_COLOR_ADDR 0x1e31 -#define VIU2_OSD2_COLOR 0x1e32 -#define VIU2_OSD2_HL1_H_START_END 0x1e33 -#define VIU2_OSD2_HL1_V_START_END 0x1e34 -#define VIU2_OSD2_HL2_H_START_END 0x1e35 -#define VIU2_OSD2_HL2_V_START_END 0x1e36 -#define VIU2_OSD2_TCOLOR_AG0 0x1e37 -#define VIU2_OSD2_TCOLOR_AG1 0x1e38 -#define VIU2_OSD2_TCOLOR_AG2 0x1e39 -#define VIU2_OSD2_TCOLOR_AG3 0x1e3a -#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b -#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f -#define VIU2_OSD2_BLK2_CFG_W0 0x1e43 -#define VIU2_OSD2_BLK3_CFG_W0 0x1e47 -#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c -#define VIU2_OSD2_BLK1_CFG_W1 0x1e40 -#define VIU2_OSD2_BLK2_CFG_W1 0x1e44 -#define VIU2_OSD2_BLK3_CFG_W1 0x1e48 -#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d -#define VIU2_OSD2_BLK1_CFG_W2 0x1e41 -#define VIU2_OSD2_BLK2_CFG_W2 0x1e45 -#define VIU2_OSD2_BLK3_CFG_W2 0x1e49 -#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e -#define VIU2_OSD2_BLK1_CFG_W3 0x1e42 -#define VIU2_OSD2_BLK2_CFG_W3 0x1e46 -#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a -#define VIU2_OSD2_BLK0_CFG_W4 0x1e64 -#define VIU2_OSD2_BLK1_CFG_W4 0x1e65 -#define VIU2_OSD2_BLK2_CFG_W4 0x1e66 -#define VIU2_OSD2_BLK3_CFG_W4 0x1e67 -#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b -#define VIU2_OSD2_TEST_RDDATA 0x1e4c -#define VIU2_OSD2_PROT_CTRL 0x1e4e - - -#define VIU2_VD1_IF0_GEN_REG 0x1e50 -#define VIU2_VD1_IF0_CANVAS0 0x1e51 -#define VIU2_VD1_IF0_CANVAS1 0x1e52 -#define VIU2_VD1_IF0_LUMA_X0 0x1e53 -#define VIU2_VD1_IF0_LUMA_Y0 0x1e54 -#define VIU2_VD1_IF0_CHROMA_X0 0x1e55 -#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 -#define VIU2_VD1_IF0_LUMA_X1 0x1e57 -#define VIU2_VD1_IF0_LUMA_Y1 0x1e58 -#define VIU2_VD1_IF0_CHROMA_X1 0x1e59 -#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a -#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b -#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c -#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d -#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e -#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f -#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 -#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 -#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 -#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 -#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a -#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b -#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c -#define VIU2_VD1_IF0_GEN_REG2 0x1e6d -#define VIU2_VD1_IF0_PROT_CNTL 0x1e6e -#define VIU2_VD1_FMT_CTRL 0x1e68 -#define VIU2_VD1_FMT_W 0x1e69 - +#define VIU2_SW_RESET0 0x1e02 +#define VIU2_SECURE_REG 0x1e05 +#define VIU2_MISC_CTRL0 0x1e06 +#define VIU2_OSD1_CTRL_STAT 0x1e30 +#define VIU2_OSD1_CTRL_STAT2 0x1e4d +#define VIU2_OSD1_COLOR_ADDR 0x1e31 +#define VIU2_OSD1_COLOR 0x1e32 +#define VIU2_OSD1_HL1_H_START_END 0x1e33 +#define VIU2_OSD1_HL1_V_START_END 0x1e34 +#define VIU2_OSD1_HL2_H_START_END 0x1e35 +#define VIU2_OSD1_HL2_V_START_END 0x1e36 +#define VIU2_OSD1_TCOLOR_AG0 0x1e37 +#define VIU2_OSD1_TCOLOR_AG1 0x1e38 +#define VIU2_OSD1_TCOLOR_AG2 0x1e39 +#define VIU2_OSD1_TCOLOR_AG3 0x1e3a +#define VIU2_OSD1_BLK0_CFG_W0 0x1e3b +#define VIU2_OSD1_BLK1_CFG_W0 0x1e3f +#define VIU2_OSD1_BLK2_CFG_W0 0x1e43 +#define VIU2_OSD1_BLK3_CFG_W0 0x1e47 +#define VIU2_OSD1_BLK0_CFG_W1 0x1e3c +#define VIU2_OSD1_BLK1_CFG_W1 0x1e40 +#define VIU2_OSD1_BLK2_CFG_W1 0x1e44 +#define VIU2_OSD1_BLK3_CFG_W1 0x1e48 +#define VIU2_OSD1_BLK0_CFG_W2 0x1e3d +#define VIU2_OSD1_BLK1_CFG_W2 0x1e41 +#define VIU2_OSD1_BLK2_CFG_W2 0x1e45 +#define VIU2_OSD1_BLK3_CFG_W2 0x1e49 +#define VIU2_OSD1_BLK0_CFG_W3 0x1e3e +#define VIU2_OSD1_BLK1_CFG_W3 0x1e42 +#define VIU2_OSD1_BLK2_CFG_W3 0x1e46 +#define VIU2_OSD1_BLK3_CFG_W3 0x1e4a +#define VIU2_OSD1_BLK0_CFG_W4 0x1e64 +#define VIU2_OSD1_BLK1_CFG_W4 0x1e65 +#define VIU2_OSD1_BLK2_CFG_W4 0x1e66 +#define VIU2_OSD1_BLK3_CFG_W4 0x1e67 +#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e4b +#define VIU2_OSD1_TEST_RDDATA 0x1e4c +#define VIU2_OSD1_PROT_CTRL 0x1e4e +#define VIU2_OSD1_MALI_UNPACK_CTRL 0x1e4f +#define VIU2_OSD1_DIMM_CTRL 0x1e50 +#define VIU2_OSD1_UNSUPPORT VIU_OSD2_TCOLOR_AG3 /* encode */ #define ENCP_VFIFO2VD_CTL 0x1b58 #define ENCP_VFIFO2VD_PIXEL_START 0x1b59 diff --git a/drivers/amlogic/media/osd/osd_sync.h b/drivers/amlogic/media/osd/osd_sync.h index 3ac2885..a7e7935 100644 --- a/drivers/amlogic/media/osd/osd_sync.h +++ b/drivers/amlogic/media/osd/osd_sync.h @@ -31,6 +31,7 @@ struct fb_sync_request_s { int out_fen_fd; }; +#if 0 struct fb_sync_request_render_s { unsigned int xoffset; unsigned int yoffset; @@ -51,3 +52,30 @@ struct fb_sync_request_render_s { unsigned int reserve; }; #endif +struct fb_sync_request_render_s { +unsigned int xoffset; +unsigned int yoffset; +int in_fen_fd; +int out_fen_fd; +int width; +int height; +int format; +int shared_fd; +unsigned int op; +unsigned int type; /*direct render or ge2d*/ +unsigned int dst_x; +unsigned int dst_y; +unsigned int dst_w; +unsigned int dst_h; +int byte_stride; +int pxiel_stride; +unsigned int background_w; +unsigned int background_h; +unsigned int zorder; +unsigned int premult_en; +unsigned int afbc_en; +unsigned int afbc_inter_format; +int reserve; +}; + +#endif diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h index b5e5dc8..d4a0b89 100644 --- a/include/dt-bindings/clock/amlogic,g12a-clkc.h +++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h @@ -236,8 +236,17 @@ #define CLKID_HEVCF_P1_GATE (CLKID_MEDIA_BASE + 58) #define CLKID_HEVCF_P1_COMP (CLKID_MEDIA_BASE + 59) #define CLKID_HEVCF_MUX (CLKID_MEDIA_BASE + 60) +#define CLKID_VPU_CLKC_P0_MUX (CLKID_MEDIA_BASE + 61) +#define CLKID_VPU_CLKC_P0_DIV (CLKID_MEDIA_BASE + 62) +#define CLKID_VPU_CLKC_P0_GATE (CLKID_MEDIA_BASE + 63) +#define CLKID_VPU_CLKC_P0_COMP (CLKID_MEDIA_BASE + 64) +#define CLKID_VPU_CLKC_P1_MUX (CLKID_MEDIA_BASE + 65) +#define CLKID_VPU_CLKC_P1_DIV (CLKID_MEDIA_BASE + 66) +#define CLKID_VPU_CLKC_P1_GATE (CLKID_MEDIA_BASE + 67) +#define CLKID_VPU_CLKC_P1_COMP (CLKID_MEDIA_BASE + 68) +#define CLKID_VPU_CLKC_MUX (CLKID_MEDIA_BASE + 69) -#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 61) +#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 70) #define CLKID_SPICC0_MUX (CLKID_MISC_BASE + 0) #define CLKID_SPICC0_DIV (CLKID_MISC_BASE + 1) #define CLKID_SPICC0_GATE (CLKID_MISC_BASE + 2) diff --git a/include/linux/amlogic/media/registers/regs/vpp_regs.h b/include/linux/amlogic/media/registers/regs/vpp_regs.h index 8606219..447a1ef 100644 --- a/include/linux/amlogic/media/registers/regs/vpp_regs.h +++ b/include/linux/amlogic/media/registers/regs/vpp_regs.h @@ -189,124 +189,12 @@ #define VPP_OSD_SCALE_COEF_IDX 0x1dcc #define VPP_OSD_SCALE_COEF 0x1dcd #define VPP_INT_LINE_NUM 0x1dce -#define VPP2_DUMMY_DATA 0x1900 -#define VPP2_LINE_IN_LENGTH 0x1901 -#define VPP2_PIC_IN_HEIGHT 0x1902 -#define VPP2_SCALE_COEF_IDX 0x1903 -#define VPP2_SCALE_COEF 0x1904 -#define VPP2_VSC_REGION12_STARTP 0x1905 -#define VPP2_VSC_REGION34_STARTP 0x1906 -#define VPP2_VSC_REGION4_ENDP 0x1907 -#define VPP2_VSC_START_PHASE_STEP 0x1908 -#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 -#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a -#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b -#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c -#define VPP2_VSC_PHASE_CTRL 0x190d -#define VPP2_VSC_INI_PHASE 0x190e -#define VPP2_HSC_REGION12_STARTP 0x1910 -#define VPP2_HSC_REGION34_STARTP 0x1911 -#define VPP2_HSC_REGION4_ENDP 0x1912 -#define VPP2_HSC_START_PHASE_STEP 0x1913 -#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 -#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 -#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 -#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 -#define VPP2_HSC_PHASE_CTRL 0x1918 -#define VPP2_SC_MISC 0x1919 -#define VPP2_PREBLEND_VD1_H_START_END 0x191a -#define VPP2_PREBLEND_VD1_V_START_END 0x191b -#define VPP2_POSTBLEND_VD1_H_START_END 0x191c -#define VPP2_POSTBLEND_VD1_V_START_END 0x191d -#define VPP2_PREBLEND_H_SIZE 0x1920 -#define VPP2_POSTBLEND_H_SIZE 0x1921 -#define VPP2_HOLD_LINES 0x1922 -#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 -#define VPP2_PREBLEND_CURRENT_XY 0x1924 -#define VPP2_POSTBLEND_CURRENT_XY 0x1925 -#define VPP2_MISC 0x1926 -#define VPP2_OFIFO_SIZE 0x1927 -#define VPP2_FIFO_STATUS 0x1928 -#define VPP2_SMOKE_CTRL 0x1929 -#define VPP2_SMOKE1_VAL 0x192a -#define VPP2_SMOKE2_VAL 0x192b -#define VPP2_SMOKE1_H_START_END 0x192d -#define VPP2_SMOKE1_V_START_END 0x192e -#define VPP2_SMOKE2_H_START_END 0x192f -#define VPP2_SMOKE2_V_START_END 0x1930 -#define VPP2_SCO_FIFO_CTRL 0x1933 -#define VPP2_HSC_PHASE_CTRL1 0x1934 -#define VPP2_HSC_INI_PAT_CTRL 0x1935 -#define VPP2_VADJ_CTRL 0x1940 -#define VPP2_VADJ1_Y 0x1941 -#define VPP2_VADJ1_MA_MB 0x1942 -#define VPP2_VADJ1_MC_MD 0x1943 -#define VPP2_VADJ2_Y 0x1944 -#define VPP2_VADJ2_MA_MB 0x1945 -#define VPP2_VADJ2_MC_MD 0x1946 -#define VPP2_MATRIX_PROBE_COLOR 0x195c -#define VPP2_MATRIX_HL_COLOR 0x195d -#define VPP2_MATRIX_PROBE_POS 0x195e -#define VPP2_MATRIX_CTRL 0x195f -#define VPP2_MATRIX_COEF00_01 0x1960 -#define VPP2_MATRIX_COEF02_10 0x1961 -#define VPP2_MATRIX_COEF11_12 0x1962 -#define VPP2_MATRIX_COEF20_21 0x1963 -#define VPP2_MATRIX_COEF22 0x1964 -#define VPP2_MATRIX_OFFSET0_1 0x1965 -#define VPP2_MATRIX_OFFSET2 0x1966 -#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 -#define VPP2_MATRIX_PRE_OFFSET2 0x1968 -#define VPP2_DUMMY_DATA1 0x1969 -#define VPP2_GAINOFF_CTRL0 0x196a -#define VPP2_GAINOFF_CTRL1 0x196b -#define VPP2_GAINOFF_CTRL2 0x196c -#define VPP2_GAINOFF_CTRL3 0x196d -#define VPP2_GAINOFF_CTRL4 0x196e -#define VPP2_CHROMA_ADDR_PORT 0x1970 -#define VPP2_CHROMA_DATA_PORT 0x1971 -#define VPP2_GCLK_CTRL0 0x1972 -#define VPP2_GCLK_CTRL1 0x1973 -#define VPP2_SC_GCLK_CTRL 0x1974 -#define VPP2_MISC1 0x1976 -#define VPP2_DNLP_CTRL_00 0x1981 -#define VPP2_DNLP_CTRL_01 0x1982 -#define VPP2_DNLP_CTRL_02 0x1983 -#define VPP2_DNLP_CTRL_03 0x1984 -#define VPP2_DNLP_CTRL_04 0x1985 -#define VPP2_DNLP_CTRL_05 0x1986 -#define VPP2_DNLP_CTRL_06 0x1987 -#define VPP2_DNLP_CTRL_07 0x1988 -#define VPP2_DNLP_CTRL_08 0x1989 -#define VPP2_DNLP_CTRL_09 0x198a -#define VPP2_DNLP_CTRL_10 0x198b -#define VPP2_DNLP_CTRL_11 0x198c -#define VPP2_DNLP_CTRL_12 0x198d -#define VPP2_DNLP_CTRL_13 0x198e -#define VPP2_DNLP_CTRL_14 0x198f -#define VPP2_DNLP_CTRL_15 0x1990 -#define VPP2_VE_ENABLE_CTRL 0x19a1 -#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 -#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 -#define VPP2_VE_H_V_SIZE 0x19a4 -#define VPP2_VDO_MEAS_CTRL 0x19a8 -#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 -#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa -#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 -#define VPP2_OSD_VSC_INI_PHASE 0x19c1 -#define VPP2_OSD_VSC_CTRL0 0x19c2 -#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 -#define VPP2_OSD_HSC_INI_PHASE 0x19c4 -#define VPP2_OSD_HSC_CTRL0 0x19c5 -#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 -#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 -#define VPP2_OSD_SC_CTRL0 0x19c8 -#define VPP2_OSD_SCI_WH_M1 0x19c9 -#define VPP2_OSD_SCO_H_START_END 0x19ca -#define VPP2_OSD_SCO_V_START_END 0x19cb -#define VPP2_OSD_SCALE_COEF_IDX 0x19cc -#define VPP2_OSD_SCALE_COEF 0x19cd -#define VPP2_INT_LINE_NUM 0x19ce + +#define VPP2_MISC 0x1e26 +#define VPP2_OFIFO_SIZE 0x1e27 +#define VPP2_INT_LINE_NUM 0x1e20 +#define VPP2_OFIFO_URG_CTRL 0x1e21 + #define SRSHARP0_SHARP_HVSIZE 0x3200 #define SRSHARP0_SHARP_HVBLANK_NUM 0x3201 #define SRSHARP0_SHARP_PK_NR_ENABLE 0x3227