From: Changhwan Youn Date: Tue, 4 Oct 2011 08:08:56 +0000 (+0900) Subject: ARM: EXYNOS4: Add support clock for EXYNOS4412 X-Git-Tag: v3.2-rc1~40^2~11^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b88b1cc72e2bbb55c56f2df55b5ad59a18ad1464;p=platform%2Fkernel%2Flinux-exynos.git ARM: EXYNOS4: Add support clock for EXYNOS4412 This patch makes EXYNOS4412 use same clock code for EXYNOS4212 because the clock hierarchy of both SoCs are same. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index f26aea3..2a037cc 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1149,7 +1149,7 @@ static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) if (soc_is_exynos4210()) return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); - else if (soc_is_exynos4212()) + else if (soc_is_exynos4212() || soc_is_exynos4412()) return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0)); else return 0; @@ -1200,7 +1200,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1), pll_4650c); - } else if (soc_is_exynos4212()) { + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),