From: Wu Zhangjin Date: Tue, 13 Apr 2010 05:16:34 +0000 (+0800) Subject: MIPS: Loongson: update cpu-feature-overrides.h X-Git-Tag: v2.6.35-rc1~443^2~23 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b8853aa3d912f47f649ad8de784ac3afd932437d;p=platform%2Fkernel%2Flinux-3.10.git MIPS: Loongson: update cpu-feature-overrides.h Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin Cc: Linux-MIPS Patchwork: http://patchwork.linux-mips.org/patch/1112/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 16210ce..675bd86 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -52,6 +52,8 @@ #define cpu_has_tx39_cache 0 #define cpu_has_userlocal 0 #define cpu_has_vce 0 +#define cpu_has_veic 0 +#define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1