From: Colin LeMahieu Date: Fri, 30 Jan 2015 20:08:37 +0000 (+0000) Subject: [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests. X-Git-Tag: llvmorg-3.7.0-rc1~13583 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b84ec022967e56c8e748dd37b1872948e222a1f4;p=platform%2Fupstream%2Fllvm.git [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests. llvm-svn: 227607 --- diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index a269315..255643a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2469,6 +2469,43 @@ def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>; def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>; } +//===----------------------------------------------------------------------===// +// Template Class -- Vector Multipy +// Used for complex multiply real or imaginary, dual multiply and even halfwords +//===----------------------------------------------------------------------===// +class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift, + bit isRnd, bit isSat > + : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") + #!if(isRnd,":rnd","") + #!if(isSat,":sat",""), + [] > { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1000; + let Inst{23-21} = MajOp; + let Inst{7-5} = MinOp; + let Inst{4-0} = Rdd; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat +let Defs = [USR_OVF], isCodeGenOnly = 0 in { +def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>; +def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>; +} + +// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat +let isCodeGenOnly = 0 in { +def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>; +def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>; +} + let hasNewValue = 1, opNewValue = 0 in class T_MType_mpy RegTyBits, RegisterClass RC, bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0, @@ -2495,6 +2532,9 @@ class T_MType_mpy RegTyBits, RegisterClass RC, let Inst{4-0} = dst; } +class T_MType_vrcmpy MajOp, bits<3> MinOp, bit isHi> + : T_MType_mpy ; + class T_MType_dd MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0 > : T_MType_mpy ; @@ -2526,6 +2566,13 @@ def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">; def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">; } +let isCodeGenOnly = 0 in { +def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>; +def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>; +def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">; +def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">; +} + // V4 Instructions let isCodeGenOnly = 0 in { def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>; @@ -2761,6 +2808,55 @@ def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>; let isCodeGenOnly = 0 in def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">; +// Vector reduce complex multiply real or imaginary: +// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) +let isCodeGenOnly = 0 in { +def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>; +def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>; +def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>; +def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>; +} + +let isCodeGenOnly = 0 in { +def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>; +def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>; +def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>; +def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>; +} + +//===----------------------------------------------------------------------===// +// Template Class -- Vector Multipy with accumulation. +// Used for complex multiply real or imaginary, dual multiply and even halfwords +//===----------------------------------------------------------------------===// +let Defs = [USR_OVF] in +class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp, + bit hasShift, bit isRnd > + : MInst <(outs DoubleRegs:$Rxx), + (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") + #!if(isRnd,":rnd","")#":sat", + [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { + bits<5> Rxx; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1010; + let Inst{23-21} = MajOp; + let Inst{7-5} = MinOp; + let Inst{4-0} = Rxx; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +// Vector complex multiply real or imaginary with accumulation +// Rxx+=vcmpy[ir](Rss,Rtt):sat +let isCodeGenOnly = 0 in { +def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>; +def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>; +} + //===----------------------------------------------------------------------===// // Template Class -- Multiply signed/unsigned halfwords with and without // saturation and rounding @@ -2890,6 +2986,47 @@ def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>; def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>; def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>; } +// Complex multiply real or imaginary +// Rxx=cmpy[ir](Rs,Rt) +let isCodeGenOnly = 0 in { +def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>; +def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>; +} + +// Rxx+=cmpy[ir](Rs,Rt) +let isCodeGenOnly = 0 in { +def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>; +def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>; +} + +// Complex multiply +// Rdd=cmpy(Rs,Rt)[:<<]:sat +let isCodeGenOnly = 0 in { +def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>; +def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>; +} + +// Rdd=cmpy(Rs,Rt*)[:<<]:sat +let isCodeGenOnly = 0 in { +def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>; +def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>; +} + +// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat +let isCodeGenOnly = 0 in { +def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>; +def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>; +def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>; +def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>; +} + +// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat +let isCodeGenOnly = 0 in { +def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>; +def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>; +def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>; +def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>; +} def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))), (i64 (anyext (i32 IntRegs:$src2))))), @@ -3741,6 +3878,10 @@ def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>; def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>; } +// Vector Complex conjugate +let isCodeGenOnly = 0 in +def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>; + // Vector absolute value halfwords with and without saturation // Rdd64=vabsh(Rss64)[:sat] let isCodeGenOnly = 0 in { @@ -5411,6 +5552,31 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in { def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>; } +let hasNewValue = 1, hasSideEffects = 0 in +class T_S3op_8 MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0> + : SInst < (outs IntRegs:$Rd), + (ins DoubleRegs:$Rss, IntRegs:$Rt), + "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")" + #!if(hasShift, ":<<1", "") + #!if(isRnd, ":rnd", "") + #!if(isSat, ":sat", ""), + [], "", S_3op_tc_1_SLOT23 > { + bits<5> Rd; + bits<5> Rss; + bits<5> Rt; + + let IClass = 0b1100; + + let Inst{27-24} = 0b0101; + let Inst{20-16} = Rss; + let Inst{12-8} = Rt; + let Inst{7-5} = MinOp; + let Inst{4-0} = Rd; + } + +let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in +def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>; + //===----------------------------------------------------------------------===// // Template class for 'insert bitfield' instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td index 76d4d83..f363b9a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td @@ -195,3 +195,62 @@ def : Pat<(callv3nr tglobaladdr:$dst), (CALLv3nr tglobaladdr:$dst)>, Requires<[HasV3T]>; def : Pat<(callv3nr texternalsym:$dst), (CALLv3nr texternalsym:$dst)>, Requires<[HasV3T]>; + +//===----------------------------------------------------------------------===// +// :raw form of vrcmpys:hi/lo insns +//===----------------------------------------------------------------------===// +// Vector reduce complex multiply by scalar. +let Defs = [USR_OVF], hasSideEffects = 0 in +class T_vrcmpRawMajOp>: + MInst<(outs DoubleRegs:$Rdd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1000; + let Inst{23-21} = MajOp; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + let Inst{7-5} = 0b100; + let Inst{4-0} = Rdd; +} + +let isCodeGenOnly = 0 in { +def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>; +def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>; +} + +// Vector reduce complex multiply by scalar with accumulation. +let Defs = [USR_OVF], hasSideEffects = 0 in +class T_vrcmpys_accMajOp>: + MInst <(outs DoubleRegs:$Rxx), + (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [], + "$Rxx = $_src_"> { + bits<5> Rxx; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1010; + let Inst{23-21} = MajOp; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + let Inst{7-5} = 0b100; + let Inst{4-0} = Rxx; + } + +let isCodeGenOnly = 0 in { +def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>; +def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>; +} + +let isCodeGenOnly = 0 in { +def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>; +def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>; +} diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index c8faa2d..3b90d48 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1741,6 +1741,19 @@ let hasNewValue = 1, isCodeGenOnly = 0 in { def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>; } +// Complex add/sub halfwords/words +let Defs = [USR_OVF], isCodeGenOnly = 0 in { + def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>; + def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>; + def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>; + def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>; +} + +let Defs = [USR_OVF], isCodeGenOnly = 0 in { + def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>; + def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>; +} + let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in { def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>; def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>; @@ -1769,6 +1782,53 @@ def M4_xor_xacc let Inst{4-0} = Rxx; } +// Rotate and reduce bytes +// Rdd=vrcrotate(Rss,Rt,#u2) +let hasSideEffects = 0, isCodeGenOnly = 0 in +def S4_vrcrotate + : SInst <(outs DoubleRegs:$Rdd), + (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2), + "$Rdd = vrcrotate($Rss, $Rt, #$u2)", + [], "", S_3op_tc_3x_SLOT23> { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rt; + bits<2> u2; + + let IClass = 0b1100; + + let Inst{27-22} = 0b001111; + let Inst{20-16} = Rss; + let Inst{13} = u2{1}; + let Inst{12-8} = Rt; + let Inst{7-6} = 0b11; + let Inst{5} = u2{0}; + let Inst{4-0} = Rdd; + } + +// Rotate and reduce bytes with accumulation +// Rxx+=vrcrotate(Rss,Rt,#u2) +let hasSideEffects = 0, isCodeGenOnly = 0 in +def S4_vrcrotate_acc + : SInst <(outs DoubleRegs:$Rxx), + (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2), + "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [], + "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> { + bits<5> Rxx; + bits<5> Rss; + bits<5> Rt; + bits<2> u2; + + let IClass = 0b1100; + + let Inst{27-21} = 0b1011101; + let Inst{20-16} = Rss; + let Inst{13} = u2{1}; + let Inst{12-8} = Rt; + let Inst{5} = u2{0}; + let Inst{4-0} = Rxx; + } + // Vector reduce conditional negate halfwords let hasSideEffects = 0, isCodeGenOnly = 0 in @@ -2284,6 +2344,12 @@ let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>; +// Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat +let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in { + def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>; + def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>; +} + // Rdd=[add|sub](Rss,Rtt,Px):carry let isPredicateLate = 1, hasSideEffects = 0 in class T_S3op_carry MajOp> diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td index b2d87cd..39c6244 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td @@ -765,6 +765,12 @@ def S5_asrhub_rnd_sat_goodsyntax : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4), "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>; +// Complex multiply 32x16 +let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in { + def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>; + def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>; +} + // Classify floating-point value let isFP = 1, isCodeGenOnly = 0 in def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>; diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt index 1b8e5c5..89b6906 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt @@ -1,5 +1,7 @@ -# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s +# Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT +# Count leading 0x11 0xc0 0x54 0x88 # CHECK: r17 = clb(r21:20) 0x51 0xc0 0x54 0x88 @@ -20,8 +22,12 @@ # CHECK: r17 = cl1(r21) 0xf1 0xc0 0x15 0x8c # CHECK: r17 = normamt(r21) + +# Count population 0x71 0xc0 0x74 0x88 # CHECK: r17 = popcount(r21:20) + +# Count trailing 0x51 0xc0 0xf4 0x88 # CHECK: r17 = ct0(r21:20) 0x91 0xc0 0xf4 0x88 @@ -30,6 +36,8 @@ # CHECK: r17 = ct0(r21) 0xb1 0xc0 0x55 0x8c # CHECK: r17 = ct1(r21) + +# Extract bitfield 0xf0 0xdf 0x54 0x81 # CHECK: r17:16 = extractu(r21:20, #31, #23) 0xf0 0xdf 0x54 0x8a @@ -46,6 +54,8 @@ # CHECK: r17 = extractu(r21, r31:30) 0x51 0xde 0x15 0xc9 # CHECK: r17 = extract(r21, r31:30) + +# Insert bitfield 0xf0 0xdf 0x54 0x83 # CHECK: r17:16 = insert(r21:20, #31, #23) 0xf1 0xdf 0x55 0x8f @@ -54,20 +64,30 @@ # CHECK: r17 = insert(r21, r31:30) 0x10 0xde 0x14 0xca # CHECK: r17:16 = insert(r21:20, r31:30) + +# Interleave/deinterleave 0x90 0xc0 0xd4 0x80 # CHECK: r17:16 = deinterleave(r21:20) 0xb0 0xc0 0xd4 0x80 # CHECK: r17:16 = interleave(r21:20) + +# Linear feedback-shift iteration 0xd0 0xde 0x94 0xc1 # CHECK: r17:16 = lfs(r21:20, r31:30) + +# Masked parity 0x11 0xde 0x14 0xd0 # CHECK: r17 = parity(r21:20, r31:30) 0x11 0xdf 0xf5 0xd5 # CHECK: r17 = parity(r21, r31) + +# Bit reverse 0xd0 0xc0 0xd4 0x80 # CHECK: r17:16 = brev(r21:20) 0xd1 0xc0 0x55 0x8c # CHECK: r17 = brev(r21) + +# Set/clear/toggle bit 0x11 0xdf 0xd5 0x8c # CHECK: r17 = setbit(r21, #31) 0x31 0xdf 0xd5 0x8c @@ -80,10 +100,14 @@ # CHECK: r17 = clrbit(r21, r31) 0x91 0xdf 0x95 0xc6 # CHECK: r17 = togglebit(r21, r31) + +# Split bitfield 0x90 0xdf 0xd5 0x88 # CHECK: r17:16 = bitsplit(r21, #31) 0x10 0xdf 0x35 0xd4 # CHECK: r17:16 = bitsplit(r21, r31) + +# Table index 0xf1 0xcd 0x15 0x87 # CHECK: r17 = tableidxb(r21, #7, #13):raw 0xf1 0xcd 0x55 0x87 diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_complex.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_complex.txt new file mode 100644 index 0000000..2332082 --- /dev/null +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_complex.txt @@ -0,0 +1,128 @@ +# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s +# Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX + +# Complex add/sub halfwords +0x90 0xde 0x54 0xc1 +# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat +0xd0 0xde 0x54 0xc1 +# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat +0x10 0xde 0xd4 0xc1 +# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat +0x50 0xde 0xd4 0xc1 +# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat + +# Complex add/sub words +0x10 0xde 0x54 0xc1 +# CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat +0x50 0xde 0x54 0xc1 +# CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat + +# Complex multiply +0xd0 0xdf 0x15 0xe5 +# CHECK: r17:16 = cmpy(r21, r31):sat +0xd0 0xdf 0x95 0xe5 +# CHECK: r17:16 = cmpy(r21, r31):<<1:sat +0xd0 0xdf 0x55 0xe5 +# CHECK: r17:16 = cmpy(r21, r31*):sat +0xd0 0xdf 0xd5 0xe5 +# CHECK: r17:16 = cmpy(r21, r31*):<<1:sat +0xd0 0xdf 0x15 0xe7 +# CHECK: r17:16 += cmpy(r21, r31):sat +0xd0 0xdf 0x95 0xe7 +# CHECK: r17:16 += cmpy(r21, r31):<<1:sat +0xf0 0xdf 0x15 0xe7 +# CHECK: r17:16 -= cmpy(r21, r31):sat +0xf0 0xdf 0x95 0xe7 +# CHECK: r17:16 -= cmpy(r21, r31):<<1:sat +0xd0 0xdf 0x55 0xe7 +# CHECK: r17:16 += cmpy(r21, r31*):sat +0xd0 0xdf 0xd5 0xe7 +# CHECK: r17:16 += cmpy(r21, r31*):<<1:sat +0xf0 0xdf 0x55 0xe7 +# CHECK: r17:16 -= cmpy(r21, r31*):sat +0xf0 0xdf 0xd5 0xe7 +# CHECK: r17:16 -= cmpy(r21, r31*):<<1:sat + +# Complex multiply real or imaginary +0x30 0xdf 0x15 0xe5 +# CHECK: r17:16 = cmpyi(r21, r31) +0x50 0xdf 0x15 0xe5 +# CHECK: r17:16 = cmpyr(r21, r31) +0x30 0xdf 0x15 0xe7 +# CHECK: r17:16 += cmpyi(r21, r31) +0x50 0xdf 0x15 0xe7 +# CHECK: r17:16 += cmpyr(r21, r31) + +# Complex multiply with round and pack +0xd1 0xdf 0x35 0xed +# CHECK: r17 = cmpy(r21, r31):rnd:sat +0xd1 0xdf 0xb5 0xed +# CHECK: r17 = cmpy(r21, r31):<<1:rnd:sat +0xd1 0xdf 0x75 0xed +# CHECK: r17 = cmpy(r21, r31*):rnd:sat +0xd1 0xdf 0xf5 0xed +# CHECK: r17 = cmpy(r21, r31*):<<1:rnd:sat + +# Complex multiply 32x16 +0x91 0xdf 0x14 0xc5 +# CHECK: r17 = cmpyiwh(r21:20, r31):<<1:rnd:sat +0xb1 0xdf 0x14 0xc5 +# CHECK: r17 = cmpyiwh(r21:20, r31*):<<1:rnd:sat +0xd1 0xdf 0x14 0xc5 +# CHECK: r17 = cmpyrwh(r21:20, r31):<<1:rnd:sat +0xf1 0xdf 0x14 0xc5 +# CHECK: r17 = cmpyrwh(r21:20, r31*):<<1:rnd:sat + +# Vector complex multiply real or imaginary +0xd0 0xde 0x34 0xe8 +# CHECK: r17:16 = vcmpyr(r21:20, r31:30):sat +0xd0 0xde 0xb4 0xe8 +# CHECK: r17:16 = vcmpyr(r21:20, r31:30):<<1:sat +0xd0 0xde 0x54 0xe8 +# CHECK: r17:16 = vcmpyi(r21:20, r31:30):sat +0xd0 0xde 0xd4 0xe8 +# CHECK: r17:16 = vcmpyi(r21:20, r31:30):<<1:sat +0x90 0xde 0x34 0xea +# CHECK: r17:16 += vcmpyr(r21:20, r31:30):sat +0x90 0xde 0x54 0xea +# CHECK: r17:16 += vcmpyi(r21:20, r31:30):sat + +# Vector complex conjugate +0xf0 0xc0 0x94 0x80 +# CHECK: r17:16 = vconj(r21:20):sat + +# Vector complex rotate +0x10 0xdf 0xd4 0xc3 +# CHECK: r17:16 = vcrotate(r21:20, r31) + +# Vector reduce complex multiply real or imaginary +0x10 0xde 0x14 0xe8 +# CHECK: r17:16 = vrcmpyi(r21:20, r31:30) +0x30 0xde 0x14 0xe8 +# CHECK: r17:16 = vrcmpyr(r21:20, r31:30) +0x10 0xde 0x54 0xe8 +# CHECK: r17:16 = vrcmpyi(r21:20, r31:30*) +0x30 0xde 0x74 0xe8 +# CHECK: r17:16 = vrcmpyr(r21:20, r31:30*) + +# Vector reduce complex multiply by scalar +0x90 0xde 0xb4 0xe8 +# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:hi +0x90 0xde 0xf4 0xe8 +# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:lo +0x90 0xde 0xb4 0xea +# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:hi +0x90 0xde 0xf4 0xea +# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:lo + +# Vector reduce complex multiply by scalar with round and pack +0xd1 0xde 0xb4 0xe9 +# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:hi +0xf1 0xde 0xb4 0xe9 +# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:lo + +# Vector reduce complex rotate +0xf0 0xff 0xd4 0xc3 +# CHECK: r17:16 = vrcrotate(r21:20, r31, #3) +0x30 0xff 0xb4 0xcb +# CHECK: r17:16 += vrcrotate(r21:20, r31, #3)