From: Icenowy Zheng <uwu@icenowy.me>
Date: Mon, 12 Dec 2022 08:22:38 +0000 (+0800)
Subject: lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible
X-Git-Tag: v1.2~4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b848d8763a737de44b64bfc036c8f51200226440;p=platform%2Fkernel%2Fopensbi.git

lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

As we already added the quirk for lacking mtime register to MTIMER
driver, add T-Head C9xx CLINT compatible to it and wire the quirk.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Anup Patel <anup@brainfault.org>
---

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index a0adc70..5244f98 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -124,9 +124,15 @@ static const struct timer_mtimer_quirks sifive_clint_quirks = {
 	.has_64bit_mmio	= true,
 };
 
+static const struct timer_mtimer_quirks thead_clint_quirks = {
+	.mtime_offset	= CLINT_MTIMER_OFFSET,
+	.without_mtime  = true,
+};
+
 static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
+	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };