From: Abel Vesa Date: Thu, 28 Feb 2019 21:42:44 +0000 (+0000) Subject: arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores X-Git-Tag: v5.4-rc1~968^2~1^2~37 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b810641a34702a747cb47e2cc1ecaa20f374868e;p=platform%2Fkernel%2Flinux-rpi.git arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores The clocks and their latencies will be used by cpufreq-dt. Signed-off-by: Abel Vesa Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 6a1cc18..07f7dff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -87,6 +87,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -95,6 +97,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -103,6 +107,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -111,6 +117,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; };