From: Maxime Ripard Date: Thu, 3 Sep 2020 08:01:01 +0000 (+0200) Subject: drm/vc4: crtc: Add a delay after disabling the PixelValve output X-Git-Tag: v5.10.7~1332^2~3^2~196 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b7cb67a6b4fbb99a297bb0a57d906f56d81b29c9;p=platform%2Fkernel%2Flinux-rpi.git drm/vc4: crtc: Add a delay after disabling the PixelValve output In order to avoid pixels getting stuck in the (unflushable) FIFO between the HVS and the PV, we need to add some delay after disabling the PV output and before disabling the HDMI controller. 20ms seems to be good enough so let's use that. Signed-off-by: Maxime Ripard Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Reviewed-by: Dave Stevenson Link: https://patchwork.freedesktop.org/patch/msgid/15cf215bd2ceebd203c4010c09c21a4019c650ed.1599120059.git-series.maxime@cerno.tech --- diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index d0b326e..4c23cf8 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -403,6 +403,24 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + /* + * This delay is needed to avoid to get a pixel stuck in an + * unflushable FIFO between the pixelvalve and the HDMI + * controllers on the BCM2711. + * + * Timing is fairly sensitive here, so mdelay is the safest + * approach. + * + * If it was to be reworked, the stuck pixel happens on a + * BCM2711 when changing mode with a good probability, so a + * script that changes mode on a regular basis should trigger + * the bug after less than 10 attempts. It manifests itself with + * every pixels being shifted by one to the right, and thus the + * last pixel of a line actually being displayed as the first + * pixel on the next line. + */ + mdelay(20); + if (vc4_encoder->post_crtc_disable) vc4_encoder->post_crtc_disable(encoder);