From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 26 Feb 2021 23:13:25 +0000 (-0600)
Subject: intel/mi_builder: add a way to reserve a register
X-Git-Tag: upstream/22.3.5~2239
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b7296e11ae97c9c8d361622b1aab2c8d6922cb62;p=platform%2Fupstream%2Fmesa.git

intel/mi_builder: add a way to reserve a register

Will be useful for GRL metakernels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
---

diff --git a/src/intel/common/mi_builder.h b/src/intel/common/mi_builder.h
index 7bb5dcc..5913899 100644
--- a/src/intel/common/mi_builder.h
+++ b/src/intel/common/mi_builder.h
@@ -226,6 +226,21 @@ mi_new_gpr(struct mi_builder *b)
       .reg = _MI_BUILDER_GPR_BASE + gpr * 8,
    };
 }
+
+static inline struct mi_value
+mi_reserve_gpr(struct mi_builder *b, unsigned gpr)
+{
+   assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS);
+   assert(!(b->gprs & (1 << gpr)));
+   assert(b->gpr_refs[gpr] == 0);
+   b->gprs |= (1u << gpr);
+   b->gpr_refs[gpr] = 128; /* Enough that we won't unref it */
+
+   return (struct mi_value) {
+      .type = MI_VALUE_TYPE_REG64,
+      .reg = _MI_BUILDER_GPR_BASE + gpr * 8,
+   };
+}
 #endif /* GFX_VERx10 >= 75 */
 
 /** Take a reference to a mi_value