From: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed, 10 May 2017 09:45:53 +0000 (-0700)
Subject: i965: Use a line end cap width of 0.5 unless smooth lines enabled.
X-Git-Tag: upstream/18.1.0~8790
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b6d56c747cbce7b9ca297be1c6f2c2b7ca91842d;p=platform%2Fupstream%2Fmesa.git

i965: Use a line end cap width of 0.5 unless smooth lines enabled.

This updates the Gen4-5 code to use a line end cap width of 0.5
for non-smooth lines, and 1.0 for smooth lines - which is what we
do on Gen6+.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 78ed71e..0c3cbce 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -126,9 +126,10 @@ static void upload_sf_unit( struct brw_context *brw )
    /* _NEW_LINE */
    sf->sf6.line_width = U_FIXED(brw_get_line_width(brw), 1);
 
-   sf->sf6.line_endcap_aa_region_width = 1;
-   if (ctx->Line.SmoothFlag)
+   if (ctx->Line.SmoothFlag) {
       sf->sf6.aa_enable = 1;
+      sf->sf6.line_endcap_aa_region_width = 1;
+   }
 
    sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;