From: Tom St Denis Date: Wed, 16 Sep 2020 16:17:04 +0000 (-0400) Subject: drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700 X-Git-Tag: v5.10.7~1332^2~18^2~15 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b6c91dadaffee8bf253b0b5ac26a2638c388c6c6;p=platform%2Fkernel%2Flinux-rpi.git drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700 This register was requested for umr debugging support. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h index 07aceff..524ba44 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h @@ -151,6 +151,8 @@ #define mmUVD_LMI_CTRL2_BASE_IDX 1 #define mmUVD_MASTINT_EN 0x0540 #define mmUVD_MASTINT_EN_BASE_IDX 1 +#define mmUVD_FW_STATUS 0x0557 +#define mmUVD_FW_STATUS_BASE_IDX 1 #define mmJPEG_CGC_CTRL 0x0565 #define mmJPEG_CGC_CTRL_BASE_IDX 1 #define mmUVD_LMI_CTRL 0x0566 @@ -219,4 +221,5 @@ #define mmUVD_CONTEXT_ID2_BASE_IDX 1 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h index b427f73..919be18 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h @@ -807,5 +807,25 @@ #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL +//UVD_FW_STATUS +#define UVD_FW_STATUS__BUSY__SHIFT 0x0 +#define UVD_FW_STATUS__ACTIVE__SHIFT 0x1 +#define UVD_FW_STATUS__SEND_EFUSE_REQ__SHIFT 0x2 +#define UVD_FW_STATUS__DONE__SHIFT 0x8 +#define UVD_FW_STATUS__PASS__SHIFT 0x10 +#define UVD_FW_STATUS__FAIL__SHIFT 0x11 +#define UVD_FW_STATUS__INVALID_LEN__SHIFT 0x12 +#define UVD_FW_STATUS__INVALID_0_PADDING__SHIFT 0x13 +#define UVD_FW_STATUS__INVALID_NONCE__SHIFT 0x14 +#define UVD_FW_STATUS__BUSY_MASK 0x00000001L +#define UVD_FW_STATUS__ACTIVE_MASK 0x00000002L +#define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK 0x00000004L +#define UVD_FW_STATUS__DONE_MASK 0x00000100L +#define UVD_FW_STATUS__PASS_MASK 0x00010000L +#define UVD_FW_STATUS__FAIL_MASK 0x00020000L +#define UVD_FW_STATUS__INVALID_LEN_MASK 0x00040000L +#define UVD_FW_STATUS__INVALID_0_PADDING_MASK 0x00080000L +#define UVD_FW_STATUS__INVALID_NONCE_MASK 0x00100000L + #endif