From: steven <steven@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 18 Jun 2004 19:38:27 +0000 (+0000)
Subject: 	* config/xtensa/xtensa.c
X-Git-Tag: upstream/4.9.2~70458
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b62f19183f58ae736ca9e010efd8cbc1f176cbb6;p=platform%2Fupstream%2Flinaro-gcc.git

	* config/xtensa/xtensa.c
	(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define.
	* xtensa.md: Replace the old pipeline description with a DFA model.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@83358 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82865eb..014cb1c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,10 @@
 2004-06-18  Steven Bosscher  <stevenb@suse.de>
+
+	* config/xtensa/xtensa.c
+	(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define.
+	* xtensa.md: Replace the old pipeline description with a DFA model.
+
+2004-06-18  Steven Bosscher  <stevenb@suse.de>
 	    Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
 
 	* config/s390/s390.md: Remove the generic pipeline description.
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 89d8c9d..e062fd9 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -259,6 +259,9 @@ static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
 #undef TARGET_RETURN_IN_MSB
 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
 
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 0b557c1..2bb2672 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -52,20 +52,41 @@
   [(set_attr "type" "multi")])
 
 
-;; Functional units.
+;; Pipeline model.
 
-(define_function_unit "memory" 1 0 (eq_attr "type" "load,fload") 2 0)
+;; The Xtensa basically has simple 5-stage RISC pipeline.
+;; Most instructions complete in 1 cycle, and it is OK to assume that
+;; everything is fully pipelined.  The exceptions have special insn
+;; reservations in the pipeline description below.  The Xtensa can
+;; issue one instruction per cycle, so defining CPU units is unnecessary.
 
-(define_function_unit "sreg" 1 1 (eq_attr "type" "rsr") 2 0)
+(define_insn_reservation "xtensa_any_insn" 1
+			 (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
+			 "nothing")
 
-(define_function_unit "mul16" 1 0 (eq_attr "type" "mul16") 2 0)
+(define_insn_reservation "xtensa_memory" 2
+			 (eq_attr "type" "load,fload")
+			 "nothing")
 
-(define_function_unit "mul32" 1 0 (eq_attr "type" "mul32") 2 0)
+(define_insn_reservation "xtensa_sreg" 2
+			 (eq_attr "type" "rsr")
+			 "nothing")
 
-(define_function_unit "fpmadd" 1 0 (eq_attr "type" "fmadd") 4 0)
+(define_insn_reservation "xtensa_mul16" 2
+			 (eq_attr "type" "mul16")
+			 "nothing")
 
-(define_function_unit "fpconv" 1 0 (eq_attr "type" "fconv") 2 0)
+(define_insn_reservation "xtensa_mul32" 2
+			 (eq_attr "type" "mul32")
+			 "nothing")
 
+(define_insn_reservation "xtensa_fmadd" 4
+			 (eq_attr "type" "fmadd")
+			 "nothing")
+
+(define_insn_reservation "xtensa_fconv" 2
+			 (eq_attr "type" "fconv")
+			 "nothing")
 
 ;; Addition.