From: Craig Topper <craig.topper@gmail.com>
Date: Mon, 17 Apr 2017 01:51:21 +0000 (+0000)
Subject: [InstCombine] Add missing testcases for srem->urem conversion. The vector version... 
X-Git-Tag: llvmorg-5.0.0-rc1~7573
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b60f300afb374c65a90ebc6d96125a33e80f0034;p=platform%2Fupstream%2Fllvm.git

[InstCombine] Add missing testcases for srem->urem conversion. The vector version isn't currently supported. NFC

llvm-svn: 300436
---

diff --git a/llvm/test/Transforms/InstCombine/rem.ll b/llvm/test/Transforms/InstCombine/rem.ll
index 7a7a134..00c020f 100644
--- a/llvm/test/Transforms/InstCombine/rem.ll
+++ b/llvm/test/Transforms/InstCombine/rem.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i64 @rem_signed(i64 %x1, i64 %y2) {
@@ -571,3 +572,24 @@ rem.is.unsafe:
   ret i32 0
 }
 
+define i32 @test22(i32 %A) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[A:%.*]], 2147483647
+; CHECK-NEXT:    [[MUL:%.*]] = urem i32 [[AND]], 2147483647
+; CHECK-NEXT:    ret i32 [[MUL]]
+;
+  %and = and i32 %A, 2147483647
+  %mul = srem i32 %and, 2147483647
+  ret i32 %mul
+}
+
+define <2 x i32> @test23(<2 x i32> %A) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[MUL:%.*]] = srem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+  %mul = srem <2 x i32> %and, <i32 2147483647, i32 2147483647>
+  ret <2 x i32> %mul
+}