From: Greg Kroah-Hartman Date: Tue, 4 Dec 2012 17:22:29 +0000 (-0800) Subject: at91 patches added X-Git-Tag: v3.4.25-ltsi~24 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b5f72d1f70981e6f94668980bc50fd91acb4695b;p=platform%2Fkernel%2Flinux-stable.git at91 patches added --- diff --git a/patches.at91/0001-MAINTAINERS-add-entry-for-Atmel-isi-driver.patch b/patches.at91/0001-MAINTAINERS-add-entry-for-Atmel-isi-driver.patch new file mode 100644 index 000000000000..cf8199884a11 --- /dev/null +++ b/patches.at91/0001-MAINTAINERS-add-entry-for-Atmel-isi-driver.patch @@ -0,0 +1,32 @@ +From f3bd6419099a0cfefc3b13cf95ba34015f06ffb3 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Fri, 23 Mar 2012 17:56:29 +0800 +Subject: MAINTAINERS: add entry for Atmel isi driver + +Signed-off-by: Josh Wu +Signed-off-by: Nicolas Ferre +--- + MAINTAINERS | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index a60009d..c7c725e 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1331,6 +1331,13 @@ M: Nicolas Ferre + S: Supported + F: drivers/tty/serial/atmel_serial.c + ++ATMEL ISI DRIVER ++M: Josh Wu ++L: linux-media@vger.kernel.org ++S: Supported ++F: drivers/media/video/atmel-isi.c ++F: include/media/atmel-isi.h ++ + ATMEL LCDFB DRIVER + M: Nicolas Ferre + L: linux-fbdev@vger.kernel.org +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0002-MAINTAINERS-add-entry-for-Atmel-touch-screen-ADC-con.patch b/patches.at91/0002-MAINTAINERS-add-entry-for-Atmel-touch-screen-ADC-con.patch new file mode 100644 index 000000000000..d4a2238d683a --- /dev/null +++ b/patches.at91/0002-MAINTAINERS-add-entry-for-Atmel-touch-screen-ADC-con.patch @@ -0,0 +1,31 @@ +From ef899cb1d2fda864b02a7efa424767981353f1b5 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Fri, 23 Mar 2012 17:56:55 +0800 +Subject: MAINTAINERS: add entry for Atmel touch screen ADC controller driver + +Signed-off-by: Josh Wu +Signed-off-by: Nicolas Ferre +--- + MAINTAINERS | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index c7c725e..347df81 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1355,6 +1355,12 @@ M: Nicolas Ferre + S: Supported + F: drivers/spi/spi-atmel.* + ++ATMEL TSADCC DRIVER ++M: Josh Wu ++L: linux-input@vger.kernel.org ++S: Supported ++F: drivers/input/touchscreen/atmel_tsadcc.c ++ + ATMEL USBA UDC DRIVER + M: Nicolas Ferre + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0003-MAINTAINERS-add-entry-for-Atmel-DMA-driver.patch b/patches.at91/0003-MAINTAINERS-add-entry-for-Atmel-DMA-driver.patch new file mode 100644 index 000000000000..68b5ddaac06d --- /dev/null +++ b/patches.at91/0003-MAINTAINERS-add-entry-for-Atmel-DMA-driver.patch @@ -0,0 +1,32 @@ +From 2dd30cf629c3267c2925a9925b31addf1ef168b6 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 26 Mar 2012 15:50:36 +0200 +Subject: MAINTAINERS: add entry for Atmel DMA driver + +Signed-off-by: Nicolas Ferre +--- + MAINTAINERS | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 347df81..5d607d2 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1331,6 +1331,14 @@ M: Nicolas Ferre + S: Supported + F: drivers/tty/serial/atmel_serial.c + ++ATMEL DMA DRIVER ++M: Nicolas Ferre ++L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ++S: Supported ++F: drivers/dma/at_hdmac.c ++F: drivers/dma/at_hdmac_regs.h ++F: arch/arm/mach-at91/include/mach/at_hdmac.h ++ + ATMEL ISI DRIVER + M: Josh Wu + L: linux-media@vger.kernel.org +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0004-MAINTAINERS-add-entry-for-Atmel-timer-counter-TC.patch b/patches.at91/0004-MAINTAINERS-add-entry-for-Atmel-timer-counter-TC.patch new file mode 100644 index 000000000000..3f2de362ad97 --- /dev/null +++ b/patches.at91/0004-MAINTAINERS-add-entry-for-Atmel-timer-counter-TC.patch @@ -0,0 +1,34 @@ +From 811046c42ca111ebc64328429ae035f48dddb2fd Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 26 Mar 2012 15:59:32 +0200 +Subject: MAINTAINERS: add entry for Atmel timer counter (TC) + +Add an entry for the Timer Counter (TC) library and the clocksource +driver that is using this library. + +Signed-off-by: Nicolas Ferre +--- + MAINTAINERS | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 5d607d2..54d18b0 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1363,6 +1363,13 @@ M: Nicolas Ferre + S: Supported + F: drivers/spi/spi-atmel.* + ++ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS ++M: Nicolas Ferre ++L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ++S: Supported ++F: drivers/misc/atmel_tclib.c ++F: drivers/clocksource/tcb_clksrc.c ++ + ATMEL TSADCC DRIVER + M: Josh Wu + L: linux-input@vger.kernel.org +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0005-MAINTAINERS-remove-non-responding-web-link-for-atmel.patch b/patches.at91/0005-MAINTAINERS-remove-non-responding-web-link-for-atmel.patch new file mode 100644 index 000000000000..a516b9522b0d --- /dev/null +++ b/patches.at91/0005-MAINTAINERS-remove-non-responding-web-link-for-atmel.patch @@ -0,0 +1,27 @@ +From ff97bdd9bbdcd2f550b68c11d90a3e01873933c7 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 26 Mar 2012 16:11:19 +0200 +Subject: MAINTAINERS: remove non-responding web link for atmel_usba driver + +Signed-off-by: Nicolas Ferre +Cc: Haavard Skinnemoen +Cc: Hans-Christian Egtvedt +--- + MAINTAINERS | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 54d18b0..9c7e7ce 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1379,7 +1379,6 @@ F: drivers/input/touchscreen/atmel_tsadcc.c + ATMEL USBA UDC DRIVER + M: Nicolas Ferre + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +-W: http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver + S: Supported + F: drivers/usb/gadget/atmel_usba_udc.* + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0006-ARM-at91-change-AT91-Kconfig-entry-comment.patch b/patches.at91/0006-ARM-at91-change-AT91-Kconfig-entry-comment.patch new file mode 100644 index 000000000000..d84aa0d952ce --- /dev/null +++ b/patches.at91/0006-ARM-at91-change-AT91-Kconfig-entry-comment.patch @@ -0,0 +1,28 @@ +From cfcd98b36cbb2f074a06b1665727a72d3677ce64 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 12:21:12 +0100 +Subject: ARM: at91: change AT91 Kconfig entry comment + +Signed-off-by: Nicolas Ferre +--- + arch/arm/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 7a8660a..ddef021 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -340,8 +340,8 @@ config ARCH_AT91 + select IRQ_DOMAIN + select NEED_MACH_IO_H if PCCARD + help +- This enables support for systems based on the Atmel AT91RM9200, +- AT91SAM9 processors. ++ This enables support for systems based on Atmel ++ AT91RM9200 and AT91SAM9* processors. + + config ARCH_BCMRING + bool "Broadcom BCMRING" +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0007-ARM-at91-Kconfig-change-at91sam9g45-entry.patch b/patches.at91/0007-ARM-at91-Kconfig-change-at91sam9g45-entry.patch new file mode 100644 index 000000000000..a709d75a03e1 --- /dev/null +++ b/patches.at91/0007-ARM-at91-Kconfig-change-at91sam9g45-entry.patch @@ -0,0 +1,40 @@ +From 4b6fd2b781b2091e70dbfe0d3b3bf5ad70e9664b Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 12:26:43 +0100 +Subject: ARM: at91/Kconfig: change at91sam9g45 entry + +The AT91SAM9G45 entry covers the whole family so we also add the AT91SAM9M10 +name and the "families" qualifier. Then, add a comment to explain which SoCs +are supported by this entry: AT91SAM9G45, AT91SAM9G46 but also +AT91SAM9M10 and AT91SAM9M11. + +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 45db05d..dfbc2c5 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -89,13 +89,16 @@ config ARCH_AT91SAM9G20 + select HAVE_NET_MACB + + config ARCH_AT91SAM9G45 +- bool "AT91SAM9G45" ++ bool "AT91SAM9G45 or AT91SAM9M10 families" + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_AT91_USART3 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + select HAVE_AT91_DBGU1 ++ help ++ Select this if you are using one of Atmel's AT91SAM9G45 family SoC. ++ This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + + config ARCH_AT91SAM9X5 + bool "AT91SAM9x5 family" +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0008-ARM-at91-Kconfig-add-comment-to-at91sam9x5-family-en.patch b/patches.at91/0008-ARM-at91-Kconfig-add-comment-to-at91sam9x5-family-en.patch new file mode 100644 index 000000000000..02a7a09d9ede --- /dev/null +++ b/patches.at91/0008-ARM-at91-Kconfig-add-comment-to-at91sam9x5-family-en.patch @@ -0,0 +1,33 @@ +From 780545021feb2796b0595ebb300522c862bafc55 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 12:48:41 +0100 +Subject: ARM: at91/Kconfig: add comment to at91sam9x5 family entry + +Add comment to make it clear that several SoC are supported by +this generic entry. + +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index dfbc2c5..cad7a15 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -107,6 +107,12 @@ config ARCH_AT91SAM9X5 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + select HAVE_AT91_DBGU0 ++ help ++ Select this if you are using one of Atmel's AT91SAM9x5 family SoC. ++ This means that your SAM9 name finishes with a '5' (except if it is ++ AT91SAM9G45!). ++ This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 ++ and AT91SAM9X35. + + config ARCH_AT91X40 + bool "AT91x40" +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0009-ARM-at91-Kconfig-add-clarifications-to-AT91SAM9M10G4.patch b/patches.at91/0009-ARM-at91-Kconfig-add-clarifications-to-AT91SAM9M10G4.patch new file mode 100644 index 000000000000..d5de31639952 --- /dev/null +++ b/patches.at91/0009-ARM-at91-Kconfig-add-clarifications-to-AT91SAM9M10G4.patch @@ -0,0 +1,34 @@ +From 2eb2471c5bf340e1057c2e5faba6d8b23f6f23e4 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 12:57:03 +0100 +Subject: ARM: at91/Kconfig: add clarifications to AT91SAM9M10G45-EK entry + +Add clarifications about the SoCs that can be found on an AT91SAM9M10G45-EK +board. Add also the web link to this board on Atmel's website. + +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index cad7a15..d2922a1 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -442,9 +442,10 @@ comment "AT91SAM9G45 Board Type" + config MACH_AT91SAM9M10G45EK + bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" + help +- Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. +- "ES" at the end of the name means that this board is an +- Engineering Sample. ++ Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. ++ Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 ++ families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. ++ + + endif + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0010-ARM-at91-Kconfig-add-AT91SAM9x5-family-to-AT91_EARLY.patch b/patches.at91/0010-ARM-at91-Kconfig-add-AT91SAM9x5-family-to-AT91_EARLY.patch new file mode 100644 index 000000000000..48aedef8c201 --- /dev/null +++ b/patches.at91/0010-ARM-at91-Kconfig-add-AT91SAM9x5-family-to-AT91_EARLY.patch @@ -0,0 +1,26 @@ +From f46c2a68a6ad0d570c5c8894d8589cb91f0e2d5f Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 13:49:21 +0100 +Subject: ARM: at91/Kconfig: add AT91SAM9x5 family to AT91_EARLY_DBGU0 entry + +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index d2922a1..e0b8b10 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -529,7 +529,7 @@ choice + prompt "Select a UART for early kernel messages" + + config AT91_EARLY_DBGU0 +- bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl" ++ bool "DBGU on rm9200, 9260/9g20, 9261/9g10, 9rl and 9x5" + depends on HAVE_AT91_DBGU0 + + config AT91_EARLY_DBGU1 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0011-ARM-at91-Kconfig-website-link-for-AT91SAM9G20-EK.patch b/patches.at91/0011-ARM-at91-Kconfig-website-link-for-AT91SAM9G20-EK.patch new file mode 100644 index 000000000000..f43f496e1e49 --- /dev/null +++ b/patches.at91/0011-ARM-at91-Kconfig-website-link-for-AT91SAM9G20-EK.patch @@ -0,0 +1,25 @@ +From 761e63c4d6f8cbf48f12bc90aff9083eefb37e2c Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 13:56:44 +0100 +Subject: ARM: at91/Kconfig: website link for AT91SAM9G20-EK + +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index e0b8b10..8acc164 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -373,6 +373,7 @@ config MACH_AT91SAM9G20EK_2MMC + Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit + with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and + onwards. ++ + + config MACH_CPU9G20 + bool "Eukrea CPU9G20 board" +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0012-rtc-Kconfig-remove-dependency-for-AT91-rtc-driver.patch b/patches.at91/0012-rtc-Kconfig-remove-dependency-for-AT91-rtc-driver.patch new file mode 100644 index 000000000000..dd918d05e054 --- /dev/null +++ b/patches.at91/0012-rtc-Kconfig-remove-dependency-for-AT91-rtc-driver.patch @@ -0,0 +1,30 @@ +From aa2c1a9a69b0a74992d2e4d129f69f58c9b9c433 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 14:38:09 +0100 +Subject: rtc: Kconfig: remove dependency for AT91 rtc driver + +This will allow to select this driver for newer SoCs. +Keep dependency on AT91 because of the use of an header +file located in include/mach directory. + +Signed-off-by: Nicolas Ferre +--- + drivers/rtc/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index 8c8377d..4161bfe 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -838,7 +838,7 @@ config RTC_DRV_AT32AP700X + + config RTC_DRV_AT91RM9200 + tristate "AT91RM9200 or some AT91SAM9 RTC" +- depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 ++ depends on ARCH_AT91 + help + Driver for the internal RTC (Realtime Clock) module found on + Atmel AT91RM9200's and some AT91SAM9 chips. On AT91SAM9 chips +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0013-Input-Kconfig-remove-dependency-for-atmel_tsadcc-dri.patch b/patches.at91/0013-Input-Kconfig-remove-dependency-for-atmel_tsadcc-dri.patch new file mode 100644 index 000000000000..f79ccb33435e --- /dev/null +++ b/patches.at91/0013-Input-Kconfig-remove-dependency-for-atmel_tsadcc-dri.patch @@ -0,0 +1,35 @@ +From 3f06a6301f2cba15b6e6f60283c5910f6383ed3f Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 16:02:02 +0100 +Subject: Input: Kconfig: remove dependency for atmel_tsadcc driver + +This will allow to select this driver for newer SoCs. +Keep dependency on AT91 because of the use of an header +file located in include/mach directory. + +Signed-off-by: Nicolas Ferre +Acked-by: Dmitry Torokhov +--- + drivers/input/touchscreen/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index 2a21419..75838d7 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -489,10 +489,10 @@ config TOUCHSCREEN_TI_TSCADC + + config TOUCHSCREEN_ATMEL_TSADCC + tristate "Atmel Touchscreen Interface" +- depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 ++ depends on ARCH_AT91 + help + Say Y here if you have a 4-wire touchscreen connected to the +- ADC Controller on your Atmel SoC (such as the AT91SAM9RL). ++ ADC Controller on your Atmel SoC. + + If unsure, say N. + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0014-hwrng-Kconfig-remove-dependency-for-atmel-rng-driver.patch b/patches.at91/0014-hwrng-Kconfig-remove-dependency-for-atmel-rng-driver.patch new file mode 100644 index 000000000000..b2703f828ca4 --- /dev/null +++ b/patches.at91/0014-hwrng-Kconfig-remove-dependency-for-atmel-rng-driver.patch @@ -0,0 +1,30 @@ +From 3511638f3d8c7369a85592a17b186482c1057b99 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 15 Mar 2012 16:10:59 +0100 +Subject: hwrng: Kconfig: remove dependency for atmel-rng driver + +This will allow to select this driver for newer SoCs. Make sure to +keep dependency on HAVE_CLK to avoid breaking other machines. + +Signed-off-by: Nicolas Ferre +Acked-by: Herbert Xu +--- + drivers/char/hw_random/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig +index 0689bf6..b2402eb 100644 +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -62,7 +62,7 @@ config HW_RANDOM_AMD + + config HW_RANDOM_ATMEL + tristate "Atmel Random Number Generator support" +- depends on HW_RANDOM && ARCH_AT91SAM9G45 ++ depends on HW_RANDOM && HAVE_CLK + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0015-ARM-at91-uncompress-Store-UART-address-in-a-variable.patch b/patches.at91/0015-ARM-at91-uncompress-Store-UART-address-in-a-variable.patch new file mode 100644 index 000000000000..bc6a63914762 --- /dev/null +++ b/patches.at91/0015-ARM-at91-uncompress-Store-UART-address-in-a-variable.patch @@ -0,0 +1,66 @@ +From d100869e11a7ed455412896d44314a81a386ed42 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Wed, 15 Feb 2012 18:35:40 +0800 +Subject: ARM: at91: uncompress Store UART address in a variable + +This will allow a future change to auto-detect which UART to use. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/include/mach/uncompress.h | 20 +++++++++++--------- + 1 file changed, 11 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h +index 4218647..d985af7 100644 +--- a/arch/arm/mach-at91/include/mach/uncompress.h ++++ b/arch/arm/mach-at91/include/mach/uncompress.h +@@ -43,6 +43,14 @@ + #define UART_OFFSET AT91_USART5 + #endif + ++void __iomem *at91_uart; ++ ++static inline void arch_decomp_setup(void) ++{ ++#ifdef UART_OFFSET ++ at91_uart = (void __iomem *) UART_OFFSET; /* physical address */ ++#endif ++} + /* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in +@@ -53,27 +61,21 @@ + static void putc(int c) + { + #ifdef UART_OFFSET +- void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ +- +- while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) ++ while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + barrier(); +- __raw_writel(c, sys + ATMEL_US_THR); ++ __raw_writel(c, at91_uart + ATMEL_US_THR); + #endif + } + + static inline void flush(void) + { + #ifdef UART_OFFSET +- void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ +- + /* wait for transmission to complete */ +- while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) ++ while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + barrier(); + #endif + } + +-#define arch_decomp_setup() +- + #define arch_decomp_wdog() + + #endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0016-ARM-at91-uncompress-autodetect-the-uart-to-use.patch b/patches.at91/0016-ARM-at91-uncompress-autodetect-the-uart-to-use.patch new file mode 100644 index 000000000000..b54384b26e4b --- /dev/null +++ b/patches.at91/0016-ARM-at91-uncompress-autodetect-the-uart-to-use.patch @@ -0,0 +1,494 @@ +From e740a739f469c0128ad12bf8388cdb69bdccc005 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Wed, 15 Feb 2012 18:44:40 +0800 +Subject: ARM: at91: uncompress: autodetect the uart to use + +This will now autodetect the first uart enabled by the bootloader +and will use it for uncompress. This will still assume that the bootloader +configured it (pins and clock). + +This also allows to include all soc headers together. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 53 -------- + arch/arm/mach-at91/include/mach/at91rm9200.h | 5 - + arch/arm/mach-at91/include/mach/at91sam9260.h | 7 -- + arch/arm/mach-at91/include/mach/at91sam9261.h | 4 - + arch/arm/mach-at91/include/mach/at91sam9263.h | 4 - + arch/arm/mach-at91/include/mach/at91sam9g45.h | 5 - + arch/arm/mach-at91/include/mach/at91sam9rl.h | 5 - + arch/arm/mach-at91/include/mach/at91sam9x5.h | 8 -- + arch/arm/mach-at91/include/mach/hardware.h | 16 +-- + arch/arm/mach-at91/include/mach/uncompress.h | 170 ++++++++++++++++++++++---- + 10 files changed, 148 insertions(+), 129 deletions(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 8acc164..885fdb9 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0 + config HAVE_AT91_DBGU1 + bool + +-config HAVE_AT91_USART3 +- bool +- +-config HAVE_AT91_USART4 +- bool +- +-config HAVE_AT91_USART5 +- bool +- + config AT91_SAM9_ALT_RESET + bool + default !ARCH_AT91X40 +@@ -36,16 +27,12 @@ config ARCH_AT91RM9200 + select CPU_ARM920T + select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 +- select HAVE_AT91_USART3 + + config ARCH_AT91SAM9260 + bool "AT91SAM9260 or AT91SAM9XE" + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 +- select HAVE_AT91_USART3 +- select HAVE_AT91_USART4 +- select HAVE_AT91_USART5 + select HAVE_NET_MACB + + config ARCH_AT91SAM9261 +@@ -74,7 +61,6 @@ config ARCH_AT91SAM9RL + bool "AT91SAM9RL" + select CPU_ARM926T + select GENERIC_CLOCKEVENTS +- select HAVE_AT91_USART3 + select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 + +@@ -83,16 +69,12 @@ config ARCH_AT91SAM9G20 + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 +- select HAVE_AT91_USART3 +- select HAVE_AT91_USART4 +- select HAVE_AT91_USART5 + select HAVE_NET_MACB + + config ARCH_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10 families" + select CPU_ARM926T + select GENERIC_CLOCKEVENTS +- select HAVE_AT91_USART3 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + select HAVE_AT91_DBGU1 +@@ -526,41 +508,6 @@ config AT91_TIMER_HZ + system clock (of at least several MHz), rounding is less of a + problem so it can be safer to use a decimal values like 100. + +-choice +- prompt "Select a UART for early kernel messages" +- +-config AT91_EARLY_DBGU0 +- bool "DBGU on rm9200, 9260/9g20, 9261/9g10, 9rl and 9x5" +- depends on HAVE_AT91_DBGU0 +- +-config AT91_EARLY_DBGU1 +- bool "DBGU on 9263 and 9g45" +- depends on HAVE_AT91_DBGU1 +- +-config AT91_EARLY_USART0 +- bool "USART0" +- +-config AT91_EARLY_USART1 +- bool "USART1" +- +-config AT91_EARLY_USART2 +- bool "USART2" +- depends on ! ARCH_AT91X40 +- +-config AT91_EARLY_USART3 +- bool "USART3" +- depends on HAVE_AT91_USART3 +- +-config AT91_EARLY_USART4 +- bool "USART4" +- depends on HAVE_AT91_USART4 +- +-config AT91_EARLY_USART5 +- bool "USART5" +- depends on HAVE_AT91_USART5 +- +-endchoice +- + endmenu + + endif +diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h +index 603e6aa..e67317c 100644 +--- a/arch/arm/mach-at91/include/mach/at91rm9200.h ++++ b/arch/arm/mach-at91/include/mach/at91rm9200.h +@@ -88,11 +88,6 @@ + #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ + #define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ + +-#define AT91_USART0 AT91RM9200_BASE_US0 +-#define AT91_USART1 AT91RM9200_BASE_US1 +-#define AT91_USART2 AT91RM9200_BASE_US2 +-#define AT91_USART3 AT91RM9200_BASE_US3 +- + /* + * Internal Memory. + */ +diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h +index 08ae9af..416c7b6 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9260.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9260.h +@@ -95,13 +95,6 @@ + #define AT91SAM9260_BASE_WDT 0xfffffd40 + #define AT91SAM9260_BASE_GPBR 0xfffffd50 + +-#define AT91_USART0 AT91SAM9260_BASE_US0 +-#define AT91_USART1 AT91SAM9260_BASE_US1 +-#define AT91_USART2 AT91SAM9260_BASE_US2 +-#define AT91_USART3 AT91SAM9260_BASE_US3 +-#define AT91_USART4 AT91SAM9260_BASE_US4 +-#define AT91_USART5 AT91SAM9260_BASE_US5 +- + + /* + * Internal Memory. +diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h +index 44fbdc1..a041406 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9261.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9261.h +@@ -79,10 +79,6 @@ + #define AT91SAM9261_BASE_WDT 0xfffffd40 + #define AT91SAM9261_BASE_GPBR 0xfffffd50 + +-#define AT91_USART0 AT91SAM9261_BASE_US0 +-#define AT91_USART1 AT91SAM9261_BASE_US1 +-#define AT91_USART2 AT91SAM9261_BASE_US2 +- + + /* + * Internal Memory. +diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h +index d96cbb2..d201029 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9263.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9263.h +@@ -95,10 +95,6 @@ + #define AT91SAM9263_BASE_RTT1 0xfffffd50 + #define AT91SAM9263_BASE_GPBR 0xfffffd60 + +-#define AT91_USART0 AT91SAM9263_BASE_US0 +-#define AT91_USART1 AT91SAM9263_BASE_US1 +-#define AT91_USART2 AT91SAM9263_BASE_US2 +- + #define AT91_SMC AT91_SMC0 + + /* +diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h +index d052abc..3a4da24 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h +@@ -106,11 +106,6 @@ + #define AT91SAM9G45_BASE_RTC 0xfffffdb0 + #define AT91SAM9G45_BASE_GPBR 0xfffffd60 + +-#define AT91_USART0 AT91SAM9G45_BASE_US0 +-#define AT91_USART1 AT91SAM9G45_BASE_US1 +-#define AT91_USART2 AT91SAM9G45_BASE_US2 +-#define AT91_USART3 AT91SAM9G45_BASE_US3 +- + /* + * Internal Memory. + */ +diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h +index e0073eb..a15db56 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h +@@ -89,11 +89,6 @@ + #define AT91SAM9RL_BASE_GPBR 0xfffffd60 + #define AT91SAM9RL_BASE_RTC 0xfffffe00 + +-#define AT91_USART0 AT91SAM9RL_BASE_US0 +-#define AT91_USART1 AT91SAM9RL_BASE_US1 +-#define AT91_USART2 AT91SAM9RL_BASE_US2 +-#define AT91_USART3 AT91SAM9RL_BASE_US3 +- + + /* + * Internal Memory. +diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h +index 88e43d5..c75ee19 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h +@@ -55,14 +55,6 @@ + #define AT91SAM9X5_BASE_USART2 0xf8024000 + + /* +- * Base addresses for early serial code (uncompress.h) +- */ +-#define AT91_DBGU AT91_BASE_DBGU0 +-#define AT91_USART0 AT91SAM9X5_BASE_USART0 +-#define AT91_USART1 AT91SAM9X5_BASE_USART1 +-#define AT91_USART2 AT91SAM9X5_BASE_USART2 +- +-/* + * Internal Memory. + */ + #define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h +index e9e29a6..3a01f8f 100644 +--- a/arch/arm/mach-at91/include/mach/hardware.h ++++ b/arch/arm/mach-at91/include/mach/hardware.h +@@ -22,27 +22,17 @@ + /* 9263, 9g45 */ + #define AT91_BASE_DBGU1 0xffffee00 + +-#if defined(CONFIG_ARCH_AT91RM9200) ++#if defined(CONFIG_ARCH_AT91X40) ++#include ++#else + #include +-#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) + #include +-#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) + #include +-#elif defined(CONFIG_ARCH_AT91SAM9263) + #include +-#elif defined(CONFIG_ARCH_AT91SAM9RL) + #include +-#elif defined(CONFIG_ARCH_AT91SAM9G45) + #include +-#elif defined(CONFIG_ARCH_AT91SAM9X5) + #include +-#elif defined(CONFIG_ARCH_AT91X40) +-#include +-#else +-#error "Unsupported AT91 processor" +-#endif + +-#if !defined(CONFIG_ARCH_AT91X40) + /* + * On all at91 except rm9200 and x40 have the System Controller starts + * at address 0xffffc000 and has a size of 16KiB. +diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h +index d985af7..6f6118d 100644 +--- a/arch/arm/mach-at91/include/mach/uncompress.h ++++ b/arch/arm/mach-at91/include/mach/uncompress.h +@@ -1,7 +1,8 @@ + /* + * arch/arm/mach-at91/include/mach/uncompress.h + * +- * Copyright (C) 2003 SAN People ++ * Copyright (C) 2003 SAN People ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -25,32 +26,149 @@ + #include + #include + +-#if defined(CONFIG_AT91_EARLY_DBGU0) +-#define UART_OFFSET AT91_BASE_DBGU0 +-#elif defined(CONFIG_AT91_EARLY_DBGU1) +-#define UART_OFFSET AT91_BASE_DBGU1 +-#elif defined(CONFIG_AT91_EARLY_USART0) +-#define UART_OFFSET AT91_USART0 +-#elif defined(CONFIG_AT91_EARLY_USART1) +-#define UART_OFFSET AT91_USART1 +-#elif defined(CONFIG_AT91_EARLY_USART2) +-#define UART_OFFSET AT91_USART2 +-#elif defined(CONFIG_AT91_EARLY_USART3) +-#define UART_OFFSET AT91_USART3 +-#elif defined(CONFIG_AT91_EARLY_USART4) +-#define UART_OFFSET AT91_USART4 +-#elif defined(CONFIG_AT91_EARLY_USART5) +-#define UART_OFFSET AT91_USART5 +-#endif ++#include ++#include + + void __iomem *at91_uart; + ++#if !defined(CONFIG_ARCH_AT91X40) ++static const u32 uarts_rm9200[] = { ++ AT91_BASE_DBGU0, ++ AT91RM9200_BASE_US0, ++ AT91RM9200_BASE_US1, ++ AT91RM9200_BASE_US2, ++ AT91RM9200_BASE_US3, ++ 0, ++}; ++ ++static const u32 uarts_sam9260[] = { ++ AT91_BASE_DBGU0, ++ AT91SAM9260_BASE_US0, ++ AT91SAM9260_BASE_US1, ++ AT91SAM9260_BASE_US2, ++ AT91SAM9260_BASE_US3, ++ AT91SAM9260_BASE_US4, ++ AT91SAM9260_BASE_US5, ++ 0, ++}; ++ ++static const u32 uarts_sam9261[] = { ++ AT91_BASE_DBGU0, ++ AT91SAM9261_BASE_US0, ++ AT91SAM9261_BASE_US1, ++ AT91SAM9261_BASE_US2, ++ 0, ++}; ++ ++static const u32 uarts_sam9263[] = { ++ AT91_BASE_DBGU1, ++ AT91SAM9263_BASE_US0, ++ AT91SAM9263_BASE_US1, ++ AT91SAM9263_BASE_US2, ++ 0, ++}; ++ ++static const u32 uarts_sam9g45[] = { ++ AT91_BASE_DBGU1, ++ AT91SAM9G45_BASE_US0, ++ AT91SAM9G45_BASE_US1, ++ AT91SAM9G45_BASE_US2, ++ AT91SAM9G45_BASE_US3, ++ 0, ++}; ++ ++static const u32 uarts_sam9rl[] = { ++ AT91_BASE_DBGU0, ++ AT91SAM9RL_BASE_US0, ++ AT91SAM9RL_BASE_US1, ++ AT91SAM9RL_BASE_US2, ++ AT91SAM9RL_BASE_US3, ++ 0, ++}; ++ ++static const u32 uarts_sam9x5[] = { ++ AT91_BASE_DBGU0, ++ AT91SAM9X5_BASE_USART0, ++ AT91SAM9X5_BASE_USART1, ++ AT91SAM9X5_BASE_USART2, ++ 0, ++}; ++ ++static inline const u32* decomp_soc_detect(u32 dbgu_base) ++{ ++ u32 cidr, socid; ++ ++ cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); ++ socid = cidr & ~AT91_CIDR_VERSION; ++ ++ switch (socid) { ++ case ARCH_ID_AT91RM9200: ++ return uarts_rm9200; ++ ++ case ARCH_ID_AT91SAM9G20: ++ case ARCH_ID_AT91SAM9260: ++ return uarts_sam9260; ++ ++ case ARCH_ID_AT91SAM9261: ++ return uarts_sam9261; ++ ++ case ARCH_ID_AT91SAM9263: ++ return uarts_sam9263; ++ ++ case ARCH_ID_AT91SAM9G45: ++ return uarts_sam9g45; ++ ++ case ARCH_ID_AT91SAM9RL64: ++ return uarts_sam9rl; ++ ++ case ARCH_ID_AT91SAM9X5: ++ return uarts_sam9x5; ++ } ++ ++ /* at91sam9g10 */ ++ if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { ++ return uarts_sam9261; ++ } ++ /* at91sam9xe */ ++ else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { ++ return uarts_sam9260; ++ } ++ ++ return NULL; ++} ++ + static inline void arch_decomp_setup(void) + { +-#ifdef UART_OFFSET +- at91_uart = (void __iomem *) UART_OFFSET; /* physical address */ +-#endif ++ int i = 0; ++ const u32* usarts; ++ ++ usarts = decomp_soc_detect(AT91_BASE_DBGU0); ++ ++ if (!usarts) ++ usarts = decomp_soc_detect(AT91_BASE_DBGU1); ++ if (!usarts) { ++ at91_uart = NULL; ++ return; ++ } ++ ++ do { ++ /* physical address */ ++ at91_uart = (void __iomem *)usarts[i]; ++ ++ if (__raw_readl(at91_uart + ATMEL_US_BRGR)) ++ return; ++ i++; ++ } while (usarts[i]); ++ ++ at91_uart = NULL; + } ++#else ++static inline void arch_decomp_setup(void) ++{ ++ at91_uart = NULL; ++} ++#endif ++ + /* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in +@@ -60,20 +178,22 @@ static inline void arch_decomp_setup(void) + */ + static void putc(int c) + { +-#ifdef UART_OFFSET ++ if (!at91_uart) ++ return; ++ + while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + barrier(); + __raw_writel(c, at91_uart + ATMEL_US_THR); +-#endif + } + + static inline void flush(void) + { +-#ifdef UART_OFFSET ++ if (!at91_uart) ++ return; ++ + /* wait for transmission to complete */ + while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + barrier(); +-#endif + } + + #define arch_decomp_wdog() +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0017-ARM-at91-drop-at91_set_serial_console.patch b/patches.at91/0017-ARM-at91-drop-at91_set_serial_console.patch new file mode 100644 index 000000000000..d394110e4a30 --- /dev/null +++ b/patches.at91/0017-ARM-at91-drop-at91_set_serial_console.patch @@ -0,0 +1,882 @@ +From 9e4b59887ceab4e5a9a311f91da86196106c75c1 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 5 Apr 2012 13:43:40 +0800 +Subject: ARM: at91: drop at91_set_serial_console + +at91_set_serial_console is used to define the default console of linux. +This is already manage by the cmdline. And if the boot loader can not be +modified you can still set it by enabling the CONFIG_CMDLINE_EXTEND option. +And then the command-line arguments provided by the boot loader will be +appended to the default kernel command string. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/at91rm9200.c | 12 ------------ + arch/arm/mach-at91/at91rm9200_devices.c | 12 ------------ + arch/arm/mach-at91/at91sam9260.c | 12 ------------ + arch/arm/mach-at91/at91sam9260_devices.c | 12 ------------ + arch/arm/mach-at91/at91sam9261.c | 12 ------------ + arch/arm/mach-at91/at91sam9261_devices.c | 12 ------------ + arch/arm/mach-at91/at91sam9263.c | 12 ------------ + arch/arm/mach-at91/at91sam9263_devices.c | 12 ------------ + arch/arm/mach-at91/at91sam9g45.c | 12 ------------ + arch/arm/mach-at91/at91sam9g45_devices.c | 12 ------------ + arch/arm/mach-at91/at91sam9rl.c | 12 ------------ + arch/arm/mach-at91/at91sam9rl_devices.c | 12 ------------ + arch/arm/mach-at91/board-1arm.c | 3 --- + arch/arm/mach-at91/board-afeb-9260v1.c | 3 --- + arch/arm/mach-at91/board-cam60.c | 3 --- + arch/arm/mach-at91/board-carmeva.c | 3 --- + arch/arm/mach-at91/board-cpu9krea.c | 3 --- + arch/arm/mach-at91/board-cpuat91.c | 3 --- + arch/arm/mach-at91/board-csb337.c | 3 --- + arch/arm/mach-at91/board-csb637.c | 3 --- + arch/arm/mach-at91/board-eb9200.c | 3 --- + arch/arm/mach-at91/board-ecbat91.c | 3 --- + arch/arm/mach-at91/board-eco920.c | 3 --- + arch/arm/mach-at91/board-flexibity.c | 3 --- + arch/arm/mach-at91/board-foxg20.c | 3 --- + arch/arm/mach-at91/board-kafa.c | 3 --- + arch/arm/mach-at91/board-kb9202.c | 3 --- + arch/arm/mach-at91/board-neocore926.c | 3 --- + arch/arm/mach-at91/board-picotux200.c | 3 --- + arch/arm/mach-at91/board-qil-a9260.c | 4 ---- + arch/arm/mach-at91/board-rm9200dk.c | 3 --- + arch/arm/mach-at91/board-rm9200ek.c | 3 --- + arch/arm/mach-at91/board-rsi-ews.c | 3 --- + arch/arm/mach-at91/board-sam9-l9260.c | 3 --- + arch/arm/mach-at91/board-sam9260ek.c | 3 --- + arch/arm/mach-at91/board-sam9261ek.c | 3 --- + arch/arm/mach-at91/board-sam9263ek.c | 3 --- + arch/arm/mach-at91/board-sam9g20ek.c | 3 --- + arch/arm/mach-at91/board-sam9m10g45ek.c | 3 --- + arch/arm/mach-at91/board-sam9rlek.c | 3 --- + arch/arm/mach-at91/board-snapper9260.c | 1 - + arch/arm/mach-at91/board-stamp9g20.c | 3 --- + arch/arm/mach-at91/board-usb-a926x.c | 3 --- + arch/arm/mach-at91/board-yl-9200.c | 3 --- + arch/arm/mach-at91/generic.h | 11 ----------- + arch/arm/mach-at91/include/mach/board.h | 1 - + 46 files changed, 251 deletions(-) + +diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c +index 364c193..d50da1a 100644 +--- a/arch/arm/mach-at91/at91rm9200.c ++++ b/arch/arm/mach-at91/at91rm9200.c +@@ -258,18 +258,6 @@ static void __init at91rm9200_register_clocks(void) + clk_register(&pck3); + } + +-static struct clk_lookup console_clock_lookup; +- +-void __init at91rm9200_set_console_clock(int id) +-{ +- if (id >= ARRAY_SIZE(usart_clocks_lookups)) +- return; +- +- console_clock_lookup.con_id = "usart"; +- console_clock_lookup.clk = usart_clocks_lookups[id].clk; +- clkdev_add(&console_clock_lookup); +-} +- + /* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ +diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c +index 05774e5..99affb5 100644 +--- a/arch/arm/mach-at91/at91rm9200_devices.c ++++ b/arch/arm/mach-at91/at91rm9200_devices.c +@@ -1152,14 +1152,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) + at91_uarts[portnr] = pdev; + } + +-void __init at91_set_serial_console(unsigned portnr) +-{ +- if (portnr < ATMEL_MAX_UART) { +- atmel_default_console_device = at91_uarts[portnr]; +- at91rm9200_set_console_clock(at91_uarts[portnr]->id); +- } +-} +- + void __init at91_add_device_serial(void) + { + int i; +@@ -1168,13 +1160,9 @@ void __init at91_add_device_serial(void) + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +- +- if (!atmel_default_console_device) +- printk(KERN_INFO "AT91: No default serial console defined.\n"); + } + #else + void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} +-void __init at91_set_serial_console(unsigned portnr) {} + void __init at91_add_device_serial(void) {} + #endif + +diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c +index 46f7742..a27bbec 100644 +--- a/arch/arm/mach-at91/at91sam9260.c ++++ b/arch/arm/mach-at91/at91sam9260.c +@@ -268,18 +268,6 @@ static void __init at91sam9260_register_clocks(void) + clk_register(&pck1); + } + +-static struct clk_lookup console_clock_lookup; +- +-void __init at91sam9260_set_console_clock(int id) +-{ +- if (id >= ARRAY_SIZE(usart_clocks_lookups)) +- return; +- +- console_clock_lookup.con_id = "usart"; +- console_clock_lookup.clk = usart_clocks_lookups[id].clk; +- clkdev_add(&console_clock_lookup); +-} +- + /* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ +diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c +index 5652dde..ad00fe9 100644 +--- a/arch/arm/mach-at91/at91sam9260_devices.c ++++ b/arch/arm/mach-at91/at91sam9260_devices.c +@@ -1229,14 +1229,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) + at91_uarts[portnr] = pdev; + } + +-void __init at91_set_serial_console(unsigned portnr) +-{ +- if (portnr < ATMEL_MAX_UART) { +- atmel_default_console_device = at91_uarts[portnr]; +- at91sam9260_set_console_clock(at91_uarts[portnr]->id); +- } +-} +- + void __init at91_add_device_serial(void) + { + int i; +@@ -1245,13 +1237,9 @@ void __init at91_add_device_serial(void) + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +- +- if (!atmel_default_console_device) +- printk(KERN_INFO "AT91: No default serial console defined.\n"); + } + #else + void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} +-void __init at91_set_serial_console(unsigned portnr) {} + void __init at91_add_device_serial(void) {} + #endif + +diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c +index 7de81e6..c77d503 100644 +--- a/arch/arm/mach-at91/at91sam9261.c ++++ b/arch/arm/mach-at91/at91sam9261.c +@@ -239,18 +239,6 @@ static void __init at91sam9261_register_clocks(void) + clk_register(&hck1); + } + +-static struct clk_lookup console_clock_lookup; +- +-void __init at91sam9261_set_console_clock(int id) +-{ +- if (id >= ARRAY_SIZE(usart_clocks_lookups)) +- return; +- +- console_clock_lookup.con_id = "usart"; +- console_clock_lookup.clk = usart_clocks_lookups[id].clk; +- clkdev_add(&console_clock_lookup); +-} +- + /* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ +diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c +index 4db961a..9295e90 100644 +--- a/arch/arm/mach-at91/at91sam9261_devices.c ++++ b/arch/arm/mach-at91/at91sam9261_devices.c +@@ -1051,14 +1051,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) + at91_uarts[portnr] = pdev; + } + +-void __init at91_set_serial_console(unsigned portnr) +-{ +- if (portnr < ATMEL_MAX_UART) { +- atmel_default_console_device = at91_uarts[portnr]; +- at91sam9261_set_console_clock(at91_uarts[portnr]->id); +- } +-} +- + void __init at91_add_device_serial(void) + { + int i; +@@ -1067,13 +1059,9 @@ void __init at91_add_device_serial(void) + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +- +- if (!atmel_default_console_device) +- printk(KERN_INFO "AT91: No default serial console defined.\n"); + } + #else + void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} +-void __init at91_set_serial_console(unsigned portnr) {} + void __init at91_add_device_serial(void) {} + #endif + +diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c +index ef301be..7fae365 100644 +--- a/arch/arm/mach-at91/at91sam9263.c ++++ b/arch/arm/mach-at91/at91sam9263.c +@@ -255,18 +255,6 @@ static void __init at91sam9263_register_clocks(void) + clk_register(&pck3); + } + +-static struct clk_lookup console_clock_lookup; +- +-void __init at91sam9263_set_console_clock(int id) +-{ +- if (id >= ARRAY_SIZE(usart_clocks_lookups)) +- return; +- +- console_clock_lookup.con_id = "usart"; +- console_clock_lookup.clk = usart_clocks_lookups[id].clk; +- clkdev_add(&console_clock_lookup); +-} +- + /* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ +diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c +index fe99206..dfe5bc0 100644 +--- a/arch/arm/mach-at91/at91sam9263_devices.c ++++ b/arch/arm/mach-at91/at91sam9263_devices.c +@@ -1461,14 +1461,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) + at91_uarts[portnr] = pdev; + } + +-void __init at91_set_serial_console(unsigned portnr) +-{ +- if (portnr < ATMEL_MAX_UART) { +- atmel_default_console_device = at91_uarts[portnr]; +- at91sam9263_set_console_clock(at91_uarts[portnr]->id); +- } +-} +- + void __init at91_add_device_serial(void) + { + int i; +@@ -1477,13 +1469,9 @@ void __init at91_add_device_serial(void) + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +- +- if (!atmel_default_console_device) +- printk(KERN_INFO "AT91: No default serial console defined.\n"); + } + #else + void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} +-void __init at91_set_serial_console(unsigned portnr) {} + void __init at91_add_device_serial(void) {} + #endif + +diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c +index d222f83..f205449 100644 +--- a/arch/arm/mach-at91/at91sam9g45.c ++++ b/arch/arm/mach-at91/at91sam9g45.c +@@ -288,18 +288,6 @@ static void __init at91sam9g45_register_clocks(void) + clk_register(&pck1); + } + +-static struct clk_lookup console_clock_lookup; +- +-void __init at91sam9g45_set_console_clock(int id) +-{ +- if (id >= ARRAY_SIZE(usart_clocks_lookups)) +- return; +- +- console_clock_lookup.con_id = "usart"; +- console_clock_lookup.clk = usart_clocks_lookups[id].clk; +- clkdev_add(&console_clock_lookup); +-} +- + /* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ +diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c +index 6b008ae..db2f88c2 100644 +--- a/arch/arm/mach-at91/at91sam9g45_devices.c ++++ b/arch/arm/mach-at91/at91sam9g45_devices.c +@@ -1741,14 +1741,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) + at91_uarts[portnr] = pdev; + } + +-void __init at91_set_serial_console(unsigned portnr) +-{ +- if (portnr < ATMEL_MAX_UART) { +- atmel_default_console_device = at91_uarts[portnr]; +- at91sam9g45_set_console_clock(at91_uarts[portnr]->id); +- } +-} +- + void __init at91_add_device_serial(void) + { + int i; +@@ -1757,13 +1749,9 @@ void __init at91_add_device_serial(void) + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +- +- if (!atmel_default_console_device) +- printk(KERN_INFO "AT91: No default serial console defined.\n"); + } + #else + void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} +-void __init at91_set_serial_console(unsigned portnr) {} + void __init at91_add_device_serial(void) {} + #endif + +diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c +index d9f2774..e420085 100644 +--- a/arch/arm/mach-at91/at91sam9rl.c ++++ b/arch/arm/mach-at91/at91sam9rl.c +@@ -232,18 +232,6 @@ static void __init at91sam9rl_register_clocks(void) + clk_register(&pck1); + } + +-static struct clk_lookup console_clock_lookup; +- +-void __init at91sam9rl_set_console_clock(int id) +-{ +- if (id >= ARRAY_SIZE(usart_clocks_lookups)) +- return; +- +- console_clock_lookup.con_id = "usart"; +- console_clock_lookup.clk = usart_clocks_lookups[id].clk; +- clkdev_add(&console_clock_lookup); +-} +- + /* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ +diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c +index fe4ae22..9c0b148 100644 +--- a/arch/arm/mach-at91/at91sam9rl_devices.c ++++ b/arch/arm/mach-at91/at91sam9rl_devices.c +@@ -1192,14 +1192,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) + at91_uarts[portnr] = pdev; + } + +-void __init at91_set_serial_console(unsigned portnr) +-{ +- if (portnr < ATMEL_MAX_UART) { +- atmel_default_console_device = at91_uarts[portnr]; +- at91sam9rl_set_console_clock(at91_uarts[portnr]->id); +- } +-} +- + void __init at91_add_device_serial(void) + { + int i; +@@ -1208,13 +1200,9 @@ void __init at91_add_device_serial(void) + if (at91_uarts[i]) + platform_device_register(at91_uarts[i]); + } +- +- if (!atmel_default_console_device) +- printk(KERN_INFO "AT91: No default serial console defined.\n"); + } + #else + void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} +-void __init at91_set_serial_console(unsigned portnr) {} + void __init at91_add_device_serial(void) {} + #endif + +diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c +index 2628384..f43ad91 100644 +--- a/arch/arm/mach-at91/board-1arm.c ++++ b/arch/arm/mach-at91/board-1arm.c +@@ -58,9 +58,6 @@ static void __init onearm_init_early(void) + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata onearm_eth_data = { +diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c +index 161efba..7c7c682 100644 +--- a/arch/arm/mach-at91/board-afeb-9260v1.c ++++ b/arch/arm/mach-at91/board-afeb-9260v1.c +@@ -65,9 +65,6 @@ static void __init afeb9260_init_early(void) + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c +index c6d44ee..871717d 100644 +--- a/arch/arm/mach-at91/board-cam60.c ++++ b/arch/arm/mach-at91/board-cam60.c +@@ -52,9 +52,6 @@ static void __init cam60_init_early(void) + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c +index 59d9cf9..168b3fa 100644 +--- a/arch/arm/mach-at91/board-carmeva.c ++++ b/arch/arm/mach-at91/board-carmeva.c +@@ -52,9 +52,6 @@ static void __init carmeva_init_early(void) + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata carmeva_eth_data = { +diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c +index 5f3680e..4073e30 100644 +--- a/arch/arm/mach-at91/board-cpu9krea.c ++++ b/arch/arm/mach-at91/board-cpu9krea.c +@@ -77,9 +77,6 @@ static void __init cpu9krea_init_early(void) + + /* USART5 on ttyS6. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c +index e094cc8..76c62ed 100644 +--- a/arch/arm/mach-at91/board-cpuat91.c ++++ b/arch/arm/mach-at91/board-cpuat91.c +@@ -78,9 +78,6 @@ static void __init cpuat91_init_early(void) + /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | + ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata cpuat91_eth_data = { +diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c +index 1a1547b..d984435 100644 +--- a/arch/arm/mach-at91/board-csb337.c ++++ b/arch/arm/mach-at91/board-csb337.c +@@ -53,9 +53,6 @@ static void __init csb337_init_early(void) + + /* DBGU on ttyS0 */ + at91_register_uart(0, 0, 0); +- +- /* make console=ttyS0 the default */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata csb337_eth_data = { +diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c +index f650bf3..0c9935d 100644 +--- a/arch/arm/mach-at91/board-csb637.c ++++ b/arch/arm/mach-at91/board-csb637.c +@@ -47,9 +47,6 @@ static void __init csb637_init_early(void) + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +- +- /* make console=ttyS0 (ie, DBGU) the default */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata csb637_eth_data = { +diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c +index d302ca3..a189b9f 100644 +--- a/arch/arm/mach-at91/board-eb9200.c ++++ b/arch/arm/mach-at91/board-eb9200.c +@@ -55,9 +55,6 @@ static void __init eb9200_init_early(void) + + /* USART2 on ttyS2. (Rx, Tx) - IRDA */ + at91_register_uart(AT91RM9200_ID_US2, 2, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata eb9200_eth_data = { +diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c +index 69966ce..307c530 100644 +--- a/arch/arm/mach-at91/board-ecbat91.c ++++ b/arch/arm/mach-at91/board-ecbat91.c +@@ -59,9 +59,6 @@ static void __init ecb_at91init_early(void) + + /* USART0 on ttyS1. (Rx & Tx only) */ + at91_register_uart(AT91RM9200_ID_US0, 1, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata ecb_at91eth_data = { +diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c +index f23aabe..7df6a9b 100644 +--- a/arch/arm/mach-at91/board-eco920.c ++++ b/arch/arm/mach-at91/board-eco920.c +@@ -43,9 +43,6 @@ static void __init eco920_init_early(void) + + /* DBGU on ttyS0. (Rx & Tx only */ + at91_register_uart(0, 0, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata eco920_eth_data = { +diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c +index 1815152..6dcc962 100644 +--- a/arch/arm/mach-at91/board-flexibity.c ++++ b/arch/arm/mach-at91/board-flexibity.c +@@ -44,9 +44,6 @@ static void __init flexibity_init_early(void) + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* USB Host port */ +diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c +index caf017f..bb07807 100644 +--- a/arch/arm/mach-at91/board-foxg20.c ++++ b/arch/arm/mach-at91/board-foxg20.c +@@ -93,9 +93,6 @@ static void __init foxg20_init_early(void) + /* USART5 on ttyS6. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); +- + /* Set the internal pull-up resistor on DRXD */ + at91_set_A_periph(AT91_PIN_PB14, 1); + +diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c +index efde1b2..3e858ed 100644 +--- a/arch/arm/mach-at91/board-kafa.c ++++ b/arch/arm/mach-at91/board-kafa.c +@@ -56,9 +56,6 @@ static void __init kafa_init_early(void) + + /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata kafa_eth_data = { +diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c +index 59b92aa..ccbc8be 100644 +--- a/arch/arm/mach-at91/board-kb9202.c ++++ b/arch/arm/mach-at91/board-kb9202.c +@@ -65,9 +65,6 @@ static void __init kb9202_init_early(void) + + /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata kb9202_eth_data = { +diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c +index 57d5f6a..c456fdc 100644 +--- a/arch/arm/mach-at91/board-neocore926.c ++++ b/arch/arm/mach-at91/board-neocore926.c +@@ -61,9 +61,6 @@ static void __init neocore926_init_early(void) + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c +index 59e35dd..4ca56cd 100644 +--- a/arch/arm/mach-at91/board-picotux200.c ++++ b/arch/arm/mach-at91/board-picotux200.c +@@ -56,9 +56,6 @@ static void __init picotux200_init_early(void) + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata picotux200_eth_data = { +diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c +index b6ed5ed..189d3fe 100644 +--- a/arch/arm/mach-at91/board-qil-a9260.c ++++ b/arch/arm/mach-at91/board-qil-a9260.c +@@ -66,10 +66,6 @@ static void __init ek_init_early(void) + + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS1 (ie, USART0) */ +- at91_set_serial_console(1); +- + } + + /* +diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c +index 01332aa..d5ce630 100644 +--- a/arch/arm/mach-at91/board-rm9200dk.c ++++ b/arch/arm/mach-at91/board-rm9200dk.c +@@ -61,9 +61,6 @@ static void __init dk_init_early(void) + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata dk_eth_data = { +diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c +index b2e4fe2..e96d5f5 100644 +--- a/arch/arm/mach-at91/board-rm9200ek.c ++++ b/arch/arm/mach-at91/board-rm9200ek.c +@@ -61,9 +61,6 @@ static void __init ek_init_early(void) + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static struct macb_platform_data __initdata ek_eth_data = { +diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c +index af0750f..2c84463 100644 +--- a/arch/arm/mach-at91/board-rsi-ews.c ++++ b/arch/arm/mach-at91/board-rsi-ews.c +@@ -52,9 +52,6 @@ static void __init rsi_ews_init_early(void) + /* USART3 on ttyS4. (Rx, Tx, RTS) */ + /* RS485 communication */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c +index e8b116b..dee44cb 100644 +--- a/arch/arm/mach-at91/board-sam9-l9260.c ++++ b/arch/arm/mach-at91/board-sam9-l9260.c +@@ -62,9 +62,6 @@ static void __init ek_init_early(void) + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c +index d5aec55..6da17b5 100644 +--- a/arch/arm/mach-at91/board-sam9260ek.c ++++ b/arch/arm/mach-at91/board-sam9260ek.c +@@ -65,9 +65,6 @@ static void __init ek_init_early(void) + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c +index 065fed3..950c20b 100644 +--- a/arch/arm/mach-at91/board-sam9261ek.c ++++ b/arch/arm/mach-at91/board-sam9261ek.c +@@ -64,9 +64,6 @@ static void __init ek_init_early(void) + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c +index 2ffe50f..4424873 100644 +--- a/arch/arm/mach-at91/board-sam9263ek.c ++++ b/arch/arm/mach-at91/board-sam9263ek.c +@@ -63,9 +63,6 @@ static void __init ek_init_early(void) + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c +index 8923ec9..05f8467 100644 +--- a/arch/arm/mach-at91/board-sam9g20ek.c ++++ b/arch/arm/mach-at91/board-sam9g20ek.c +@@ -76,9 +76,6 @@ static void __init ek_init_early(void) + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c +index c88e908..be2ca19 100644 +--- a/arch/arm/mach-at91/board-sam9m10g45ek.c ++++ b/arch/arm/mach-at91/board-sam9m10g45ek.c +@@ -60,9 +60,6 @@ static void __init ek_init_early(void) + /* USART0 not connected on the -EK board */ + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c +index b109ce2..23f383a 100644 +--- a/arch/arm/mach-at91/board-sam9rlek.c ++++ b/arch/arm/mach-at91/board-sam9rlek.c +@@ -48,9 +48,6 @@ static void __init ek_init_early(void) + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c +index ebc9d01..1a6774a 100644 +--- a/arch/arm/mach-at91/board-snapper9260.c ++++ b/arch/arm/mach-at91/board-snapper9260.c +@@ -46,7 +46,6 @@ static void __init snapper9260_init_early(void) + + /* Debug on ttyS0 */ + at91_register_uart(0, 0, 0); +- at91_set_serial_console(0); + + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS); +diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c +index 7640049..38a7ca5 100644 +--- a/arch/arm/mach-at91/board-stamp9g20.c ++++ b/arch/arm/mach-at91/board-stamp9g20.c +@@ -39,9 +39,6 @@ void __init stamp9g20_init_early(void) + + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + static void __init stamp9g20evb_init_early(void) +diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c +index b7483a3..ee482eb 100644 +--- a/arch/arm/mach-at91/board-usb-a926x.c ++++ b/arch/arm/mach-at91/board-usb-a926x.c +@@ -56,9 +56,6 @@ static void __init ek_init_early(void) + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c +index 38dd279..e94a04e 100644 +--- a/arch/arm/mach-at91/board-yl-9200.c ++++ b/arch/arm/mach-at91/board-yl-9200.c +@@ -75,9 +75,6 @@ static void __init yl9200_init_early(void) + + /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); +- +- /* set serial console to ttyS0 (ie, DBGU) */ +- at91_set_serial_console(0); + } + + /* +diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h +index dd9b346..0a60bf8 100644 +--- a/arch/arm/mach-at91/generic.h ++++ b/arch/arm/mach-at91/generic.h +@@ -40,17 +40,6 @@ extern struct sys_timer at91sam926x_timer; + extern struct sys_timer at91x40_timer; + + /* Clocks */ +-/* +- * function to specify the clock of the default console. As we do not +- * use the device/driver bus, the dev_name is not intialize. So we need +- * to link the clock to a specific con_id only "usart" +- */ +-extern void __init at91rm9200_set_console_clock(int id); +-extern void __init at91sam9260_set_console_clock(int id); +-extern void __init at91sam9261_set_console_clock(int id); +-extern void __init at91sam9263_set_console_clock(int id); +-extern void __init at91sam9rl_set_console_clock(int id); +-extern void __init at91sam9g45_set_console_clock(int id); + #ifdef CONFIG_AT91_PMC_UNIT + extern int __init at91_clock_init(unsigned long main_clock); + extern int __init at91_dt_clock_init(void); +diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h +index 49a8211..369afc2 100644 +--- a/arch/arm/mach-at91/include/mach/board.h ++++ b/arch/arm/mach-at91/include/mach/board.h +@@ -121,7 +121,6 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de + #define ATMEL_UART_RI 0x20 + + extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins); +-extern void __init at91_set_serial_console(unsigned portnr); + + extern struct platform_device *atmel_default_console_device; + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0018-ARM-at91-do-not-pin-mux-the-UARTs-in-init_early.patch b/patches.at91/0018-ARM-at91-do-not-pin-mux-the-UARTs-in-init_early.patch new file mode 100644 index 000000000000..7e4cfed4a699 --- /dev/null +++ b/patches.at91/0018-ARM-at91-do-not-pin-mux-the-UARTs-in-init_early.patch @@ -0,0 +1,1405 @@ +From 01175552b5bdf3438fa9bb6acbbfa5498414d2ab Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 5 Apr 2012 14:14:28 +0800 +Subject: ARM: at91: do not pin mux the UARTs in init_early + +There is no need to pinmux the UART so early in the kernel. +Move it to the board init. + +This will also allow to finally move the gpio driver to platform device/driver. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/board-1arm.c | 21 +++++----- + arch/arm/mach-at91/board-afeb-9260v1.c | 25 ++++++------ + arch/arm/mach-at91/board-cam60.c | 5 +-- + arch/arm/mach-at91/board-carmeva.c | 15 ++++---- + arch/arm/mach-at91/board-cpu9krea.c | 49 ++++++++++++------------ + arch/arm/mach-at91/board-cpuat91.c | 37 +++++++++--------- + arch/arm/mach-at91/board-csb337.c | 5 +-- + arch/arm/mach-at91/board-csb637.c | 5 +-- + arch/arm/mach-at91/board-eb9200.c | 21 +++++----- + arch/arm/mach-at91/board-ecbat91.c | 11 +++--- + arch/arm/mach-at91/board-eco920.c | 5 +-- + arch/arm/mach-at91/board-flexibity.c | 5 +-- + arch/arm/mach-at91/board-foxg20.c | 68 ++++++++++++++++----------------- + arch/arm/mach-at91/board-gsia18s.c | 63 +++++++++++++++--------------- + arch/arm/mach-at91/board-kafa.c | 11 +++--- + arch/arm/mach-at91/board-kb9202.c | 23 ++++++----- + arch/arm/mach-at91/board-neocore926.c | 11 +++--- + arch/arm/mach-at91/board-pcontrol-g20.c | 21 +++++----- + arch/arm/mach-at91/board-picotux200.c | 15 ++++---- + arch/arm/mach-at91/board-qil-a9260.c | 27 +++++++------ + arch/arm/mach-at91/board-rm9200dk.c | 15 ++++---- + arch/arm/mach-at91/board-rm9200ek.c | 15 ++++---- + arch/arm/mach-at91/board-rsi-ews.c | 27 +++++++------ + arch/arm/mach-at91/board-sam9-l9260.c | 21 +++++----- + arch/arm/mach-at91/board-sam9260ek.c | 21 +++++----- + arch/arm/mach-at91/board-sam9261ek.c | 5 +-- + arch/arm/mach-at91/board-sam9263ek.c | 11 +++--- + arch/arm/mach-at91/board-sam9g20ek.c | 21 +++++----- + arch/arm/mach-at91/board-sam9m10g45ek.c | 13 +++---- + arch/arm/mach-at91/board-sam9rlek.c | 11 +++--- + arch/arm/mach-at91/board-snapper9260.c | 17 ++++----- + arch/arm/mach-at91/board-stamp9g20.c | 61 ++++++++++++----------------- + arch/arm/mach-at91/board-usb-a926x.c | 5 +-- + arch/arm/mach-at91/board-yl-9200.c | 27 +++++++------ + 34 files changed, 333 insertions(+), 380 deletions(-) + +diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c +index f43ad91..271f994 100644 +--- a/arch/arm/mach-at91/board-1arm.c ++++ b/arch/arm/mach-at91/board-1arm.c +@@ -47,17 +47,6 @@ static void __init onearm_init_early(void) + + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); + } + + static struct macb_platform_data __initdata onearm_eth_data = { +@@ -79,6 +68,16 @@ static struct at91_udc_data __initdata onearm_udc_data = { + static void __init onearm_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); ++ ++ /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&onearm_eth_data); +diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c +index 7c7c682..b7d8aa7 100644 +--- a/arch/arm/mach-at91/board-afeb-9260v1.c ++++ b/arch/arm/mach-at91/board-afeb-9260v1.c +@@ -52,19 +52,6 @@ static void __init afeb9260_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, +- ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR +- | ATMEL_UART_DCD | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, +- ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -180,6 +167,18 @@ static struct at91_cf_data afeb9260_cf_data = { + static void __init afeb9260_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ++ ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR ++ | ATMEL_UART_DCD | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ++ ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&afeb9260_usbh_data); +diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c +index 871717d..29d3ef0 100644 +--- a/arch/arm/mach-at91/board-cam60.c ++++ b/arch/arm/mach-at91/board-cam60.c +@@ -49,9 +49,6 @@ static void __init cam60_init_early(void) + { + /* Initialize processor: 10 MHz crystal */ + at91_initialize(10000000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); + } + + /* +@@ -172,6 +169,8 @@ static void __init cam60_add_device_nand(void) + static void __init cam60_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* SPI */ + at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices)); +diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c +index 168b3fa..44328a6 100644 +--- a/arch/arm/mach-at91/board-carmeva.c ++++ b/arch/arm/mach-at91/board-carmeva.c +@@ -44,14 +44,6 @@ static void __init carmeva_init_early(void) + { + /* Initialize processor: 20.000 MHz crystal */ + at91_initialize(20000000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); + } + + static struct macb_platform_data __initdata carmeva_eth_data = { +@@ -136,6 +128,13 @@ static struct gpio_led carmeva_leds[] = { + static void __init carmeva_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&carmeva_eth_data); +diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c +index 4073e30..69951ec 100644 +--- a/arch/arm/mach-at91/board-cpu9krea.c ++++ b/arch/arm/mach-at91/board-cpu9krea.c +@@ -52,31 +52,6 @@ static void __init cpu9krea_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DGBU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | +- ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | +- ATMEL_UART_DCD | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | +- ATMEL_UART_RTS); +- +- /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | +- ATMEL_UART_RTS); +- +- /* USART3 on ttyS4. (Rx, Tx) */ +- at91_register_uart(AT91SAM9260_ID_US3, 4, 0); +- +- /* USART4 on ttyS5. (Rx, Tx) */ +- at91_register_uart(AT91SAM9260_ID_US4, 5, 0); +- +- /* USART5 on ttyS6. (Rx, Tx) */ +- at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + } + + /* +@@ -349,6 +324,30 @@ static void __init cpu9krea_board_init(void) + /* NOR */ + cpu9krea_add_device_nor(); + /* Serial */ ++ /* DGBU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ++ ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | ++ ATMEL_UART_DCD | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ++ ATMEL_UART_RTS); ++ ++ /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ++ ATMEL_UART_RTS); ++ ++ /* USART3 on ttyS4. (Rx, Tx) */ ++ at91_register_uart(AT91SAM9260_ID_US3, 4, 0); ++ ++ /* USART4 on ttyS5. (Rx, Tx) */ ++ at91_register_uart(AT91SAM9260_ID_US4, 5, 0); ++ ++ /* USART5 on ttyS6. (Rx, Tx) */ ++ at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&cpu9krea_usbh_data); +diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c +index 76c62ed..895cf2d 100644 +--- a/arch/arm/mach-at91/board-cpuat91.c ++++ b/arch/arm/mach-at91/board-cpuat91.c +@@ -59,25 +59,6 @@ static void __init cpuat91_init_early(void) + + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | +- ATMEL_UART_RTS); +- +- /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | +- ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | +- ATMEL_UART_DCD | ATMEL_UART_RI); +- +- /* USART2 on ttyS3 (Rx, Tx) */ +- at91_register_uart(AT91RM9200_ID_US2, 3, 0); +- +- /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | +- ATMEL_UART_RTS); + } + + static struct macb_platform_data __initdata cpuat91_eth_data = { +@@ -158,6 +139,24 @@ static struct platform_device *platform_devices[] __initdata = { + static void __init cpuat91_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ++ ATMEL_UART_RTS); ++ ++ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ++ ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | ++ ATMEL_UART_DCD | ATMEL_UART_RI); ++ ++ /* USART2 on ttyS3 (Rx, Tx) */ ++ at91_register_uart(AT91RM9200_ID_US2, 3, 0); ++ ++ /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | ++ ATMEL_UART_RTS); + at91_add_device_serial(); + /* LEDs. */ + at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds)); +diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c +index d984435..ad7f9f0 100644 +--- a/arch/arm/mach-at91/board-csb337.c ++++ b/arch/arm/mach-at91/board-csb337.c +@@ -50,9 +50,6 @@ static void __init csb337_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); +- +- /* DBGU on ttyS0 */ +- at91_register_uart(0, 0, 0); + } + + static struct macb_platform_data __initdata csb337_eth_data = { +@@ -226,6 +223,8 @@ static struct gpio_led csb_leds[] = { + static void __init csb337_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0 */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&csb337_eth_data); +diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c +index 0c9935d..7c8b05a 100644 +--- a/arch/arm/mach-at91/board-csb637.c ++++ b/arch/arm/mach-at91/board-csb637.c +@@ -44,9 +44,6 @@ static void __init csb637_init_early(void) + { + /* Initialize processor: 3.6864 MHz crystal */ + at91_initialize(3686400); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); + } + + static struct macb_platform_data __initdata csb637_eth_data = { +@@ -115,6 +112,8 @@ static void __init csb637_board_init(void) + /* LED(s) */ + at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds)); + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&csb637_eth_data); +diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c +index a189b9f..bd10172 100644 +--- a/arch/arm/mach-at91/board-eb9200.c ++++ b/arch/arm/mach-at91/board-eb9200.c +@@ -44,17 +44,6 @@ static void __init eb9200_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART2 on ttyS2. (Rx, Tx) - IRDA */ +- at91_register_uart(AT91RM9200_ID_US2, 2, 0); + } + + static struct macb_platform_data __initdata eb9200_eth_data = { +@@ -98,6 +87,16 @@ static struct i2c_board_info __initdata eb9200_i2c_devices[] = { + static void __init eb9200_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART2 on ttyS2. (Rx, Tx) - IRDA */ ++ at91_register_uart(AT91RM9200_ID_US2, 2, 0); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&eb9200_eth_data); +diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c +index 307c530..2510825 100644 +--- a/arch/arm/mach-at91/board-ecbat91.c ++++ b/arch/arm/mach-at91/board-ecbat91.c +@@ -53,12 +53,6 @@ static void __init ecb_at91init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx & Tx only) */ +- at91_register_uart(AT91RM9200_ID_US0, 1, 0); + } + + static struct macb_platform_data __initdata ecb_at91eth_data = { +@@ -149,6 +143,11 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = { + static void __init ecb_at91board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx & Tx only) */ ++ at91_register_uart(AT91RM9200_ID_US0, 1, 0); + at91_add_device_serial(); + + /* Ethernet */ +diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c +index 7df6a9b..bebeae8 100644 +--- a/arch/arm/mach-at91/board-eco920.c ++++ b/arch/arm/mach-at91/board-eco920.c +@@ -40,9 +40,6 @@ static void __init eco920_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); +- +- /* DBGU on ttyS0. (Rx & Tx only */ +- at91_register_uart(0, 0, 0); + } + + static struct macb_platform_data __initdata eco920_eth_data = { +@@ -100,6 +97,8 @@ static struct spi_board_info eco920_spi_devices[] = { + + static void __init eco920_board_init(void) + { ++ /* DBGU on ttyS0. (Rx & Tx only */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + at91_add_device_eth(&eco920_eth_data); + at91_add_device_usbh(&eco920_usbh_data); +diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c +index 6dcc962..47658f7 100644 +--- a/arch/arm/mach-at91/board-flexibity.c ++++ b/arch/arm/mach-at91/board-flexibity.c +@@ -41,9 +41,6 @@ static void __init flexibity_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); + } + + /* USB Host port */ +@@ -140,6 +137,8 @@ static struct gpio_led flexibity_leds[] = { + static void __init flexibity_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&flexibity_usbh_data); +diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c +index bb07807..33411e6 100644 +--- a/arch/arm/mach-at91/board-foxg20.c ++++ b/arch/arm/mach-at91/board-foxg20.c +@@ -61,41 +61,6 @@ static void __init foxg20_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, +- ATMEL_UART_CTS +- | ATMEL_UART_RTS +- | ATMEL_UART_DTR +- | ATMEL_UART_DSR +- | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, +- ATMEL_UART_CTS +- | ATMEL_UART_RTS); +- +- /* USART2 on ttyS3. (Rx & Tx only) */ +- at91_register_uart(AT91SAM9260_ID_US2, 3, 0); +- +- /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US3, 4, +- ATMEL_UART_CTS +- | ATMEL_UART_RTS); +- +- /* USART4 on ttyS5. (Rx & Tx only) */ +- at91_register_uart(AT91SAM9260_ID_US4, 5, 0); +- +- /* USART5 on ttyS6. (Rx & Tx only) */ +- at91_register_uart(AT91SAM9260_ID_US5, 6, 0); +- +- /* Set the internal pull-up resistor on DRXD */ +- at91_set_A_periph(AT91_PIN_PB14, 1); +- + } + + /* +@@ -238,6 +203,39 @@ static struct i2c_board_info __initdata foxg20_i2c_devices[] = { + static void __init foxg20_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ++ ATMEL_UART_CTS ++ | ATMEL_UART_RTS ++ | ATMEL_UART_DTR ++ | ATMEL_UART_DSR ++ | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ++ ATMEL_UART_CTS ++ | ATMEL_UART_RTS); ++ ++ /* USART2 on ttyS3. (Rx & Tx only) */ ++ at91_register_uart(AT91SAM9260_ID_US2, 3, 0); ++ ++ /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US3, 4, ++ ATMEL_UART_CTS ++ | ATMEL_UART_RTS); ++ ++ /* USART4 on ttyS5. (Rx & Tx only) */ ++ at91_register_uart(AT91SAM9260_ID_US4, 5, 0); ++ ++ /* USART5 on ttyS6. (Rx & Tx only) */ ++ at91_register_uart(AT91SAM9260_ID_US5, 6, 0); ++ ++ /* Set the internal pull-up resistor on DRXD */ ++ at91_set_A_periph(AT91_PIN_PB14, 1); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&foxg20_usbh_data); +diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c +index 230e719..3e0dfa6 100644 +--- a/arch/arm/mach-at91/board-gsia18s.c ++++ b/arch/arm/mach-at91/board-gsia18s.c +@@ -41,38 +41,6 @@ + static void __init gsia18s_init_early(void) + { + stamp9g20_init_early(); +- +- /* +- * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). +- * Used for Internal Analog Modem. +- */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, +- ATMEL_UART_CTS | ATMEL_UART_RTS | +- ATMEL_UART_DTR | ATMEL_UART_DSR | +- ATMEL_UART_DCD | ATMEL_UART_RI); +- /* +- * USART1 on ttyS2 (Rx, Tx, CTS, RTS). +- * Used for GPS or WiFi or Data stream. +- */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, +- ATMEL_UART_CTS | ATMEL_UART_RTS); +- /* +- * USART2 on ttyS3 (Rx, Tx, CTS, RTS). +- * Used for External Modem. +- */ +- at91_register_uart(AT91SAM9260_ID_US2, 3, +- ATMEL_UART_CTS | ATMEL_UART_RTS); +- /* +- * USART3 on ttyS4 (Rx, Tx, RTS). +- * Used for RS-485. +- */ +- at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); +- +- /* +- * USART4 on ttyS5 (Rx, Tx). +- * Used for TRX433 Radio Module. +- */ +- at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + } + + /* +@@ -558,6 +526,37 @@ static int __init gsia18s_power_off_init(void) + + static void __init gsia18s_board_init(void) + { ++ /* ++ * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). ++ * Used for Internal Analog Modem. ++ */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ++ ATMEL_UART_CTS | ATMEL_UART_RTS | ++ ATMEL_UART_DTR | ATMEL_UART_DSR | ++ ATMEL_UART_DCD | ATMEL_UART_RI); ++ /* ++ * USART1 on ttyS2 (Rx, Tx, CTS, RTS). ++ * Used for GPS or WiFi or Data stream. ++ */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ++ ATMEL_UART_CTS | ATMEL_UART_RTS); ++ /* ++ * USART2 on ttyS3 (Rx, Tx, CTS, RTS). ++ * Used for External Modem. ++ */ ++ at91_register_uart(AT91SAM9260_ID_US2, 3, ++ ATMEL_UART_CTS | ATMEL_UART_RTS); ++ /* ++ * USART3 on ttyS4 (Rx, Tx, RTS). ++ * Used for RS-485. ++ */ ++ at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); ++ ++ /* ++ * USART4 on ttyS5 (Rx, Tx). ++ * Used for TRX433 Radio Module. ++ */ ++ at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + stamp9g20_board_init(); + at91_add_device_usbh(&usbh_data); + at91_add_device_udc(&udc_data); +diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c +index 3e858ed..f46b3eb 100644 +--- a/arch/arm/mach-at91/board-kafa.c ++++ b/arch/arm/mach-at91/board-kafa.c +@@ -50,12 +50,6 @@ static void __init kafa_init_early(void) + + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + static struct macb_platform_data __initdata kafa_eth_data = { +@@ -77,6 +71,11 @@ static struct at91_udc_data __initdata kafa_udc_data = { + static void __init kafa_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&kafa_eth_data); +diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c +index ccbc8be..e71b9e1 100644 +--- a/arch/arm/mach-at91/board-kb9202.c ++++ b/arch/arm/mach-at91/board-kb9202.c +@@ -53,18 +53,6 @@ static void __init kb9202_init_early(void) + + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1 (Rx & Tx only) */ +- at91_register_uart(AT91RM9200_ID_US0, 1, 0); +- +- /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */ +- at91_register_uart(AT91RM9200_ID_US1, 2, 0); +- +- /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ +- at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + static struct macb_platform_data __initdata kb9202_eth_data = { +@@ -113,6 +101,17 @@ static struct atmel_nand_data __initdata kb9202_nand_data = { + static void __init kb9202_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1 (Rx & Tx only) */ ++ at91_register_uart(AT91RM9200_ID_US0, 1, 0); ++ ++ /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */ ++ at91_register_uart(AT91RM9200_ID_US1, 2, 0); ++ ++ /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ ++ at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&kb9202_eth_data); +diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c +index c456fdc..d2f4cc1 100644 +--- a/arch/arm/mach-at91/board-neocore926.c ++++ b/arch/arm/mach-at91/board-neocore926.c +@@ -55,12 +55,6 @@ static void __init neocore926_init_early(void) + { + /* Initialize processor: 20 MHz crystal */ + at91_initialize(20000000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -338,6 +332,11 @@ static struct ac97c_platform_data neocore926_ac97_data = { + static void __init neocore926_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + + /* USB Host */ +diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c +index b4a12fc..7fe6383 100644 +--- a/arch/arm/mach-at91/board-pcontrol-g20.c ++++ b/arch/arm/mach-at91/board-pcontrol-g20.c +@@ -40,17 +40,6 @@ + static void __init pcontrol_g20_init_early(void) + { + stamp9g20_init_early(); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS +- | ATMEL_UART_RTS); +- +- /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS +- | ATMEL_UART_RTS); +- +- /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ +- at91_register_uart(AT91SAM9260_ID_US4, 3, 0); + } + + static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { +@@ -199,6 +188,16 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = { + + static void __init pcontrol_g20_board_init(void) + { ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS ++ | ATMEL_UART_RTS); ++ ++ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS ++ | ATMEL_UART_RTS); ++ ++ /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ ++ at91_register_uart(AT91SAM9260_ID_US4, 3, 0); + stamp9g20_board_init(); + at91_add_device_usbh(&usbh_data); + at91_add_device_eth(&macb_data); +diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c +index 4ca56cd..b45c0a5 100644 +--- a/arch/arm/mach-at91/board-picotux200.c ++++ b/arch/arm/mach-at91/board-picotux200.c +@@ -48,14 +48,6 @@ static void __init picotux200_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); + } + + static struct macb_platform_data __initdata picotux200_eth_data = { +@@ -103,6 +95,13 @@ static struct platform_device picotux200_flash = { + static void __init picotux200_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&picotux200_eth_data); +diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c +index 189d3fe..0c61bf0 100644 +--- a/arch/arm/mach-at91/board-qil-a9260.c ++++ b/arch/arm/mach-at91/board-qil-a9260.c +@@ -52,20 +52,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 12.000 MHz crystal */ + at91_initialize(12000000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -231,6 +217,19 @@ static struct gpio_led ek_leds[] = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); ++ ++ /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c +index d5ce630..4a0b097 100644 +--- a/arch/arm/mach-at91/board-rm9200dk.c ++++ b/arch/arm/mach-at91/board-rm9200dk.c +@@ -53,14 +53,6 @@ static void __init dk_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); + } + + static struct macb_platform_data __initdata dk_eth_data = { +@@ -188,6 +180,13 @@ static struct gpio_led dk_leds[] = { + static void __init dk_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&dk_eth_data); +diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c +index e96d5f5..6fa54ac 100644 +--- a/arch/arm/mach-at91/board-rm9200ek.c ++++ b/arch/arm/mach-at91/board-rm9200ek.c +@@ -53,14 +53,6 @@ static void __init ek_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); + } + + static struct macb_platform_data __initdata ek_eth_data = { +@@ -159,6 +151,13 @@ static struct gpio_led ek_leds[] = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&ek_eth_data); +diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c +index 2c84463..10d8730 100644 +--- a/arch/arm/mach-at91/board-rsi-ews.c ++++ b/arch/arm/mach-at91/board-rsi-ews.c +@@ -38,20 +38,6 @@ static void __init rsi_ews_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- /* This one is for debugging */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- /* Dialin/-out modem interface */ +- at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART3 on ttyS4. (Rx, Tx, RTS) */ +- /* RS485 communication */ +- at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); + } + + /* +@@ -202,6 +188,19 @@ static struct platform_device rsiews_nor_flash = { + static void __init rsi_ews_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ /* This one is for debugging */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ /* Dialin/-out modem interface */ ++ at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART3 on ttyS4. (Rx, Tx, RTS) */ ++ /* RS485 communication */ ++ at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); + at91_add_device_serial(); + at91_set_gpio_output(AT91_PIN_PA21, 0); + /* Ethernet */ +diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c +index dee44cb..5343dab 100644 +--- a/arch/arm/mach-at91/board-sam9-l9260.c ++++ b/arch/arm/mach-at91/board-sam9-l9260.c +@@ -51,17 +51,6 @@ static void __init ek_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -182,6 +171,16 @@ static struct at91_mmc_data __initdata ek_mmc_data = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c +index 6da17b5..7b3c391 100644 +--- a/arch/arm/mach-at91/board-sam9260ek.c ++++ b/arch/arm/mach-at91/board-sam9260ek.c +@@ -54,17 +54,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -317,6 +306,16 @@ static void __init ek_add_device_buttons(void) {} + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c +index 950c20b..de1ed46 100644 +--- a/arch/arm/mach-at91/board-sam9261ek.c ++++ b/arch/arm/mach-at91/board-sam9261ek.c +@@ -61,9 +61,6 @@ static void __init ek_init_early(void) + + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); + } + + /* +@@ -575,6 +572,8 @@ static struct gpio_led ek_leds[] = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c +index 4424873..983cb98 100644 +--- a/arch/arm/mach-at91/board-sam9263ek.c ++++ b/arch/arm/mach-at91/board-sam9263ek.c +@@ -57,12 +57,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 16.367 MHz crystal */ + at91_initialize(16367660); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -409,6 +403,11 @@ static struct at91_can_data ek_can_data = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c +index 05f8467..3d61553 100644 +--- a/arch/arm/mach-at91/board-sam9g20ek.c ++++ b/arch/arm/mach-at91/board-sam9g20ek.c +@@ -65,17 +65,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -369,6 +358,16 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c +index be2ca19..9a87f0b 100644 +--- a/arch/arm/mach-at91/board-sam9m10g45ek.c ++++ b/arch/arm/mach-at91/board-sam9m10g45ek.c +@@ -53,13 +53,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 12.000 MHz crystal */ + at91_initialize(12000000); +- +- /* DGBU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 not connected on the -EK board */ +- /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ +- at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -454,6 +447,12 @@ static struct platform_device *devices[] __initdata = { + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DGBU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 not connected on the -EK board */ ++ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ ++ at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB HS Host */ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); +diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c +index 23f383a..be3239f 100644 +--- a/arch/arm/mach-at91/board-sam9rlek.c ++++ b/arch/arm/mach-at91/board-sam9rlek.c +@@ -42,12 +42,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 12.000 MHz crystal */ + at91_initialize(12000000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + } + + /* +@@ -293,6 +287,11 @@ static void __init ek_add_device_buttons(void) {} + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_add_device_serial(); + /* USB HS */ + at91_add_device_usba(&ek_usba_udc_data); +diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c +index 1a6774a..9d446f1 100644 +--- a/arch/arm/mach-at91/board-snapper9260.c ++++ b/arch/arm/mach-at91/board-snapper9260.c +@@ -43,15 +43,6 @@ + static void __init snapper9260_init_early(void) + { + at91_initialize(18432000); +- +- /* Debug on ttyS0 */ +- at91_register_uart(0, 0, 0); +- +- at91_register_uart(AT91SAM9260_ID_US0, 1, +- ATMEL_UART_CTS | ATMEL_UART_RTS); +- at91_register_uart(AT91SAM9260_ID_US1, 2, +- ATMEL_UART_CTS | ATMEL_UART_RTS); +- at91_register_uart(AT91SAM9260_ID_US2, 3, 0); + } + + static struct at91_usbh_data __initdata snapper9260_usbh_data = { +@@ -167,6 +158,14 @@ static void __init snapper9260_board_init(void) + snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31); + i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1); + ++ /* Debug on ttyS0 */ ++ at91_register_uart(0, 0, 0); ++ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ++ ATMEL_UART_CTS | ATMEL_UART_RTS); ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ++ ATMEL_UART_CTS | ATMEL_UART_RTS); ++ at91_register_uart(AT91SAM9260_ID_US2, 3, 0); + at91_add_device_serial(); + at91_add_device_usbh(&snapper9260_usbh_data); + at91_add_device_udc(&snapper9260_udc_data); +diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c +index 38a7ca5..ee86f9d 100644 +--- a/arch/arm/mach-at91/board-stamp9g20.c ++++ b/arch/arm/mach-at91/board-stamp9g20.c +@@ -36,41 +36,6 @@ void __init stamp9g20_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* DGBU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +-} +- +-static void __init stamp9g20evb_init_early(void) +-{ +- stamp9g20_init_early(); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR +- | ATMEL_UART_DCD | ATMEL_UART_RI); +-} +- +-static void __init portuxg20_init_early(void) +-{ +- stamp9g20_init_early(); +- +- /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR +- | ATMEL_UART_DCD | ATMEL_UART_RI); +- +- /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ +- at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); +- +- /* USART4 on ttyS5. (Rx, Tx only) */ +- at91_register_uart(AT91SAM9260_ID_US4, 5, 0); +- +- /* USART5 on ttyS6. (Rx, Tx only) */ +- at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + } + + /* +@@ -251,6 +216,8 @@ void add_w1(void) + void __init stamp9g20_board_init(void) + { + /* Serial */ ++ /* DGBU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* NAND */ + add_device_nand(); +@@ -266,6 +233,22 @@ void __init stamp9g20_board_init(void) + + static void __init portuxg20_board_init(void) + { ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR ++ | ATMEL_UART_DCD | ATMEL_UART_RI); ++ ++ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); ++ ++ /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ ++ at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); ++ ++ /* USART4 on ttyS5. (Rx, Tx only) */ ++ at91_register_uart(AT91SAM9260_ID_US4, 5, 0); ++ ++ /* USART5 on ttyS6. (Rx, Tx only) */ ++ at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + stamp9g20_board_init(); + /* USB Host */ + at91_add_device_usbh(&usbh_data); +@@ -283,6 +266,10 @@ static void __init portuxg20_board_init(void) + + static void __init stamp9g20evb_board_init(void) + { ++ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR ++ | ATMEL_UART_DCD | ATMEL_UART_RI); + stamp9g20_board_init(); + /* USB Host */ + at91_add_device_usbh(&usbh_data); +@@ -300,7 +287,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20") + /* Maintainer: taskit GmbH */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, +- .init_early = portuxg20_init_early, ++ .init_early = stamp9g20_init_early, + .init_irq = at91_init_irq_default, + .init_machine = portuxg20_board_init, + MACHINE_END +@@ -309,7 +296,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20") + /* Maintainer: taskit GmbH */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, +- .init_early = stamp9g20evb_init_early, ++ .init_early = stamp9g20_init_early, + .init_irq = at91_init_irq_default, + .init_machine = stamp9g20evb_board_init, + MACHINE_END +diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c +index ee482eb..332ecd4 100644 +--- a/arch/arm/mach-at91/board-usb-a926x.c ++++ b/arch/arm/mach-at91/board-usb-a926x.c +@@ -53,9 +53,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 12.00 MHz crystal */ + at91_initialize(12000000); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); + } + + /* +@@ -322,6 +319,8 @@ static void __init ek_add_device_leds(void) + static void __init ek_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); +diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c +index e94a04e..db8d25c 100644 +--- a/arch/arm/mach-at91/board-yl-9200.c ++++ b/arch/arm/mach-at91/board-yl-9200.c +@@ -61,20 +61,6 @@ static void __init yl9200_init_early(void) + + /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ + at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); +- +- /* DBGU on ttyS0. (Rx & Tx only) */ +- at91_register_uart(0, 0, 0); +- +- /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ +- at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS +- | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD +- | ATMEL_UART_RI); +- +- /* USART0 on ttyS2. (Rx & Tx only to JP3) */ +- at91_register_uart(AT91RM9200_ID_US0, 2, 0); +- +- /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ +- at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); + } + + /* +@@ -558,6 +544,19 @@ void __init yl9200_add_device_video(void) {} + static void __init yl9200_board_init(void) + { + /* Serial */ ++ /* DBGU on ttyS0. (Rx & Tx only) */ ++ at91_register_uart(0, 0, 0); ++ ++ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ ++ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS ++ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD ++ | ATMEL_UART_RI); ++ ++ /* USART0 on ttyS2. (Rx & Tx only to JP3) */ ++ at91_register_uart(AT91RM9200_ID_US0, 2, 0); ++ ++ /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ ++ at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); + at91_add_device_serial(); + /* Ethernet */ + at91_add_device_eth(&yl9200_eth_data); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0019-ARM-at91-move-at91_init_leds-to-board-init.patch b/patches.at91/0019-ARM-at91-move-at91_init_leds-to-board-init.patch new file mode 100644 index 000000000000..4e75d7d4ff61 --- /dev/null +++ b/patches.at91/0019-ARM-at91-move-at91_init_leds-to-board-init.patch @@ -0,0 +1,288 @@ +From 0543012c6006a0638654943130daae637f764d5a Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 5 Apr 2012 14:27:57 +0800 +Subject: ARM: at91: move at91_init_leds to board init + +This will also allow to finally move the gpio driver to platform device/driver. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/board-csb337.c | 5 ++--- + arch/arm/mach-at91/board-ecbat91.c | 6 +++--- + arch/arm/mach-at91/board-eco920.c | 5 ++--- + arch/arm/mach-at91/board-kafa.c | 6 +++--- + arch/arm/mach-at91/board-kb9202.c | 6 +++--- + arch/arm/mach-at91/board-rm9200dk.c | 6 +++--- + arch/arm/mach-at91/board-rm9200ek.c | 6 +++--- + arch/arm/mach-at91/board-rsi-ews.c | 6 +++--- + arch/arm/mach-at91/board-sam9-l9260.c | 6 +++--- + arch/arm/mach-at91/board-sam9261ek.c | 6 +++--- + arch/arm/mach-at91/board-yl-9200.c | 6 +++--- + 11 files changed, 31 insertions(+), 33 deletions(-) + +diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c +index ad7f9f0..cd81336 100644 +--- a/arch/arm/mach-at91/board-csb337.c ++++ b/arch/arm/mach-at91/board-csb337.c +@@ -47,9 +47,6 @@ static void __init csb337_init_early(void) + { + /* Initialize processor: 3.6864 MHz crystal */ + at91_initialize(3686400); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + } + + static struct macb_platform_data __initdata csb337_eth_data = { +@@ -222,6 +219,8 @@ static struct gpio_led csb_leds[] = { + + static void __init csb337_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + /* Serial */ + /* DBGU on ttyS0 */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c +index 2510825..89cc372 100644 +--- a/arch/arm/mach-at91/board-ecbat91.c ++++ b/arch/arm/mach-at91/board-ecbat91.c +@@ -50,9 +50,6 @@ static void __init ecb_at91init_early(void) + + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); + } + + static struct macb_platform_data __initdata ecb_at91eth_data = { +@@ -142,6 +139,9 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = { + + static void __init ecb_at91board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c +index bebeae8..558546c 100644 +--- a/arch/arm/mach-at91/board-eco920.c ++++ b/arch/arm/mach-at91/board-eco920.c +@@ -37,9 +37,6 @@ static void __init eco920_init_early(void) + at91rm9200_set_type(ARCH_REVISON_9200_PQFP); + + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + } + + static struct macb_platform_data __initdata eco920_eth_data = { +@@ -97,6 +94,8 @@ static struct spi_board_info eco920_spi_devices[] = { + + static void __init eco920_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + /* DBGU on ttyS0. (Rx & Tx only */ + at91_register_uart(0, 0, 0); + at91_add_device_serial(); +diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c +index f46b3eb..f260657 100644 +--- a/arch/arm/mach-at91/board-kafa.c ++++ b/arch/arm/mach-at91/board-kafa.c +@@ -47,9 +47,6 @@ static void __init kafa_init_early(void) + + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Set up the LEDs */ +- at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); + } + + static struct macb_platform_data __initdata kafa_eth_data = { +@@ -70,6 +67,9 @@ static struct at91_udc_data __initdata kafa_udc_data = { + + static void __init kafa_board_init(void) + { ++ /* Set up the LEDs */ ++ at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c +index e71b9e1..ba39db5 100644 +--- a/arch/arm/mach-at91/board-kb9202.c ++++ b/arch/arm/mach-at91/board-kb9202.c +@@ -50,9 +50,6 @@ static void __init kb9202_init_early(void) + + /* Initialize processor: 10 MHz crystal */ + at91_initialize(10000000); +- +- /* Set up the LEDs */ +- at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); + } + + static struct macb_platform_data __initdata kb9202_eth_data = { +@@ -100,6 +97,9 @@ static struct atmel_nand_data __initdata kb9202_nand_data = { + + static void __init kb9202_board_init(void) + { ++ /* Set up the LEDs */ ++ at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c +index 4a0b097..afd7a47 100644 +--- a/arch/arm/mach-at91/board-rm9200dk.c ++++ b/arch/arm/mach-at91/board-rm9200dk.c +@@ -50,9 +50,6 @@ static void __init dk_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); + } + + static struct macb_platform_data __initdata dk_eth_data = { +@@ -179,6 +176,9 @@ static struct gpio_led dk_leds[] = { + + static void __init dk_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c +index 6fa54ac..2b15b8a 100644 +--- a/arch/arm/mach-at91/board-rm9200ek.c ++++ b/arch/arm/mach-at91/board-rm9200ek.c +@@ -50,9 +50,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); + } + + static struct macb_platform_data __initdata ek_eth_data = { +@@ -150,6 +147,9 @@ static struct gpio_led ek_leds[] = { + + static void __init ek_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c +index 10d8730..24ab9be 100644 +--- a/arch/arm/mach-at91/board-rsi-ews.c ++++ b/arch/arm/mach-at91/board-rsi-ews.c +@@ -35,9 +35,6 @@ static void __init rsi_ews_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); + } + + /* +@@ -187,6 +184,9 @@ static struct platform_device rsiews_nor_flash = { + */ + static void __init rsi_ews_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + /* This one is for debugging */ +diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c +index 5343dab..cdd21f2 100644 +--- a/arch/arm/mach-at91/board-sam9-l9260.c ++++ b/arch/arm/mach-at91/board-sam9-l9260.c +@@ -48,9 +48,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); + } + + /* +@@ -170,6 +167,9 @@ static struct at91_mmc_data __initdata ek_mmc_data = { + + static void __init ek_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c +index de1ed46..2736453 100644 +--- a/arch/arm/mach-at91/board-sam9261ek.c ++++ b/arch/arm/mach-at91/board-sam9261ek.c +@@ -58,9 +58,6 @@ static void __init ek_init_early(void) + { + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs */ +- at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); + } + + /* +@@ -571,6 +568,9 @@ static struct gpio_led ek_leds[] = { + + static void __init ek_board_init(void) + { ++ /* Setup the LEDs */ ++ at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c +index db8d25c..d56665e 100644 +--- a/arch/arm/mach-at91/board-yl-9200.c ++++ b/arch/arm/mach-at91/board-yl-9200.c +@@ -58,9 +58,6 @@ static void __init yl9200_init_early(void) + + /* Initialize processor: 18.432 MHz crystal */ + at91_initialize(18432000); +- +- /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ +- at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); + } + + /* +@@ -543,6 +540,9 @@ void __init yl9200_add_device_video(void) {} + + static void __init yl9200_board_init(void) + { ++ /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ ++ at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); ++ + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0020-ARM-at91-pm-select-memory-controler-at-runtime.patch b/patches.at91/0020-ARM-at91-pm-select-memory-controler-at-runtime.patch new file mode 100644 index 000000000000..23c7bb326439 --- /dev/null +++ b/patches.at91/0020-ARM-at91-pm-select-memory-controler-at-runtime.patch @@ -0,0 +1,117 @@ +From e7d4df4ef74b1ed11a0e2037bc5cbe8123cf258d Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon, 13 Feb 2012 14:58:30 +0800 +Subject: ARM: at91: pm select memory controler at runtime + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +[nicolas.ferre@atmel.com: add cpuidle modification] +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/cpuidle.c | 8 +++++++- + arch/arm/mach-at91/pm.c | 12 ++++++++---- + arch/arm/mach-at91/pm.h | 13 ------------- + 3 files changed, 15 insertions(+), 18 deletions(-) + +diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c +index ece1f9a..0c63815 100644 +--- a/arch/arm/mach-at91/cpuidle.c ++++ b/arch/arm/mach-at91/cpuidle.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + #include "pm.h" + +@@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) + { +- at91_standby(); ++ if (cpu_is_at91rm9200()) ++ at91rm9200_standby(); ++ else if (cpu_is_at91sam9g45()) ++ at91sam9g45_standby(); ++ else ++ at91sam9_standby(); + + return index; + } +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index f630250..1bfaad6 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state) + * For ARM 926 based chips, this requirement is weaker + * as at91sam9 can access a RAM in self-refresh mode. + */ +- at91_standby(); ++ if (cpu_is_at91rm9200()) ++ at91rm9200_standby(); ++ else if (cpu_is_at91sam9g45()) ++ at91sam9g45_standby(); ++ else ++ at91sam9_standby(); + break; + + case PM_SUSPEND_ON: +@@ -307,10 +312,9 @@ static int __init at91_pm_init(void) + + pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); + +-#ifdef CONFIG_ARCH_AT91RM9200 + /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ +- at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); +-#endif ++ if (cpu_is_at91rm9200()) ++ at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); + + suspend_set_ops(&at91_pm_ops); + +diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h +index 89f56f3..1b4865e 100644 +--- a/arch/arm/mach-at91/pm.h ++++ b/arch/arm/mach-at91/pm.h +@@ -12,7 +12,6 @@ + #define __ARCH_ARM_MACH_AT91_PM + + #include +-#ifdef CONFIG_ARCH_AT91RM9200 + #include + + /* +@@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void) + "r" (lpr)); + } + +-#define at91_standby at91rm9200_standby +- +-#elif defined(CONFIG_ARCH_AT91SAM9G45) +- + /* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +@@ -75,10 +70,6 @@ static inline void at91sam9g45_standby(void) + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); + } + +-#define at91_standby at91sam9g45_standby +- +-#else +- + #ifdef CONFIG_ARCH_AT91SAM9263 + /* + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; +@@ -102,8 +93,4 @@ static inline void at91sam9_standby(void) + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); + } + +-#define at91_standby at91sam9_standby +- +-#endif +- + #endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0021-ARM-at91-add-SOC_AT91SAM9-kconfig-option-to-factoris.patch b/patches.at91/0021-ARM-at91-add-SOC_AT91SAM9-kconfig-option-to-factoris.patch new file mode 100644 index 000000000000..3d2ea6f94e1a --- /dev/null +++ b/patches.at91/0021-ARM-at91-add-SOC_AT91SAM9-kconfig-option-to-factoris.patch @@ -0,0 +1,133 @@ +From 54af5dc6fcc90243d7d161c83f2c94cb1ef67697 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri, 6 Apr 2012 13:04:04 +0800 +Subject: ARM: at91: add SOC_AT91SAM9 kconfig option to factorise select + +This will allow to simplify the switch to multi soc in the same kernel. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 29 +++++++++++++---------------- + arch/arm/mach-at91/Makefile | 17 +++++++++-------- + 2 files changed, 22 insertions(+), 24 deletions(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 885fdb9..40e31c7 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -17,6 +17,11 @@ config AT91_SAM9G45_RESET + bool + default !ARCH_AT91X40 + ++config SOC_AT91SAM9 ++ bool ++ select GENERIC_CLOCKEVENTS ++ select CPU_ARM926T ++ + menu "Atmel AT91 System-on-Chip" + + choice +@@ -30,51 +35,44 @@ config ARCH_AT91RM9200 + + config ARCH_AT91SAM9260 + bool "AT91SAM9260 or AT91SAM9XE" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAVE_NET_MACB + + config ARCH_AT91SAM9261 + bool "AT91SAM9261" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 + + config ARCH_AT91SAM9G10 + bool "AT91SAM9G10" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAVE_FB_ATMEL + + config ARCH_AT91SAM9263 + bool "AT91SAM9263" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + select HAVE_AT91_DBGU1 + + config ARCH_AT91SAM9RL + bool "AT91SAM9RL" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 + + config ARCH_AT91SAM9G20 + bool "AT91SAM9G20" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAVE_NET_MACB + + config ARCH_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10 families" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + select HAVE_AT91_DBGU1 +@@ -84,8 +82,7 @@ config ARCH_AT91SAM9G45 + + config ARCH_AT91SAM9X5 + bool "AT91SAM9x5 family" +- select CPU_ARM926T +- select GENERIC_CLOCKEVENTS ++ select SOC_AT91SAM9 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + select HAVE_AT91_DBGU0 +diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile +index 8512e53..d97d0f4 100644 +--- a/arch/arm/mach-at91/Makefile ++++ b/arch/arm/mach-at91/Makefile +@@ -10,17 +10,18 @@ obj- := + obj-$(CONFIG_AT91_PMC_UNIT) += clock.o + obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o + obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o ++obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o + + # CPU-specific support + obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o +-obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o ++obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam9rl_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o + obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o + + # AT91RM9200 board-specific support +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0022-ARN-at91-introduce-SOC_AT91xxx-define-to-allow-to-co.patch b/patches.at91/0022-ARN-at91-introduce-SOC_AT91xxx-define-to-allow-to-co.patch new file mode 100644 index 000000000000..13ba82bd9366 --- /dev/null +++ b/patches.at91/0022-ARN-at91-introduce-SOC_AT91xxx-define-to-allow-to-co.patch @@ -0,0 +1,378 @@ +From 420a99e1110afb0a9a2fd8ac6e1c18ba2136002e Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri, 6 Apr 2012 11:51:50 +0800 +Subject: ARN: at91: introduce SOC_AT91xxx define to allow to compile SoC core + support + +We can now compile all SoC core support together and DT boards. +We still can not compile together the non DT board. +So We keep the ARCH_AT91xxx for the non DT board and for backward defconfig +compatibility. This will enable the plaform_device ressources. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/configs/at91rm9200_defconfig | 1 + + arch/arm/mach-at91/Kconfig | 91 ++++++++++++++++++++++++----------- + arch/arm/mach-at91/Makefile | 25 ++++++---- + arch/arm/mach-at91/include/mach/cpu.h | 28 +++++------ + arch/arm/mach-at91/pm.h | 2 +- + arch/arm/mach-at91/pm_slowclock.S | 2 +- + arch/arm/mach-at91/soc.h | 14 +++--- + 7 files changed, 101 insertions(+), 62 deletions(-) + +diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig +index bbe4e1a..d54e2ac 100644 +--- a/arch/arm/configs/at91rm9200_defconfig ++++ b/arch/arm/configs/at91rm9200_defconfig +@@ -14,6 +14,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_IOSCHED_CFQ is not set + CONFIG_ARCH_AT91=y ++CONFIG_ARCH_AT91RM9200=y + CONFIG_MACH_ONEARM=y + CONFIG_ARCH_AT91RM9200DK=y + CONFIG_MACH_AT91RM9200EK=y +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 40e31c7..98a42f3 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -24,68 +24,66 @@ config SOC_AT91SAM9 + + menu "Atmel AT91 System-on-Chip" + +-choice +- prompt "Atmel AT91 Processor" ++comment "Atmel AT91 Processor" + +-config ARCH_AT91RM9200 ++config SOC_AT91SAM9 ++ bool ++ select CPU_ARM926T ++ select AT91_SAM9_TIME ++ select AT91_SAM9_SMC ++ ++config SOC_AT91RM9200 + bool "AT91RM9200" + select CPU_ARM920T + select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 + +-config ARCH_AT91SAM9260 +- bool "AT91SAM9260 or AT91SAM9XE" ++config SOC_AT91SAM9260 ++ bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAVE_NET_MACB ++ help ++ Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE ++ or AT91SAM9G20 SoC. + +-config ARCH_AT91SAM9261 +- bool "AT91SAM9261" +- select SOC_AT91SAM9 +- select HAVE_FB_ATMEL +- select HAVE_AT91_DBGU0 +- +-config ARCH_AT91SAM9G10 +- bool "AT91SAM9G10" ++config SOC_AT91SAM9261 ++ bool "AT91SAM9261 or AT91SAM9G10" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAVE_FB_ATMEL ++ help ++ Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. + +-config ARCH_AT91SAM9263 ++config SOC_AT91SAM9263 + bool "AT91SAM9263" + select SOC_AT91SAM9 ++ select HAVE_AT91_DBGU1 + select HAVE_FB_ATMEL + select HAVE_NET_MACB +- select HAVE_AT91_DBGU1 + +-config ARCH_AT91SAM9RL ++config SOC_AT91SAM9RL + bool "AT91SAM9RL" + select SOC_AT91SAM9 +- select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 ++ select HAVE_FB_ATMEL + +-config ARCH_AT91SAM9G20 +- bool "AT91SAM9G20" +- select SOC_AT91SAM9 +- select HAVE_AT91_DBGU0 +- select HAVE_NET_MACB +- +-config ARCH_AT91SAM9G45 ++config SOC_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10 families" + select SOC_AT91SAM9 ++ select HAVE_AT91_DBGU1 + select HAVE_FB_ATMEL + select HAVE_NET_MACB +- select HAVE_AT91_DBGU1 + help + Select this if you are using one of Atmel's AT91SAM9G45 family SoC. + This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + +-config ARCH_AT91SAM9X5 ++config SOC_AT91SAM9X5 + bool "AT91SAM9x5 family" + select SOC_AT91SAM9 ++ select HAVE_AT91_DBGU0 + select HAVE_FB_ATMEL + select HAVE_NET_MACB +- select HAVE_AT91_DBGU0 + help + Select this if you are using one of Atmel's AT91SAM9x5 family SoC. + This means that your SAM9 name finishes with a '5' (except if it is +@@ -93,8 +91,47 @@ config ARCH_AT91SAM9X5 + This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 + and AT91SAM9X35. + ++choice ++ prompt "Atmel AT91 Processor Devices for non DT boards" ++ ++config ARCH_AT91_NONE ++ bool "None" ++ ++config ARCH_AT91RM9200 ++ bool "AT91RM9200" ++ select SOC_AT91RM9200 ++ ++config ARCH_AT91SAM9260 ++ bool "AT91SAM9260 or AT91SAM9XE" ++ select SOC_AT91SAM9260 ++ ++config ARCH_AT91SAM9261 ++ bool "AT91SAM9261" ++ select SOC_AT91SAM9261 ++ ++config ARCH_AT91SAM9G10 ++ bool "AT91SAM9G10" ++ select SOC_AT91SAM9261 ++ ++config ARCH_AT91SAM9263 ++ bool "AT91SAM9263" ++ select SOC_AT91SAM9263 ++ ++config ARCH_AT91SAM9RL ++ bool "AT91SAM9RL" ++ select SOC_AT91SAM9RL ++ ++config ARCH_AT91SAM9G20 ++ bool "AT91SAM9G20" ++ select SOC_AT91SAM9260 ++ ++config ARCH_AT91SAM9G45 ++ bool "AT91SAM9G45" ++ select SOC_AT91SAM9G45 ++ + config ARCH_AT91X40 + bool "AT91x40" ++ depends on !MMU + select ARCH_USES_GETTIMEOFFSET + + endchoice +diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile +index d97d0f4..79d0f60 100644 +--- a/arch/arm/mach-at91/Makefile ++++ b/arch/arm/mach-at91/Makefile +@@ -13,15 +13,22 @@ obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o + obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o + + # CPU-specific support +-obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam9rl_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o +-obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o ++obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o ++obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o ++obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o ++obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o ++obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o ++obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o ++obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o ++ ++obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o ++obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o + obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o + + # AT91RM9200 board-specific support +diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h +index 0118c33..73d2fd2 100644 +--- a/arch/arm/mach-at91/include/mach/cpu.h ++++ b/arch/arm/mach-at91/include/mach/cpu.h +@@ -54,6 +54,7 @@ + #define ARCH_REVISON_9200_BGA (0 << 0) + #define ARCH_REVISON_9200_PQFP (1 << 0) + ++#ifndef __ASSEMBLY__ + enum at91_soc_type { + /* 920T */ + AT91_SOC_RM9200, +@@ -106,7 +107,7 @@ static inline int at91_soc_is_detected(void) + return at91_soc_initdata.type != AT91_SOC_NONE; + } + +-#ifdef CONFIG_ARCH_AT91RM9200 ++#ifdef CONFIG_SOC_AT91RM9200 + #define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) + #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) + #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) +@@ -116,45 +117,37 @@ static inline int at91_soc_is_detected(void) + #define cpu_is_at91rm9200_pqfp() (0) + #endif + +-#ifdef CONFIG_ARCH_AT91SAM9260 ++#ifdef CONFIG_SOC_AT91SAM9260 + #define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) + #define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) ++#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) + #else + #define cpu_is_at91sam9xe() (0) + #define cpu_is_at91sam9260() (0) +-#endif +- +-#ifdef CONFIG_ARCH_AT91SAM9G20 +-#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) +-#else + #define cpu_is_at91sam9g20() (0) + #endif + +-#ifdef CONFIG_ARCH_AT91SAM9261 ++#ifdef CONFIG_SOC_AT91SAM9261 + #define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) +-#else +-#define cpu_is_at91sam9261() (0) +-#endif +- +-#ifdef CONFIG_ARCH_AT91SAM9G10 + #define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) + #else ++#define cpu_is_at91sam9261() (0) + #define cpu_is_at91sam9g10() (0) + #endif + +-#ifdef CONFIG_ARCH_AT91SAM9263 ++#ifdef CONFIG_SOC_AT91SAM9263 + #define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) + #else + #define cpu_is_at91sam9263() (0) + #endif + +-#ifdef CONFIG_ARCH_AT91SAM9RL ++#ifdef CONFIG_SOC_AT91SAM9RL + #define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) + #else + #define cpu_is_at91sam9rl() (0) + #endif + +-#ifdef CONFIG_ARCH_AT91SAM9G45 ++#ifdef CONFIG_SOC_AT91SAM9G45 + #define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) + #define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) + #define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) +@@ -168,7 +161,7 @@ static inline int at91_soc_is_detected(void) + #define cpu_is_at91sam9m11() (0) + #endif + +-#ifdef CONFIG_ARCH_AT91SAM9X5 ++#ifdef CONFIG_SOC_AT91SAM9X5 + #define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) + #define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) + #define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) +@@ -189,5 +182,6 @@ static inline int at91_soc_is_detected(void) + * definitions may reduce clutter in common drivers. + */ + #define cpu_is_at32ap7000() (0) ++#endif /* __ASSEMBLY__ */ + + #endif /* __MACH_CPU_H__ */ +diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h +index 1b4865e..38f467c 100644 +--- a/arch/arm/mach-at91/pm.h ++++ b/arch/arm/mach-at91/pm.h +@@ -70,7 +70,7 @@ static inline void at91sam9g45_standby(void) + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); + } + +-#ifdef CONFIG_ARCH_AT91SAM9263 ++#ifdef CONFIG_SOC_AT91SAM9263 + /* + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; + * handle those cases both here and in the Suspend-To-RAM support. +diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S +index db54521..098c28d 100644 +--- a/arch/arm/mach-at91/pm_slowclock.S ++++ b/arch/arm/mach-at91/pm_slowclock.S +@@ -18,7 +18,7 @@ + #include + + +-#ifdef CONFIG_ARCH_AT91SAM9263 ++#ifdef CONFIG_SOC_AT91SAM9263 + /* + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; + * handle those cases both here and in the Suspend-To-RAM support. +diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h +index 5db4aa4..683dddf 100644 +--- a/arch/arm/mach-at91/soc.h ++++ b/arch/arm/mach-at91/soc.h +@@ -26,30 +26,30 @@ static inline int at91_soc_is_enabled(void) + return at91_boot_soc.init != NULL; + } + +-#if !defined(CONFIG_ARCH_AT91RM9200) ++#if !defined(CONFIG_SOC_AT91RM9200) + #define at91rm9200_soc at91_boot_soc + #endif + +-#if !(defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)) ++#if !defined(CONFIG_SOC_AT91SAM9260) + #define at91sam9260_soc at91_boot_soc + #endif + +-#if !(defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)) ++#if !defined(CONFIG_SOC_AT91SAM9261) + #define at91sam9261_soc at91_boot_soc + #endif + +-#if !defined(CONFIG_ARCH_AT91SAM9263) ++#if !defined(CONFIG_SOC_AT91SAM9263) + #define at91sam9263_soc at91_boot_soc + #endif + +-#if !defined(CONFIG_ARCH_AT91SAM9G45) ++#if !defined(CONFIG_SOC_AT91SAM9G45) + #define at91sam9g45_soc at91_boot_soc + #endif + +-#if !defined(CONFIG_ARCH_AT91SAM9RL) ++#if !defined(CONFIG_SOC_AT91SAM9RL) + #define at91sam9rl_soc at91_boot_soc + #endif + +-#if !defined(CONFIG_ARCH_AT91SAM9X5) ++#if !defined(CONFIG_SOC_AT91SAM9X5) + #define at91sam9x5_soc at91_boot_soc + #endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0023-ARM-at91-dt-do-not-specify-the-board-any-more.patch b/patches.at91/0023-ARM-at91-dt-do-not-specify-the-board-any-more.patch new file mode 100644 index 000000000000..5f968506f6d9 --- /dev/null +++ b/patches.at91/0023-ARM-at91-dt-do-not-specify-the-board-any-more.patch @@ -0,0 +1,42 @@ +From 77a5977e7fdc175bb1963143b80ad2a74cf3d9b8 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 1 Mar 2012 14:47:44 +0800 +Subject: ARM: at91/dt: do not specify the board any more + +This will allow to add any board to a compiled kernel by just passing the DTB. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/board-dt.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c +index c18d4d3..a1fce05 100644 +--- a/arch/arm/mach-at91/board-dt.c ++++ b/arch/arm/mach-at91/board-dt.c +@@ -1,10 +1,6 @@ + /* + * Setup code for AT91SAM Evaluation Kits with Device Tree support + * +- * Covers: * AT91SAM9G45-EKES board +- * * AT91SAM9M10-EKES board +- * * AT91SAM9M10G45-EK board +- * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + * +@@ -49,9 +45,7 @@ static void __init at91_dt_device_init(void) + } + + static const char *at91_dt_board_compat[] __initdata = { +- "atmel,at91sam9m10g45ek", +- "atmel,at91sam9x5ek", +- "calao,usb-a9g20", ++ "atmel,at91sam9", + NULL + }; + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0024-ARM-at91-add-defconfig-for-device-tree.patch b/patches.at91/0024-ARM-at91-add-defconfig-for-device-tree.patch new file mode 100644 index 000000000000..9ae95597c5db --- /dev/null +++ b/patches.at91/0024-ARM-at91-add-defconfig-for-device-tree.patch @@ -0,0 +1,220 @@ +From 73aa3911713fc739b9213475b4ff86d85d80d113 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun, 8 Apr 2012 17:40:06 +0200 +Subject: ARM: at91: add defconfig for device tree + +This will enable all current SoC support on DT (9260, 9g20, 9g45 family +and 9x5 family). + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/configs/at91_dt_defconfig | 196 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 196 insertions(+) + create mode 100644 arch/arm/configs/at91_dt_defconfig + +diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig +new file mode 100644 +index 0000000..67bc571 +--- /dev/null ++++ b/arch/arm/configs/at91_dt_defconfig +@@ -0,0 +1,196 @@ ++CONFIG_EXPERIMENTAL=y ++# CONFIG_LOCALVERSION_AUTO is not set ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_EMBEDDED=y ++CONFIG_SLAB=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_ARCH_AT91=y ++CONFIG_SOC_AT91SAM9260=y ++CONFIG_SOC_AT91SAM9263=y ++CONFIG_SOC_AT91SAM9G45=y ++CONFIG_SOC_AT91SAM9X5=y ++CONFIG_MACH_AT91SAM_DT=y ++CONFIG_AT91_PROGRAMMABLE_CLOCKS=y ++CONFIG_AT91_TIMER_HZ=128 ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++CONFIG_LEDS=y ++CONFIG_LEDS_CPU=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" ++CONFIG_KEXEC=y ++CONFIG_AUTO_ZRELADDR=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_PNP=y ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++CONFIG_IPV6=y ++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET6_XFRM_MODE_BEET is not set ++CONFIG_IPV6_SIT_6RD=y ++# CONFIG_WIRELESS is not set ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_MTD=y ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_NAND=y ++CONFIG_MTD_NAND_ATMEL=y ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_GLUEBI=y ++CONFIG_PROC_DEVICETREE=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=4 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++CONFIG_ATMEL_PWM=y ++CONFIG_ATMEL_TCLIB=y ++CONFIG_EEPROM_93CX6=m ++CONFIG_SCSI=y ++CONFIG_BLK_DEV_SD=y ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++CONFIG_MACB=y ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_FARADAY is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++CONFIG_DAVICOM_PHY=y ++CONFIG_MICREL_PHY=y ++# CONFIG_WLAN is not set ++CONFIG_INPUT_POLLDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 ++CONFIG_INPUT_JOYDEV=y ++CONFIG_INPUT_EVDEV=y ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_SERIO is not set ++CONFIG_LEGACY_PTY_COUNT=4 ++CONFIG_SERIAL_ATMEL=y ++CONFIG_SERIAL_ATMEL_CONSOLE=y ++CONFIG_HW_RANDOM=y ++CONFIG_I2C=y ++CONFIG_I2C_GPIO=y ++CONFIG_SPI=y ++CONFIG_SPI_ATMEL=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_AT91SAM9X_WATCHDOG=y ++CONFIG_SSB=m ++CONFIG_FB=y ++CONFIG_FB_MODE_HELPERS=y ++CONFIG_FB_ATMEL=y ++CONFIG_BACKLIGHT_LCD_SUPPORT=y ++# CONFIG_LCD_CLASS_DEVICE is not set ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_ATMEL_LCDC=y ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y ++CONFIG_FONTS=y ++CONFIG_FONT_8x8=y ++CONFIG_FONT_ACORN_8x8=y ++CONFIG_FONT_MINI_4x6=y ++CONFIG_LOGO=y ++# CONFIG_HID_SUPPORT is not set ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_ACM=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_SERIAL=y ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_FTDI_SIO=y ++CONFIG_USB_SERIAL_PL2303=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_AT91=m ++CONFIG_USB_ATMEL_USBA=m ++CONFIG_USB_ETH=m ++CONFIG_USB_GADGETFS=m ++CONFIG_USB_CDC_COMPOSITE=m ++CONFIG_USB_G_ACM_MS=m ++CONFIG_USB_G_MULTI=m ++CONFIG_USB_G_MULTI_CDC=y ++CONFIG_MMC=y ++CONFIG_MMC_ATMELMCI=y ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DRV_AT91RM9200=y ++CONFIG_RTC_DRV_AT91SAM9=y ++CONFIG_DMADEVICES=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXT2_FS=y ++CONFIG_FANOTIFY=y ++CONFIG_VFAT_FS=y ++CONFIG_TMPFS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_850=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_STRIP_ASM_SYMS=y ++CONFIG_DEBUG_FS=y ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_FTRACE is not set ++CONFIG_DEBUG_USER=y ++CONFIG_CRYPTO=y ++CONFIG_CRYPTO_ECB=y ++CONFIG_CRYPTO_AES=y ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_USER_API_HASH=m ++CONFIG_CRYPTO_USER_API_SKCIPHER=m ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_CCITT=m ++CONFIG_CRC_ITU_T=m ++CONFIG_CRC7=m ++CONFIG_AVERAGE=y +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0025-ARM-at91-add-at91sam9260-DT-support.patch b/patches.at91/0025-ARM-at91-add-at91sam9260-DT-support.patch new file mode 100644 index 000000000000..48bd9750d284 --- /dev/null +++ b/patches.at91/0025-ARM-at91-add-at91sam9260-DT-support.patch @@ -0,0 +1,522 @@ +From d795dab6d067cd5734cd7af4b67634f3b3961bd7 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon, 9 Apr 2012 19:26:33 +0800 +Subject: ARM: at91: add at91sam9260 DT support + +The at91sam9260 and at91sam9g20 share most of the same IP. +So udpate the node property in the at91sam9g20 only. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/at91sam9260.dtsi | 238 +++++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/at91sam9g20.dtsi | 226 +---------------------------------- + arch/arm/mach-at91/Makefile.boot | 1 + + 3 files changed, 242 insertions(+), 223 deletions(-) + create mode 100644 arch/arm/boot/dts/at91sam9260.dtsi + +diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi +new file mode 100644 +index 0000000..f4605ff +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9260.dtsi +@@ -0,0 +1,238 @@ ++/* ++ * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC ++ * ++ * Copyright (C) 2011 Atmel, ++ * 2011 Nicolas Ferre , ++ * 2011 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 or later. ++ */ ++ ++/include/ "skeleton.dtsi" ++ ++/ { ++ model = "Atmel AT91SAM9260 family SoC"; ++ compatible = "atmel,at91sam9260"; ++ interrupt-parent = <&aic>; ++ ++ aliases { ++ serial0 = &dbgu; ++ serial1 = &usart0; ++ serial2 = &usart1; ++ serial3 = &usart2; ++ serial4 = &usart3; ++ serial5 = &usart4; ++ serial6 = &usart5; ++ gpio0 = &pioA; ++ gpio1 = &pioB; ++ gpio2 = &pioC; ++ tcb0 = &tcb0; ++ tcb1 = &tcb1; ++ }; ++ cpus { ++ cpu@0 { ++ compatible = "arm,arm926ejs"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++ ahb { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ apb { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ aic: interrupt-controller@fffff000 { ++ #interrupt-cells = <2>; ++ compatible = "atmel,at91rm9200-aic"; ++ interrupt-controller; ++ reg = <0xfffff000 0x200>; ++ }; ++ ++ ramc0: ramc@ffffea00 { ++ compatible = "atmel,at91sam9260-sdramc"; ++ reg = <0xffffea00 0x200>; ++ }; ++ ++ pmc: pmc@fffffc00 { ++ compatible = "atmel,at91rm9200-pmc"; ++ reg = <0xfffffc00 0x100>; ++ }; ++ ++ rstc@fffffd00 { ++ compatible = "atmel,at91sam9260-rstc"; ++ reg = <0xfffffd00 0x10>; ++ }; ++ ++ shdwc@fffffd10 { ++ compatible = "atmel,at91sam9260-shdwc"; ++ reg = <0xfffffd10 0x10>; ++ }; ++ ++ pit: timer@fffffd30 { ++ compatible = "atmel,at91sam9260-pit"; ++ reg = <0xfffffd30 0xf>; ++ interrupts = <1 4>; ++ }; ++ ++ tcb0: timer@fffa0000 { ++ compatible = "atmel,at91rm9200-tcb"; ++ reg = <0xfffa0000 0x100>; ++ interrupts = <17 4 18 4 19 4>; ++ }; ++ ++ tcb1: timer@fffdc000 { ++ compatible = "atmel,at91rm9200-tcb"; ++ reg = <0xfffdc000 0x100>; ++ interrupts = <26 4 27 4 28 4>; ++ }; ++ ++ pioA: gpio@fffff400 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff400 0x100>; ++ interrupts = <2 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioB: gpio@fffff600 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff600 0x100>; ++ interrupts = <3 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioC: gpio@fffff800 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff800 0x100>; ++ interrupts = <4 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ dbgu: serial@fffff200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffff200 0x200>; ++ interrupts = <1 4>; ++ status = "disabled"; ++ }; ++ ++ usart0: serial@fffb0000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffb0000 0x200>; ++ interrupts = <6 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart1: serial@fffb4000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffb4000 0x200>; ++ interrupts = <7 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart2: serial@fffb8000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffb8000 0x200>; ++ interrupts = <8 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart3: serial@fffd0000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffd0000 0x200>; ++ interrupts = <23 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart4: serial@fffd4000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffd4000 0x200>; ++ interrupts = <24 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart5: serial@fffd8000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffd8000 0x200>; ++ interrupts = <25 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ macb0: ethernet@fffc4000 { ++ compatible = "cdns,at32ap7000-macb", "cdns,macb"; ++ reg = <0xfffc4000 0x100>; ++ interrupts = <21 4>; ++ status = "disabled"; ++ }; ++ ++ usb1: gadget@fffa4000 { ++ compatible = "atmel,at91rm9200-udc"; ++ reg = <0xfffa4000 0x4000>; ++ interrupts = <10 4>; ++ status = "disabled"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ compatible = "atmel,at91rm9200-nand"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x40000000 0x10000000 ++ 0xffffe800 0x200 ++ >; ++ atmel,nand-addr-offset = <21>; ++ atmel,nand-cmd-offset = <22>; ++ gpios = <&pioC 13 0 ++ &pioC 14 0 ++ 0 ++ >; ++ status = "disabled"; ++ }; ++ ++ usb0: ohci@00500000 { ++ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; ++ reg = <0x00500000 0x100000>; ++ interrupts = <20 4>; ++ status = "disabled"; ++ }; ++ }; ++ ++ i2c@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&pioA 23 0 /* sda */ ++ &pioA 24 0 /* scl */ ++ >; ++ i2c-gpio,sda-open-drain; ++ i2c-gpio,scl-open-drain; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi +index 773ef48..0eb1a75 100644 +--- a/arch/arm/boot/dts/at91sam9g20.dtsi ++++ b/arch/arm/boot/dts/at91sam9g20.dtsi +@@ -1,238 +1,18 @@ + /* + * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC + * +- * Copyright (C) 2011 Atmel, +- * 2011 Nicolas Ferre , +- * 2011 Jean-Christophe PLAGNIOL-VILLARD ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * +- * Licensed under GPLv2 or later. ++ * Licensed under GPLv2. + */ + +-/include/ "skeleton.dtsi" ++/include/ "at91sam9260.dtsi" + + / { + model = "Atmel AT91SAM9G20 family SoC"; + compatible = "atmel,at91sam9g20"; +- interrupt-parent = <&aic>; +- +- aliases { +- serial0 = &dbgu; +- serial1 = &usart0; +- serial2 = &usart1; +- serial3 = &usart2; +- serial4 = &usart3; +- serial5 = &usart4; +- serial6 = &usart5; +- gpio0 = &pioA; +- gpio1 = &pioB; +- gpio2 = &pioC; +- tcb0 = &tcb0; +- tcb1 = &tcb1; +- }; +- cpus { +- cpu@0 { +- compatible = "arm,arm926ejs"; +- }; +- }; + + memory { + reg = <0x20000000 0x08000000>; + }; +- +- ahb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- apb { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- aic: interrupt-controller@fffff000 { +- #interrupt-cells = <2>; +- compatible = "atmel,at91rm9200-aic"; +- interrupt-controller; +- reg = <0xfffff000 0x200>; +- }; +- +- ramc0: ramc@ffffea00 { +- compatible = "atmel,at91sam9260-sdramc"; +- reg = <0xffffea00 0x200>; +- }; +- +- pmc: pmc@fffffc00 { +- compatible = "atmel,at91rm9200-pmc"; +- reg = <0xfffffc00 0x100>; +- }; +- +- rstc@fffffd00 { +- compatible = "atmel,at91sam9260-rstc"; +- reg = <0xfffffd00 0x10>; +- }; +- +- shdwc@fffffd10 { +- compatible = "atmel,at91sam9260-shdwc"; +- reg = <0xfffffd10 0x10>; +- }; +- +- pit: timer@fffffd30 { +- compatible = "atmel,at91sam9260-pit"; +- reg = <0xfffffd30 0xf>; +- interrupts = <1 4>; +- }; +- +- tcb0: timer@fffa0000 { +- compatible = "atmel,at91rm9200-tcb"; +- reg = <0xfffa0000 0x100>; +- interrupts = <17 4 18 4 19 4>; +- }; +- +- tcb1: timer@fffdc000 { +- compatible = "atmel,at91rm9200-tcb"; +- reg = <0xfffdc000 0x100>; +- interrupts = <26 4 27 4 28 4>; +- }; +- +- pioA: gpio@fffff400 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff400 0x100>; +- interrupts = <2 4>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- }; +- +- pioB: gpio@fffff600 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff600 0x100>; +- interrupts = <3 4>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- }; +- +- pioC: gpio@fffff800 { +- compatible = "atmel,at91rm9200-gpio"; +- reg = <0xfffff800 0x100>; +- interrupts = <4 4>; +- #gpio-cells = <2>; +- gpio-controller; +- interrupt-controller; +- }; +- +- dbgu: serial@fffff200 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffff200 0x200>; +- interrupts = <1 4>; +- status = "disabled"; +- }; +- +- usart0: serial@fffb0000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb0000 0x200>; +- interrupts = <6 4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- +- usart1: serial@fffb4000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb4000 0x200>; +- interrupts = <7 4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- +- usart2: serial@fffb8000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffb8000 0x200>; +- interrupts = <8 4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- +- usart3: serial@fffd0000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffd0000 0x200>; +- interrupts = <23 4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- +- usart4: serial@fffd4000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffd4000 0x200>; +- interrupts = <24 4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- +- usart5: serial@fffd8000 { +- compatible = "atmel,at91sam9260-usart"; +- reg = <0xfffd8000 0x200>; +- interrupts = <25 4>; +- atmel,use-dma-rx; +- atmel,use-dma-tx; +- status = "disabled"; +- }; +- +- macb0: ethernet@fffc4000 { +- compatible = "cdns,at32ap7000-macb", "cdns,macb"; +- reg = <0xfffc4000 0x100>; +- interrupts = <21 4>; +- status = "disabled"; +- }; +- +- usb1: gadget@fffa4000 { +- compatible = "atmel,at91rm9200-udc"; +- reg = <0xfffa4000 0x4000>; +- interrupts = <10 4>; +- status = "disabled"; +- }; +- }; +- +- nand0: nand@40000000 { +- compatible = "atmel,at91rm9200-nand"; +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0x40000000 0x10000000 +- 0xffffe800 0x200 +- >; +- atmel,nand-addr-offset = <21>; +- atmel,nand-cmd-offset = <22>; +- gpios = <&pioC 13 0 +- &pioC 14 0 +- 0 +- >; +- status = "disabled"; +- }; +- +- usb0: ohci@00500000 { +- compatible = "atmel,at91rm9200-ohci", "usb-ohci"; +- reg = <0x00500000 0x100000>; +- interrupts = <20 4>; +- status = "disabled"; +- }; +- }; +- +- i2c@0 { +- compatible = "i2c-gpio"; +- gpios = <&pioA 23 0 /* sda */ +- &pioA 24 0 /* scl */ +- >; +- i2c-gpio,sda-open-drain; +- i2c-gpio,scl-open-drain; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; + }; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 0da66ca..0c2336c 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -14,6 +14,7 @@ initrd_phys-y := 0x20410000 + endif + + # Keep dtb files sorted alphabetically for each SoC ++# sam9260 + # sam9g20 + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb + # sam9g45 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0026-arm-at91-add-Calao-TNY-A9260-and-TNY-A9G20-board-sup.patch b/patches.at91/0026-arm-at91-add-Calao-TNY-A9260-and-TNY-A9G20-board-sup.patch new file mode 100644 index 000000000000..002aa4488239 --- /dev/null +++ b/patches.at91/0026-arm-at91-add-Calao-TNY-A9260-and-TNY-A9G20-board-sup.patch @@ -0,0 +1,165 @@ +From 735aea5075e405af25ecdaea8a00091fa0b45c29 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon, 30 Jan 2012 23:45:52 +0800 +Subject: arm: at91: add Calao TNY-A9260 and TNY-A9G20 board support + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/tny_a9260.dts | 15 ++++++ + arch/arm/boot/dts/tny_a9260_common.dtsi | 83 +++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/tny_a9g20.dts | 15 ++++++ + arch/arm/mach-at91/Makefile.boot | 2 + + 4 files changed, 115 insertions(+) + create mode 100644 arch/arm/boot/dts/tny_a9260.dts + create mode 100644 arch/arm/boot/dts/tny_a9260_common.dtsi + create mode 100644 arch/arm/boot/dts/tny_a9g20.dts + +diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts +new file mode 100644 +index 0000000..367a16d +--- /dev/null ++++ b/arch/arm/boot/dts/tny_a9260.dts +@@ -0,0 +1,15 @@ ++/* ++ * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2. ++ */ ++/dts-v1/; ++/include/ "at91sam9260.dtsi" ++/include/ "tny_a9260_common.dtsi" ++ ++/ { ++ model = "Calao TNY A9260"; ++ compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9"; ++}; +diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi +new file mode 100644 +index 0000000..0e6d3de +--- /dev/null ++++ b/arch/arm/boot/dts/tny_a9260_common.dtsi +@@ -0,0 +1,83 @@ ++/* ++ * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2. ++ */ ++ ++/ { ++ chosen { ++ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x4000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <12000000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@fffff200 { ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ ++ at91bootstrap@0 { ++ label = "at91bootstrap"; ++ reg = <0x0 0x20000>; ++ }; ++ ++ barebox@20000 { ++ label = "barebox"; ++ reg = <0x20000 0x40000>; ++ }; ++ ++ bareboxenv@60000 { ++ label = "bareboxenv"; ++ reg = <0x60000 0x20000>; ++ }; ++ ++ bareboxenv2@80000 { ++ label = "bareboxenv2"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ ++ kernel@a0000 { ++ label = "kernel"; ++ reg = <0xc0000 0x400000>; ++ }; ++ ++ rootfs@4a0000 { ++ label = "rootfs"; ++ reg = <0x4c0000 0x7800000>; ++ }; ++ ++ data@7ca0000 { ++ label = "data"; ++ reg = <0x7cc0000 0x8340000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts +new file mode 100644 +index 0000000..e1ab64c +--- /dev/null ++++ b/arch/arm/boot/dts/tny_a9g20.dts +@@ -0,0 +1,15 @@ ++/* ++ * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2. ++ */ ++/dts-v1/; ++/include/ "at91sam9g20.dtsi" ++/include/ "tny_a9260_common.dtsi" ++ ++/ { ++ model = "Calao TNY A9G20"; ++ compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 0c2336c..bdf9841 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -15,7 +15,9 @@ endif + + # Keep dtb files sorted alphabetically for each SoC + # sam9260 ++dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb + # sam9g20 ++dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb + # sam9g45 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0027-ARM-at91-add-at91sam9g20ek-boards-dt-support.patch b/patches.at91/0027-ARM-at91-add-at91sam9g20ek-boards-dt-support.patch new file mode 100644 index 000000000000..73d1a909e38b --- /dev/null +++ b/patches.at91/0027-ARM-at91-add-at91sam9g20ek-boards-dt-support.patch @@ -0,0 +1,253 @@ +From a72c0834c3f846f3fe9f2c782c8d6a67df258458 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon, 13 Feb 2012 00:54:47 +0800 +Subject: ARM: at91: add at91sam9g20ek boards dt support + +Add both board revision support 1mmc and 2mmc and use a dtsi for common part. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/at91sam9g20ek.dts | 29 ++++++ + arch/arm/boot/dts/at91sam9g20ek_2mmc.dts | 29 ++++++ + arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 142 ++++++++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 2 + + 4 files changed, 202 insertions(+) + create mode 100644 arch/arm/boot/dts/at91sam9g20ek.dts + create mode 100644 arch/arm/boot/dts/at91sam9g20ek_2mmc.dts + create mode 100644 arch/arm/boot/dts/at91sam9g20ek_common.dtsi + +diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts +new file mode 100644 +index 0000000..e5324bf +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9g20ek.dts +@@ -0,0 +1,29 @@ ++/* ++ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2. ++ */ ++/dts-v1/; ++/include/ "at91sam9g20ek_common.dtsi" ++ ++/ { ++ model = "Atmel at91sam9g20ek"; ++ compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ ds1 { ++ label = "ds1"; ++ gpios = <&pioA 9 0>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ ds5 { ++ label = "ds5"; ++ gpios = <&pioA 6 1>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +new file mode 100644 +index 0000000..f1b2e14 +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +@@ -0,0 +1,29 @@ ++/* ++ * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2. ++ */ ++/dts-v1/; ++/include/ "at91sam9g20ek_common.dtsi" ++ ++/ { ++ model = "Atmel at91sam9g20ek 2 mmc"; ++ compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ ds1 { ++ label = "ds1"; ++ gpios = <&pioB 9 0>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ ds5 { ++ label = "ds5"; ++ gpios = <&pioB 8 1>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +new file mode 100644 +index 0000000..b06c0db +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +@@ -0,0 +1,142 @@ ++/* ++ * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2. ++ */ ++/include/ "at91sam9g20.dtsi" ++ ++/ { ++ ++ chosen { ++ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x4000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <18432000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@fffff200 { ++ status = "okay"; ++ }; ++ ++ usart0: serial@fffb0000 { ++ status = "okay"; ++ }; ++ ++ usart1: serial@fffb4000 { ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@fffc4000 { ++ phy-mode = "rmii"; ++ status = "okay"; ++ }; ++ ++ usb1: gadget@fffa4000 { ++ atmel,vbus-gpio = <&pioC 5 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ ++ at91bootstrap@0 { ++ label = "at91bootstrap"; ++ reg = <0x0 0x20000>; ++ }; ++ ++ barebox@20000 { ++ label = "barebox"; ++ reg = <0x20000 0x40000>; ++ }; ++ ++ bareboxenv@60000 { ++ label = "bareboxenv"; ++ reg = <0x60000 0x20000>; ++ }; ++ ++ bareboxenv2@80000 { ++ label = "bareboxenv2"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ ++ kernel@a0000 { ++ label = "kernel"; ++ reg = <0xc0000 0x400000>; ++ }; ++ ++ rootfs@4a0000 { ++ label = "rootfs"; ++ reg = <0x4c0000 0x7800000>; ++ }; ++ ++ data@7ca0000 { ++ label = "data"; ++ reg = <0x7cc0000 0x8340000>; ++ }; ++ }; ++ ++ usb0: ohci@00500000 { ++ num-ports = <2>; ++ status = "okay"; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ ++ 24c512@50 { ++ compatible = "24c512"; ++ reg = <0x50>; ++ }; ++ ++ wm8731@1b { ++ compatible = "wm8731"; ++ reg = <0x1b>; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ btn3 { ++ label = "Buttin 3"; ++ gpios = <&pioA 30 1>; ++ linux,code = <0x103>; ++ gpio-key,wakeup; ++ }; ++ ++ btn4 { ++ label = "Buttin 4"; ++ gpios = <&pioA 31 1>; ++ linux,code = <0x104>; ++ gpio-key,wakeup; ++ }; ++ }; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index bdf9841..30d6c10 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -17,6 +17,8 @@ endif + # sam9260 + dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb + # sam9g20 ++dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb ++dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb + # sam9g45 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0028-ARM-at91-USB-A926x-update-nand-partition.patch b/patches.at91/0028-ARM-at91-USB-A926x-update-nand-partition.patch new file mode 100644 index 000000000000..d8029a144ce8 --- /dev/null +++ b/patches.at91/0028-ARM-at91-USB-A926x-update-nand-partition.patch @@ -0,0 +1,64 @@ +From b2b5334c32e6c1c8c0333279e4ee9600b3d4d34a Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Wed, 11 Apr 2012 23:40:31 +0800 +Subject: ARM: at91: USB A926x update nand partition + +We now store the dtb in a nand partition. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/usb_a9g20.dts | 11 ++++++++--- + arch/arm/mach-at91/board-usb-a926x.c | 4 ++++ + 2 files changed, 12 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts +index 7c2399c..0f88ec8 100644 +--- a/arch/arm/boot/dts/usb_a9g20.dts ++++ b/arch/arm/boot/dts/usb_a9g20.dts +@@ -74,19 +74,24 @@ + reg = <0x80000 0x20000>; + }; + ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ + kernel@a0000 { + label = "kernel"; +- reg = <0xa0000 0x400000>; ++ reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; +- reg = <0x4a0000 0x7800000>; ++ reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; +- reg = <0x7ca0000 0x8360000>; ++ reg = <0x7cc0000 0x8340000>; + }; + }; + +diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c +index 332ecd4..95393fc 100644 +--- a/arch/arm/mach-at91/board-usb-a926x.c ++++ b/arch/arm/mach-at91/board-usb-a926x.c +@@ -172,6 +172,10 @@ static struct mtd_partition __initdata ek_nand_partition[] = { + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_128K, + }, { ++ .name = "oftree", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_128K, ++ }, { + .name = "kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = 4 * SZ_1M, +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0029-ARM-at91-Calao-USB-A926x-factorize-common-binding-in.patch b/patches.at91/0029-ARM-at91-Calao-USB-A926x-factorize-common-binding-in.patch new file mode 100644 index 000000000000..d3b4a11e21ff --- /dev/null +++ b/patches.at91/0029-ARM-at91-Calao-USB-A926x-factorize-common-binding-in.patch @@ -0,0 +1,268 @@ +From 23f3c5a2f5746c2e1eca2364ea6fb3d3e4515cf3 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Wed, 11 Apr 2012 23:42:44 +0800 +Subject: ARM: at91: Calao USB A926x factorize common binding in + usb_a9260_common + +This will simplify the adding of the A9260. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/usb_a9260_common.dtsi | 117 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/usb_a9g20.dts | 107 +---------------------------- + 2 files changed, 118 insertions(+), 106 deletions(-) + create mode 100644 arch/arm/boot/dts/usb_a9260_common.dtsi + +diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi +new file mode 100644 +index 0000000..e70d229 +--- /dev/null ++++ b/arch/arm/boot/dts/usb_a9260_common.dtsi +@@ -0,0 +1,117 @@ ++/* ++ * usb_a926x.dts - Device Tree file for Caloa USB A926x board ++ * ++ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 or later. ++ */ ++ ++/ { ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <12000000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@fffff200 { ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@fffc4000 { ++ phy-mode = "rmii"; ++ status = "okay"; ++ }; ++ ++ usb1: gadget@fffa4000 { ++ atmel,vbus-gpio = <&pioC 5 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ ++ at91bootstrap@0 { ++ label = "at91bootstrap"; ++ reg = <0x0 0x20000>; ++ }; ++ ++ barebox@20000 { ++ label = "barebox"; ++ reg = <0x20000 0x40000>; ++ }; ++ ++ bareboxenv@60000 { ++ label = "bareboxenv"; ++ reg = <0x60000 0x20000>; ++ }; ++ ++ bareboxenv2@80000 { ++ label = "bareboxenv2"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ ++ kernel@a0000 { ++ label = "kernel"; ++ reg = <0xc0000 0x400000>; ++ }; ++ ++ rootfs@4a0000 { ++ label = "rootfs"; ++ reg = <0x4c0000 0x7800000>; ++ }; ++ ++ data@7ca0000 { ++ label = "data"; ++ reg = <0x7cc0000 0x8340000>; ++ }; ++ }; ++ ++ usb0: ohci@00500000 { ++ num-ports = <2>; ++ status = "okay"; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ user_led { ++ label = "user_led"; ++ gpios = <&pioB 21 1>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ user_pb { ++ label = "user_pb"; ++ gpios = <&pioB 10 1>; ++ linux,code = <28>; ++ gpio-key,wakeup; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts +index 0f88ec8..2dacb16c 100644 +--- a/arch/arm/boot/dts/usb_a9g20.dts ++++ b/arch/arm/boot/dts/usb_a9g20.dts +@@ -7,6 +7,7 @@ + */ + /dts-v1/; + /include/ "at91sam9g20.dtsi" ++/include/ "usb_a9260_common.dtsi" + + / { + model = "Calao USB A9G20"; +@@ -20,113 +21,7 @@ + reg = <0x20000000 0x4000000>; + }; + +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- main_clock: clock@0 { +- compatible = "atmel,osc", "fixed-clock"; +- clock-frequency = <12000000>; +- }; +- }; +- +- ahb { +- apb { +- dbgu: serial@fffff200 { +- status = "okay"; +- }; +- +- macb0: ethernet@fffc4000 { +- phy-mode = "rmii"; +- status = "okay"; +- }; +- +- usb1: gadget@fffa4000 { +- atmel,vbus-gpio = <&pioC 5 0>; +- status = "okay"; +- }; +- }; +- +- nand0: nand@40000000 { +- nand-bus-width = <8>; +- nand-ecc-mode = "soft"; +- nand-on-flash-bbt; +- status = "okay"; +- +- at91bootstrap@0 { +- label = "at91bootstrap"; +- reg = <0x0 0x20000>; +- }; +- +- barebox@20000 { +- label = "barebox"; +- reg = <0x20000 0x40000>; +- }; +- +- bareboxenv@60000 { +- label = "bareboxenv"; +- reg = <0x60000 0x20000>; +- }; +- +- bareboxenv2@80000 { +- label = "bareboxenv2"; +- reg = <0x80000 0x20000>; +- }; +- +- oftree@80000 { +- label = "oftree"; +- reg = <0xa0000 0x20000>; +- }; +- +- kernel@a0000 { +- label = "kernel"; +- reg = <0xc0000 0x400000>; +- }; +- +- rootfs@4a0000 { +- label = "rootfs"; +- reg = <0x4c0000 0x7800000>; +- }; +- +- data@7ca0000 { +- label = "data"; +- reg = <0x7cc0000 0x8340000>; +- }; +- }; +- +- usb0: ohci@00500000 { +- num-ports = <2>; +- status = "okay"; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- user_led { +- label = "user_led"; +- gpios = <&pioB 21 1>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- user_pb { +- label = "user_pb"; +- gpios = <&pioB 10 1>; +- linux,code = <28>; +- gpio-key,wakeup; +- }; +- }; +- + i2c@0 { +- status = "okay"; +- + rv3029c2@56 { + compatible = "rv3029c2"; + reg = <0x56>; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0030-ARM-at91-DT-add-Calao-USB-A9260-DT-support.patch b/patches.at91/0030-ARM-at91-DT-add-Calao-USB-A9260-DT-support.patch new file mode 100644 index 000000000000..e3259ae532e1 --- /dev/null +++ b/patches.at91/0030-ARM-at91-DT-add-Calao-USB-A9260-DT-support.patch @@ -0,0 +1,57 @@ +From 83be7b15e8dea5beb4d3299835b79347c3148fd2 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon, 9 Apr 2012 14:43:34 +0800 +Subject: ARM: at91: DT: add Calao USB A9260 DT support + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/usb_a9260.dts | 23 +++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 1 + + 2 files changed, 24 insertions(+) + create mode 100644 arch/arm/boot/dts/usb_a9260.dts + +diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts +new file mode 100644 +index 0000000..2962160 +--- /dev/null ++++ b/arch/arm/boot/dts/usb_a9260.dts +@@ -0,0 +1,23 @@ ++/* ++ * usb_a9260.dts - Device Tree file for Caloa USB A9260 board ++ * ++ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 or later. ++ */ ++/dts-v1/; ++/include/ "at91sam9260.dtsi" ++/include/ "usb_a9260_common.dtsi" ++ ++/ { ++ model = "Calao USB A9260"; ++ compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x4000000>; ++ }; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 30d6c10..b2ac536 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -16,6 +16,7 @@ endif + # Keep dtb files sorted alphabetically for each SoC + # sam9260 + dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb ++dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb + # sam9g20 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0031-ARM-at91-standard-device-init-only-if-DT-is-not-popu.patch b/patches.at91/0031-ARM-at91-standard-device-init-only-if-DT-is-not-popu.patch new file mode 100644 index 000000000000..f27c8142d2ba --- /dev/null +++ b/patches.at91/0031-ARM-at91-standard-device-init-only-if-DT-is-not-popu.patch @@ -0,0 +1,115 @@ +From 07e34d884cb904668fe1e413fe10958a65de3c57 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue, 28 Feb 2012 15:23:43 +0800 +Subject: ARM: at91: standard device init only if DT is not populated. + +This will avoid the CONFIG_OF on the *_devices.c as this file is deprecated +for DT support. + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/at91sam9260_devices.c | 20 +++----------------- + arch/arm/mach-at91/at91sam9g45_devices.c | 30 ++++-------------------------- + 2 files changed, 7 insertions(+), 43 deletions(-) + +diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c +index ad00fe9..d556de1 100644 +--- a/arch/arm/mach-at91/at91sam9260_devices.c ++++ b/arch/arm/mach-at91/at91sam9260_devices.c +@@ -702,25 +702,8 @@ static struct platform_device at91sam9260_tcb1_device = { + .num_resources = ARRAY_SIZE(tcb1_resources), + }; + +-#if defined(CONFIG_OF) +-static struct of_device_id tcb_ids[] = { +- { .compatible = "atmel,at91rm9200-tcb" }, +- { /*sentinel*/ } +-}; +-#endif +- + static void __init at91_add_device_tc(void) + { +-#if defined(CONFIG_OF) +- struct device_node *np; +- +- np = of_find_matching_node(NULL, tcb_ids); +- if (np) { +- of_node_put(np); +- return; +- } +-#endif +- + platform_device_register(&at91sam9260_tcb0_device); + platform_device_register(&at91sam9260_tcb1_device); + } +@@ -1364,6 +1347,9 @@ void __init at91_add_device_cf(struct at91_cf_data * data) {} + */ + static int __init at91_add_standard_devices(void) + { ++ if (of_have_populated_dt()) ++ return 0; ++ + at91_add_device_rtt(); + at91_add_device_watchdog(); + at91_add_device_tc(); +diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c +index db2f88c2..35bd42d 100644 +--- a/arch/arm/mach-at91/at91sam9g45_devices.c ++++ b/arch/arm/mach-at91/at91sam9g45_devices.c +@@ -69,15 +69,7 @@ static struct platform_device at_hdmac_device = { + + void __init at91_add_device_hdmac(void) + { +-#if defined(CONFIG_OF) +- struct device_node *of_node = +- of_find_node_by_name(NULL, "dma-controller"); +- +- if (of_node) +- of_node_put(of_node); +- else +-#endif +- platform_device_register(&at_hdmac_device); ++ platform_device_register(&at_hdmac_device); + } + #else + void __init at91_add_device_hdmac(void) {} +@@ -1094,25 +1086,8 @@ static struct platform_device at91sam9g45_tcb1_device = { + .num_resources = ARRAY_SIZE(tcb1_resources), + }; + +-#if defined(CONFIG_OF) +-static struct of_device_id tcb_ids[] = { +- { .compatible = "atmel,at91rm9200-tcb" }, +- { /*sentinel*/ } +-}; +-#endif +- + static void __init at91_add_device_tc(void) + { +-#if defined(CONFIG_OF) +- struct device_node *np; +- +- np = of_find_matching_node(NULL, tcb_ids); +- if (np) { +- of_node_put(np); +- return; +- } +-#endif +- + platform_device_register(&at91sam9g45_tcb0_device); + platform_device_register(&at91sam9g45_tcb1_device); + } +@@ -1763,6 +1738,9 @@ void __init at91_add_device_serial(void) {} + */ + static int __init at91_add_standard_devices(void) + { ++ if (of_have_populated_dt()) ++ return 0; ++ + at91_add_device_hdmac(); + at91_add_device_rtc(); + at91_add_device_rtt(); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0032-ARM-at91-add-at91sam9263-DT-support.patch b/patches.at91/0032-ARM-at91-add-at91sam9263-DT-support.patch new file mode 100644 index 000000000000..c624252fec83 --- /dev/null +++ b/patches.at91/0032-ARM-at91-add-at91sam9263-DT-support.patch @@ -0,0 +1,304 @@ +From 6703c4d1f42cf346f9a6f5f174f46c01ece33c90 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun, 26 Feb 2012 19:12:43 +0800 +Subject: ARM: at91: add at91sam9263 DT support + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/at91sam9263.dtsi | 220 +++++++++++++++++++++++++++++++ + arch/arm/mach-at91/at91sam9263.c | 10 ++ + arch/arm/mach-at91/at91sam9263_devices.c | 20 +++ + 3 files changed, 250 insertions(+) + create mode 100644 arch/arm/boot/dts/at91sam9263.dtsi + +diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi +new file mode 100644 +index 0000000..0209913 +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9263.dtsi +@@ -0,0 +1,220 @@ ++/* ++ * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 only. ++ */ ++ ++/include/ "skeleton.dtsi" ++ ++/ { ++ model = "Atmel AT91SAM9263 family SoC"; ++ compatible = "atmel,at91sam9263"; ++ interrupt-parent = <&aic>; ++ ++ aliases { ++ serial0 = &dbgu; ++ serial1 = &usart0; ++ serial2 = &usart1; ++ serial3 = &usart2; ++ gpio0 = &pioA; ++ gpio1 = &pioB; ++ gpio2 = &pioC; ++ gpio3 = &pioD; ++ gpio4 = &pioE; ++ tcb0 = &tcb0; ++ }; ++ cpus { ++ cpu@0 { ++ compatible = "arm,arm926ejs"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++ ahb { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ apb { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ aic: interrupt-controller@fffff000 { ++ #interrupt-cells = <2>; ++ compatible = "atmel,at91rm9200-aic"; ++ interrupt-controller; ++ reg = <0xfffff000 0x200>; ++ }; ++ ++ pmc: pmc@fffffc00 { ++ compatible = "atmel,at91rm9200-pmc"; ++ reg = <0xfffffc00 0x100>; ++ }; ++ ++ ramc: ramc@ffffe200 { ++ compatible = "atmel,at91sam9260-sdramc"; ++ reg = <0xffffe200 0x200 ++ 0xffffe800 0x200>; ++ }; ++ ++ pit: timer@fffffd30 { ++ compatible = "atmel,at91sam9260-pit"; ++ reg = <0xfffffd30 0xf>; ++ interrupts = <1 4>; ++ }; ++ ++ tcb0: timer@fff7c000 { ++ compatible = "atmel,at91rm9200-tcb"; ++ reg = <0xfff7c000 0x100>; ++ interrupts = <19 4>; ++ }; ++ ++ rstc@fffffd00 { ++ compatible = "atmel,at91sam9260-rstc"; ++ reg = <0xfffffd00 0x10>; ++ }; ++ ++ shdwc@fffffd10 { ++ compatible = "atmel,at91sam9260-shdwc"; ++ reg = <0xfffffd10 0x10>; ++ }; ++ ++ pioA: gpio@fffff200 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff200 0x100>; ++ interrupts = <2 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioB: gpio@fffff400 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff400 0x100>; ++ interrupts = <3 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioC: gpio@fffff600 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff600 0x100>; ++ interrupts = <4 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioD: gpio@fffff800 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffff800 0x100>; ++ interrupts = <4 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioE: gpio@fffffa00 { ++ compatible = "atmel,at91rm9200-gpio"; ++ reg = <0xfffffa00 0x100>; ++ interrupts = <4 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ dbgu: serial@ffffee00 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xffffee00 0x200>; ++ interrupts = <1 4>; ++ status = "disabled"; ++ }; ++ ++ usart0: serial@fff8c000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfff8c000 0x200>; ++ interrupts = <7 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart1: serial@fff90000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfff90000 0x200>; ++ interrupts = <8 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart2: serial@fff94000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfff94000 0x200>; ++ interrupts = <9 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ macb0: ethernet@fffbc000 { ++ compatible = "cdns,at32ap7000-macb", "cdns,macb"; ++ reg = <0xfffbc000 0x100>; ++ interrupts = <21 4>; ++ status = "disabled"; ++ }; ++ ++ usb1: gadget@fff78000 { ++ compatible = "atmel,at91rm9200-udc"; ++ reg = <0xfff78000 0x4000>; ++ interrupts = <24 4>; ++ status = "disabled"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ compatible = "atmel,at91rm9200-nand"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x40000000 0x10000000 ++ 0xffffe000 0x200 ++ >; ++ atmel,nand-addr-offset = <21>; ++ atmel,nand-cmd-offset = <22>; ++ gpios = <&pioA 22 0 ++ &pioD 15 0 ++ 0 ++ >; ++ status = "disabled"; ++ }; ++ ++ usb0: ohci@00a00000 { ++ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; ++ reg = <0x00a00000 0x100000>; ++ interrupts = <29 4>; ++ status = "disabled"; ++ }; ++ }; ++ ++ i2c@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&pioB 4 0 /* sda */ ++ &pioB 5 0 /* scl */ ++ >; ++ i2c-gpio,sda-open-drain; ++ i2c-gpio,scl-open-drain; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++}; +diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c +index 7fae365..ed91c7e 100644 +--- a/arch/arm/mach-at91/at91sam9263.c ++++ b/arch/arm/mach-at91/at91sam9263.c +@@ -199,6 +199,16 @@ static struct clk_lookup periph_clocks_lookups[] = { + CLKDEV_CON_ID("pioC", &pioCDE_clk), + CLKDEV_CON_ID("pioD", &pioCDE_clk), + CLKDEV_CON_ID("pioE", &pioCDE_clk), ++ /* more usart lookup table for DT entries */ ++ CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), ++ CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk), ++ CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk), ++ CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk), ++ /* more tc lookup table for DT entries */ ++ CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk), ++ CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk), ++ CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), ++ CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), + }; + + static struct clk_lookup usart_clocks_lookups[] = { +diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c +index dfe5bc0..175e000 100644 +--- a/arch/arm/mach-at91/at91sam9263_devices.c ++++ b/arch/arm/mach-at91/at91sam9263_devices.c +@@ -953,8 +953,25 @@ static struct platform_device at91sam9263_tcb_device = { + .num_resources = ARRAY_SIZE(tcb_resources), + }; + ++#if defined(CONFIG_OF) ++static struct of_device_id tcb_ids[] = { ++ { .compatible = "atmel,at91rm9200-tcb" }, ++ { /*sentinel*/ } ++}; ++#endif ++ + static void __init at91_add_device_tc(void) + { ++#if defined(CONFIG_OF) ++ struct device_node *np; ++ ++ np = of_find_matching_node(NULL, tcb_ids); ++ if (np) { ++ of_node_put(np); ++ return; ++ } ++#endif ++ + platform_device_register(&at91sam9263_tcb_device); + } + #else +@@ -1483,6 +1500,9 @@ void __init at91_add_device_serial(void) {} + */ + static int __init at91_add_standard_devices(void) + { ++ if (of_have_populated_dt()) ++ return 0; ++ + at91_add_device_rtt(); + at91_add_device_watchdog(); + at91_add_device_tc(); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0033-ARM-at91-add-at91sam9263ek-DT-support.patch b/patches.at91/0033-ARM-at91-add-at91sam9263ek-DT-support.patch new file mode 100644 index 000000000000..7b9c30e1b7b6 --- /dev/null +++ b/patches.at91/0033-ARM-at91-add-at91sam9263ek-DT-support.patch @@ -0,0 +1,191 @@ +From 57fab5b53e9cf05574fffd706373b62713eb616c Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun, 26 Feb 2012 19:12:43 +0800 +Subject: ARM: at91: add at91sam9263ek DT support + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/at91sam9263ek.dts | 156 ++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 2 + + 2 files changed, 158 insertions(+) + create mode 100644 arch/arm/boot/dts/at91sam9263ek.dts + +diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts +new file mode 100644 +index 0000000..f86ac4b +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9263ek.dts +@@ -0,0 +1,156 @@ ++/* ++ * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 only ++ */ ++/dts-v1/; ++/include/ "at91sam9263.dtsi" ++ ++/ { ++ model = "Atmel at91sam9263ek"; ++ compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x4000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <16367660>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@ffffee00 { ++ status = "okay"; ++ }; ++ ++ usart0: serial@fff8c000 { ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@fffbc000 { ++ phy-mode = "rmii"; ++ status = "okay"; ++ }; ++ ++ usb1: gadget@fff78000 { ++ atmel,vbus-gpio = <&pioA 25 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt = <1>; ++ status = "okay"; ++ ++ at91bootstrap@0 { ++ label = "at91bootstrap"; ++ reg = <0x0 0x20000>; ++ }; ++ ++ barebox@20000 { ++ label = "barebox"; ++ reg = <0x20000 0x40000>; ++ }; ++ ++ bareboxenv@60000 { ++ label = "bareboxenv"; ++ reg = <0x60000 0x20000>; ++ }; ++ ++ bareboxenv2@80000 { ++ label = "bareboxenv2"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ ++ kernel@a0000 { ++ label = "kernel"; ++ reg = <0xc0000 0x400000>; ++ }; ++ ++ rootfs@4a0000 { ++ label = "rootfs"; ++ reg = <0x4c0000 0x7800000>; ++ }; ++ ++ data@7ca0000 { ++ label = "data"; ++ reg = <0x7cc0000 0x8340000>; ++ }; ++ }; ++ ++ usb0: ohci@00a00000 { ++ num-ports = <2>; ++ status = "okay"; ++ atmel,vbus-gpio = <&pioA 24 0 ++ &pioA 21 0 ++ >; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ d3 { ++ label = "d3"; ++ gpios = <&pioB 7 0>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ d2 { ++ label = "d2"; ++ gpios = <&pioC 29 1>; ++ linux,default-trigger = "nand-disk"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ left_click { ++ label = "left_click"; ++ gpios = <&pioC 5 1>; ++ linux,code = <272>; ++ gpio-key,wakeup; ++ }; ++ ++ right_click { ++ label = "right_click"; ++ gpios = <&pioC 4 1>; ++ linux,code = <273>; ++ gpio-key,wakeup; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ ++ 24c512@50 { ++ compatible = "24c512"; ++ reg = <0x50>; ++ pagesize = <128>; ++ }; ++ }; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index b2ac536..0c6e0e9 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -17,6 +17,8 @@ endif + # sam9260 + dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb ++# sam9263 ++dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb + # sam9g20 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0034-ARM-at91-DT-add-Calao-USB-A9263-board-support.patch b/patches.at91/0034-ARM-at91-DT-add-Calao-USB-A9263-board-support.patch new file mode 100644 index 000000000000..5ad367b549f0 --- /dev/null +++ b/patches.at91/0034-ARM-at91-DT-add-Calao-USB-A9263-board-support.patch @@ -0,0 +1,165 @@ +From 6c84b391e098cad2350f661ebffd8b8d4f6b8981 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 12 Apr 2012 18:01:33 +0800 +Subject: ARM: at91: DT: add Calao USB A9263 board support + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/usb_a9263.dts | 131 +++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 1 + + 2 files changed, 132 insertions(+) + create mode 100644 arch/arm/boot/dts/usb_a9263.dts + +diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts +new file mode 100644 +index 0000000..6fe05cc +--- /dev/null ++++ b/arch/arm/boot/dts/usb_a9263.dts +@@ -0,0 +1,131 @@ ++/* ++ * usb_a9263.dts - Device Tree file for Caloa USB A9293 board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 only ++ */ ++/dts-v1/; ++/include/ "at91sam9263.dtsi" ++ ++/ { ++ model = "Calao USB A9263"; ++ compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x4000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <12000000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@ffffee00 { ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@fffbc000 { ++ phy-mode = "rmii"; ++ status = "okay"; ++ }; ++ ++ usb1: gadget@fff78000 { ++ atmel,vbus-gpio = <&pioB 11 0>; ++ status = "okay"; ++ }; ++ ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ ++ at91bootstrap@0 { ++ label = "at91bootstrap"; ++ reg = <0x0 0x20000>; ++ }; ++ ++ barebox@20000 { ++ label = "barebox"; ++ reg = <0x20000 0x40000>; ++ }; ++ ++ bareboxenv@60000 { ++ label = "bareboxenv"; ++ reg = <0x60000 0x20000>; ++ }; ++ ++ bareboxenv2@80000 { ++ label = "bareboxenv2"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ ++ kernel@a0000 { ++ label = "kernel"; ++ reg = <0xc0000 0x400000>; ++ }; ++ ++ rootfs@4a0000 { ++ label = "rootfs"; ++ reg = <0x4c0000 0x7800000>; ++ }; ++ ++ data@7ca0000 { ++ label = "data"; ++ reg = <0x7cc0000 0x8340000>; ++ }; ++ }; ++ ++ usb0: ohci@00a00000 { ++ num-ports = <2>; ++ status = "okay"; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ user_led { ++ label = "user_led"; ++ gpios = <&pioB 21 0>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ user_pb { ++ label = "user_pb"; ++ gpios = <&pioB 10 1>; ++ linux,code = <28>; ++ gpio-key,wakeup; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ }; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 0c6e0e9..7f0a5cb 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -19,6 +19,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb + # sam9263 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb ++dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb + # sam9g20 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0035-ARM-at91-DT-add-Calao-TNY-A9263-board-support.patch b/patches.at91/0035-ARM-at91-DT-add-Calao-TNY-A9263-board-support.patch new file mode 100644 index 000000000000..1cdfb9cc6dc5 --- /dev/null +++ b/patches.at91/0035-ARM-at91-DT-add-Calao-TNY-A9263-board-support.patch @@ -0,0 +1,131 @@ +From 242797da12e5e34231572f9d5472ab2f80bbc301 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 12 Apr 2012 18:47:32 +0800 +Subject: ARM: at91: DT: add Calao TNY A9263 board support + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Acked-by: Nicolas Ferre +--- + arch/arm/boot/dts/tny_a9263.dts | 97 ++++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 1 + + 2 files changed, 98 insertions(+) + create mode 100644 arch/arm/boot/dts/tny_a9263.dts + +diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts +new file mode 100644 +index 0000000..dee9c57 +--- /dev/null ++++ b/arch/arm/boot/dts/tny_a9263.dts +@@ -0,0 +1,97 @@ ++/* ++ * usb_a9263.dts - Device Tree file for Caloa USB A9293 board ++ * ++ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD ++ * ++ * Licensed under GPLv2 only ++ */ ++/dts-v1/; ++/include/ "at91sam9263.dtsi" ++ ++/ { ++ model = "Calao TNY A9263"; ++ compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x4000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <12000000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@ffffee00 { ++ status = "okay"; ++ }; ++ ++ usb1: gadget@fff78000 { ++ atmel,vbus-gpio = <&pioB 11 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ ++ at91bootstrap@0 { ++ label = "at91bootstrap"; ++ reg = <0x0 0x20000>; ++ }; ++ ++ barebox@20000 { ++ label = "barebox"; ++ reg = <0x20000 0x40000>; ++ }; ++ ++ bareboxenv@60000 { ++ label = "bareboxenv"; ++ reg = <0x60000 0x20000>; ++ }; ++ ++ bareboxenv2@80000 { ++ label = "bareboxenv2"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ oftree@80000 { ++ label = "oftree"; ++ reg = <0xa0000 0x20000>; ++ }; ++ ++ kernel@a0000 { ++ label = "kernel"; ++ reg = <0xc0000 0x400000>; ++ }; ++ ++ rootfs@4a0000 { ++ label = "rootfs"; ++ reg = <0x4c0000 0x7800000>; ++ }; ++ ++ data@7ca0000 { ++ label = "data"; ++ reg = <0x7cc0000 0x8340000>; ++ }; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ }; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 7f0a5cb..618fc5b 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -19,6 +19,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb + # sam9263 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb ++dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb + # sam9g20 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0036-ARM-at91-add-kizbox-board-dt-support.patch b/patches.at91/0036-ARM-at91-add-kizbox-board-dt-support.patch new file mode 100644 index 000000000000..c6646e562f12 --- /dev/null +++ b/patches.at91/0036-ARM-at91-add-kizbox-board-dt-support.patch @@ -0,0 +1,176 @@ +From 1dd636835a243a050417ff1c10f221ef545d5ab0 Mon Sep 17 00:00:00 2001 +From: Boris BREZILLON +Date: Fri, 20 Apr 2012 14:37:50 +0200 +Subject: ARM: at91: add kizbox board dt support. + +This patch adds support for the kizbox board (based on at91sam9g20 SoC) + +Signed-off-by: Boris BREZILLON +Acked-by: Arnd Bergmann +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +--- + arch/arm/boot/dts/kizbox.dts | 138 +++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 1 + + 2 files changed, 139 insertions(+) + create mode 100644 arch/arm/boot/dts/kizbox.dts + +diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts +new file mode 100644 +index 0000000..e8814fe +--- /dev/null ++++ b/arch/arm/boot/dts/kizbox.dts +@@ -0,0 +1,138 @@ ++/* ++ * kizbox.dts - Device Tree file for Overkiz Kizbox board ++ * ++ * Copyright (C) 2012 Boris BREZILLON ++ * ++ * Licensed under GPLv2. ++ */ ++/dts-v1/; ++/include/ "at91sam9g20.dtsi" ++ ++/ { ++ ++ model = "Overkiz kizbox"; ++ compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x2000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <18432000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@fffff200 { ++ status = "okay"; ++ }; ++ ++ usart0: serial@fffb0000 { ++ status = "okay"; ++ }; ++ ++ usart1: serial@fffb4000 { ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@fffc4000 { ++ phy-mode = "mii"; ++ status = "okay"; ++ }; ++ ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ status = "okay"; ++ ++ bootloaderkernel@0 { ++ label = "bootloader-kernel"; ++ reg = <0x0 0xc0000>; ++ }; ++ ++ ubi@c0000 { ++ label = "ubi"; ++ reg = <0xc0000 0x7f40000>; ++ }; ++ ++ }; ++ ++ usb0: ohci@00500000 { ++ num-ports = <1>; ++ status = "okay"; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ ++ pcf8563@51 { ++ /* nxp pcf8563 rtc */ ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ }; ++ ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led1g { ++ label = "led1:green"; ++ gpios = <&pioB 0 1>; ++ linux,default-trigger = "none"; ++ }; ++ ++ led1r { ++ label = "led1:red"; ++ gpios = <&pioB 1 1>; ++ linux,default-trigger = "none"; ++ }; ++ ++ led2g { ++ label = "led2:green"; ++ gpios = <&pioB 2 1>; ++ linux,default-trigger = "none"; ++ default-state = "on"; ++ }; ++ ++ led2r { ++ label = "led2:red"; ++ gpios = <&pioB 3 1>; ++ linux,default-trigger = "none"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ reset { ++ label = "reset"; ++ gpios = <&pioB 30 1>; ++ linux,code = <0x100>; ++ gpio-key,wakeup; ++ }; ++ ++ mode { ++ label = "mode"; ++ gpios = <&pioB 31 1>; ++ linux,code = <0x101>; ++ gpio-key,wakeup; ++ }; ++ }; ++}; +\ No newline at end of file +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 618fc5b..99e8097 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -24,6 +24,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb + # sam9g20 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb ++dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb + # sam9g45 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0037-Ethernut-5-board-support.patch b/patches.at91/0037-Ethernut-5-board-support.patch new file mode 100644 index 000000000000..a3b9b1084348 --- /dev/null +++ b/patches.at91/0037-Ethernut-5-board-support.patch @@ -0,0 +1,120 @@ +From 6d9ded2c6183d8098f852b2a5dcd18454f9de0e7 Mon Sep 17 00:00:00 2001 +From: Tim Schendekehl +Date: Tue, 24 Apr 2012 18:47:59 +0200 +Subject: Ethernut 5 board support + +Add support for the Ethernut 5 open hardware design, based +on Atmel's AT91SAM9XE512 SoC. + +Signed-off-by: Tim Schendekehl +--- + arch/arm/boot/dts/ethernut5.dts | 84 ++++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/Makefile.boot | 1 + + 2 files changed, 85 insertions(+) + create mode 100644 arch/arm/boot/dts/ethernut5.dts + +diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts +new file mode 100644 +index 0000000..1ea9d34 +--- /dev/null ++++ b/arch/arm/boot/dts/ethernut5.dts +@@ -0,0 +1,84 @@ ++/* ++ * ethernut5.dts - Device Tree file for Ethernut 5 board ++ * ++ * Copyright (C) 2012 egnite GmbH ++ * ++ * Licensed under GPLv2. ++ */ ++/dts-v1/; ++/include/ "at91sam9260.dtsi" ++ ++/ { ++ model = "Ethernut 5"; ++ compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@fffff200 { ++ status = "okay"; ++ }; ++ ++ usart0: serial@fffb0000 { ++ status = "okay"; ++ }; ++ ++ usart1: serial@fffb4000 { ++ status = "okay"; ++ }; ++ ++ macb0: ethernet@fffc4000 { ++ phy-mode = "rmii"; ++ status = "okay"; ++ }; ++ ++ usb1: gadget@fffa4000 { ++ atmel,vbus-gpio = <&pioC 5 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ ++ gpios = <0 ++ &pioC 14 0 ++ 0 ++ >; ++ ++ root@0 { ++ label = "root"; ++ reg = <0x0 0x08000000>; ++ }; ++ ++ data@20000 { ++ label = "data"; ++ reg = <0x08000000 0x38000000>; ++ }; ++ }; ++ ++ usb0: ohci@00500000 { ++ num-ports = <2>; ++ status = "okay"; ++ }; ++ }; ++ ++ i2c@0 { ++ status = "okay"; ++ ++ pcf8563@50 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ }; ++ }; ++}; +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index 99e8097..c03417d 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -15,6 +15,7 @@ endif + + # Keep dtb files sorted alphabetically for each SoC + # sam9260 ++dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb + # sam9263 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0038-ARM-at91-Add-machine-header-file-for-AT91SAM9N12-SoC.patch b/patches.at91/0038-ARM-at91-Add-machine-header-file-for-AT91SAM9N12-SoC.patch new file mode 100644 index 000000000000..dc6f319c3282 --- /dev/null +++ b/patches.at91/0038-ARM-at91-Add-machine-header-file-for-AT91SAM9N12-SoC.patch @@ -0,0 +1,213 @@ +From 771d02d8690db4118b239f864edca3d80d1c163f Mon Sep 17 00:00:00 2001 +From: Hong Xu +Date: Tue, 17 Apr 2012 14:26:30 +0800 +Subject: ARM: at91: Add machine header file for AT91SAM9N12 SoC + +Signed-off-by: Hong Xu +Signed-off-by: Nicolas Ferre +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +--- + arch/arm/mach-at91/include/mach/at91sam9n12.h | 60 ++++++++++++++++++++++ + .../mach-at91/include/mach/at91sam9n12_matrix.h | 53 +++++++++++++++++++ + arch/arm/mach-at91/include/mach/cpu.h | 10 ++++ + arch/arm/mach-at91/include/mach/hardware.h | 1 + + arch/arm/mach-at91/soc.h | 5 ++ + 5 files changed, 129 insertions(+) + create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12.h + create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h + +diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h +new file mode 100644 +index 0000000..d374b87 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h +@@ -0,0 +1,60 @@ ++/* ++ * SoC specific header file for the AT91SAM9N12 ++ * ++ * Copyright (C) 2012 Atmel Corporation ++ * ++ * Common definitions, based on AT91SAM9N12 SoC datasheet ++ * ++ * Licensed under GPLv2 or later ++ */ ++ ++#ifndef _AT91SAM9N12_H_ ++#define _AT91SAM9N12_H_ ++ ++/* ++ * Peripheral identifiers/interrupts. ++ */ ++#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ ++#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ ++#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */ ++#define AT91SAM9N12_ID_USART0 5 /* USART 0 */ ++#define AT91SAM9N12_ID_USART1 6 /* USART 1 */ ++#define AT91SAM9N12_ID_USART2 7 /* USART 2 */ ++#define AT91SAM9N12_ID_USART3 8 /* USART 3 */ ++#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */ ++#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */ ++#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */ ++#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */ ++#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */ ++#define AT91SAM9N12_ID_UART0 15 /* UART 0 */ ++#define AT91SAM9N12_ID_UART1 16 /* UART 1 */ ++#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ ++#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */ ++#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */ ++#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */ ++#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */ ++#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */ ++#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */ ++#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */ ++#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */ ++#define AT91SAM9N12_ID_TRNG 30 /* TRNG */ ++#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */ ++ ++/* ++ * User Peripheral physical base addresses. ++ */ ++#define AT91SAM9N12_BASE_USART0 0xf801c000 ++#define AT91SAM9N12_BASE_USART1 0xf8020000 ++#define AT91SAM9N12_BASE_USART2 0xf8024000 ++#define AT91SAM9N12_BASE_USART3 0xf8028000 ++ ++/* ++ * Internal Memory. ++ */ ++#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ ++#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ ++ ++#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */ ++#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h +new file mode 100644 +index 0000000..40060cd +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h +@@ -0,0 +1,53 @@ ++/* ++ * Matrix-centric header file for the AT91SAM9N12 ++ * ++ * Copyright (C) 2012 Atmel Corporation. ++ * ++ * Only EBI related registers. ++ * Write Protect register definitions may be useful. ++ * ++ * Licensed under GPLv2 or later. ++ */ ++ ++#ifndef _AT91SAM9N12_MATRIX_H_ ++#define _AT91SAM9N12_MATRIX_H_ ++ ++#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */ ++#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ ++#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) ++#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) ++#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ ++#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) ++#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) ++#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ ++#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) ++#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) ++#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ ++#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) ++#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) ++#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ ++#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) ++#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) ++#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ ++#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) ++#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) ++#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ ++#define AT91_MATRIX_NFD0_ON_D0 (0 << 24) ++#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) ++#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ ++#define AT91_MATRIX_MP_OFF (0 << 25) ++#define AT91_MATRIX_MP_ON (1 << 25) ++ ++#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ ++#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ ++#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) ++#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) ++#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ ++ ++#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ ++#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ ++#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) ++#define AT91_MATRIX_WPSR_WPV (1 << 0) ++#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h +index 73d2fd2..b6504c1 100644 +--- a/arch/arm/mach-at91/include/mach/cpu.h ++++ b/arch/arm/mach-at91/include/mach/cpu.h +@@ -25,6 +25,7 @@ + #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ + #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ + #define ARCH_ID_AT91SAM9X5 0x819a05a0 ++#define ARCH_ID_AT91SAM9N12 0x819a07a0 + + #define ARCH_ID_AT91SAM9XE128 0x329973a0 + #define ARCH_ID_AT91SAM9XE256 0x329a93a0 +@@ -71,6 +72,9 @@ enum at91_soc_type { + /* SAM9X5 */ + AT91_SOC_SAM9X5, + ++ /* SAM9N12 */ ++ AT91_SOC_SAM9N12, ++ + /* Unknown type */ + AT91_SOC_NONE + }; +@@ -177,6 +181,12 @@ static inline int at91_soc_is_detected(void) + #define cpu_is_at91sam9x25() (0) + #endif + ++#ifdef CONFIG_SOC_AT91SAM9N12 ++#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12) ++#else ++#define cpu_is_at91sam9n12() (0) ++#endif ++ + /* + * Since this is ARM, we will never run on any AVR32 CPU. But these + * definitions may reduce clutter in common drivers. +diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h +index 3a01f8f..24b46bd 100644 +--- a/arch/arm/mach-at91/include/mach/hardware.h ++++ b/arch/arm/mach-at91/include/mach/hardware.h +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + /* + * On all at91 except rm9200 and x40 have the System Controller starts +diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h +index 683dddf..a9cfeb1 100644 +--- a/arch/arm/mach-at91/soc.h ++++ b/arch/arm/mach-at91/soc.h +@@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc; + extern struct at91_init_soc at91sam9g45_soc; + extern struct at91_init_soc at91sam9rl_soc; + extern struct at91_init_soc at91sam9x5_soc; ++extern struct at91_init_soc at91sam9n12_soc; + + static inline int at91_soc_is_enabled(void) + { +@@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void) + #if !defined(CONFIG_SOC_AT91SAM9X5) + #define at91sam9x5_soc at91_boot_soc + #endif ++ ++#if !defined(CONFIG_SOC_AT91SAM9N12) ++#define at91sam9n12_soc at91_boot_soc ++#endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0039-ARM-at91-Add-machine-files-for-AT91SAM9N12-SoC.patch b/patches.at91/0039-ARM-at91-Add-machine-files-for-AT91SAM9N12-SoC.patch new file mode 100644 index 000000000000..c5a453488e8e --- /dev/null +++ b/patches.at91/0039-ARM-at91-Add-machine-files-for-AT91SAM9N12-SoC.patch @@ -0,0 +1,368 @@ +From 37b8c7ad2aa24a15b778cff614913c63b7e5c505 Mon Sep 17 00:00:00 2001 +From: Hong Xu +Date: Tue, 17 Apr 2012 14:26:31 +0800 +Subject: ARM: at91: Add machine files for AT91SAM9N12 SoC + +Signed-off-by: Hong Xu +Signed-off-by: Nicolas Ferre +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +--- + arch/arm/mach-at91/Kconfig | 8 ++ + arch/arm/mach-at91/Makefile | 1 + + arch/arm/mach-at91/Makefile.boot | 2 + + arch/arm/mach-at91/at91sam9n12.c | 233 +++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-at91/clock.c | 15 ++- + arch/arm/mach-at91/setup.c | 6 + + 6 files changed, 260 insertions(+), 5 deletions(-) + create mode 100644 arch/arm/mach-at91/at91sam9n12.c + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 98a42f3..19505c0 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -91,6 +91,14 @@ config SOC_AT91SAM9X5 + This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 + and AT91SAM9X35. + ++config SOC_AT91SAM9N12 ++ bool "AT91SAM9N12 family" ++ select SOC_AT91SAM9 ++ select HAVE_AT91_DBGU0 ++ select HAVE_FB_ATMEL ++ help ++ Select this if you are using Atmel's AT91SAM9N12 SoC. ++ + choice + prompt "Atmel AT91 Processor Devices for non DT boards" + +diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile +index 79d0f60..3bb7a51 100644 +--- a/arch/arm/mach-at91/Makefile ++++ b/arch/arm/mach-at91/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o + obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o + obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o + obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o ++obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o + obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o + obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o + +diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot +index c03417d..9e84fe4 100644 +--- a/arch/arm/mach-at91/Makefile.boot ++++ b/arch/arm/mach-at91/Makefile.boot +@@ -30,5 +30,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb + dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb + # sam9g45 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb ++# sam9n12 ++dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb + # sam9x5 + dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb +diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c +new file mode 100644 +index 0000000..0849466 +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9n12.c +@@ -0,0 +1,233 @@ ++/* ++ * SoC specific setup code for the AT91SAM9N12 ++ * ++ * Copyright (C) 2012 Atmel Corporation. ++ * ++ * Licensed under GPLv2 or later. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "soc.h" ++#include "generic.h" ++#include "clock.h" ++#include "sam9_smc.h" ++ ++/* -------------------------------------------------------------------- ++ * Clocks ++ * -------------------------------------------------------------------- */ ++ ++/* ++ * The peripheral clocks. ++ */ ++static struct clk pioAB_clk = { ++ .name = "pioAB_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioCD_clk = { ++ .name = "pioCD_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart0_clk = { ++ .name = "usart0_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_USART0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart1_clk = { ++ .name = "usart1_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_USART1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart2_clk = { ++ .name = "usart2_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_USART2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart3_clk = { ++ .name = "usart3_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_USART3, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi0_clk = { ++ .name = "twi0_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_TWI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi1_clk = { ++ .name = "twi1_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_TWI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk mmc_clk = { ++ .name = "mci_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_MCI, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi0_clk = { ++ .name = "spi0_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_SPI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi1_clk = { ++ .name = "spi1_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_SPI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uart0_clk = { ++ .name = "uart0_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_UART0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uart1_clk = { ++ .name = "uart1_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_UART1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tcb_clk = { ++ .name = "tcb_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_TCB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pwm_clk = { ++ .name = "pwm_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_PWM, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk adc_clk = { ++ .name = "adc_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_ADC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk dma_clk = { ++ .name = "dma_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_DMA, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uhp_clk = { ++ .name = "uhp", ++ .pmc_mask = 1 << AT91SAM9N12_ID_UHP, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk udp_clk = { ++ .name = "udp_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_UDP, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk lcdc_clk = { ++ .name = "lcdc_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_LCDC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc_clk = { ++ .name = "ssc_clk", ++ .pmc_mask = 1 << AT91SAM9N12_ID_SSC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++ ++static struct clk *periph_clocks[] __initdata = { ++ &pioAB_clk, ++ &pioCD_clk, ++ &usart0_clk, ++ &usart1_clk, ++ &usart2_clk, ++ &usart3_clk, ++ &twi0_clk, ++ &twi1_clk, ++ &mmc_clk, ++ &spi0_clk, ++ &spi1_clk, ++ &lcdc_clk, ++ &uart0_clk, ++ &uart1_clk, ++ &tcb_clk, ++ &pwm_clk, ++ &adc_clk, ++ &dma_clk, ++ &uhp_clk, ++ &udp_clk, ++ &ssc_clk, ++}; ++ ++static struct clk_lookup periph_clocks_lookups[] = { ++ /* lookup table for DT entries */ ++ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), ++ CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk), ++ CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk), ++ CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk), ++ CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk), ++ CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk), ++ CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk), ++ CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), ++ CLKDEV_CON_ID("pioA", &pioAB_clk), ++ CLKDEV_CON_ID("pioB", &pioAB_clk), ++ CLKDEV_CON_ID("pioC", &pioCD_clk), ++ CLKDEV_CON_ID("pioD", &pioCD_clk), ++ /* additional fake clock for macb_hclk */ ++ CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk), ++ CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk), ++}; ++ ++/* ++ * The two programmable clocks. ++ * You must configure pin multiplexing to bring these signals out. ++ */ ++static struct clk pck0 = { ++ .name = "pck0", ++ .pmc_mask = AT91_PMC_PCK0, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 0, ++}; ++static struct clk pck1 = { ++ .name = "pck1", ++ .pmc_mask = AT91_PMC_PCK1, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 1, ++}; ++ ++static void __init at91sam9n12_register_clocks(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) ++ clk_register(periph_clocks[i]); ++ clk_register(&pck0); ++ clk_register(&pck1); ++ ++ clkdev_add_table(periph_clocks_lookups, ++ ARRAY_SIZE(periph_clocks_lookups)); ++ ++} ++ ++/* -------------------------------------------------------------------- ++ * AT91SAM9N12 processor initialization ++ * -------------------------------------------------------------------- */ ++ ++static void __init at91sam9n12_map_io(void) ++{ ++ at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); ++} ++ ++void __init at91sam9n12_initialize(void) ++{ ++ at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); ++ ++ /* Register GPIO subsystem (using DT) */ ++ at91_gpio_init(NULL, 0); ++} ++ ++struct at91_init_soc __initdata at91sam9n12_soc = { ++ .map_io = at91sam9n12_map_io, ++ .register_clocks = at91sam9n12_register_clocks, ++ .init = at91sam9n12_initialize, ++}; +diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c +index 6b69282..de2ec6b 100644 +--- a/arch/arm/mach-at91/clock.c ++++ b/arch/arm/mach-at91/clock.c +@@ -58,13 +58,15 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); + + #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ + || cpu_is_at91sam9g45() \ +- || cpu_is_at91sam9x5()) ++ || cpu_is_at91sam9x5() \ ++ || cpu_is_at91sam9n12()) + + #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) + + #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ + || cpu_is_at91sam9g45() \ +- || cpu_is_at91sam9x5())) ++ || cpu_is_at91sam9x5() \ ++ || cpu_is_at91sam9n12())) + + #define cpu_has_upll() (cpu_is_at91sam9g45() \ + || cpu_is_at91sam9x5()) +@@ -78,12 +80,15 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); + || cpu_is_at91sam9x5())) + + #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ +- || cpu_is_at91sam9x5()) ++ || cpu_is_at91sam9x5() \ ++ || cpu_is_at91sam9n12()) + + #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ +- || cpu_is_at91sam9x5()) ++ || cpu_is_at91sam9x5() \ ++ || cpu_is_at91sam9n12()) + +-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5()) ++#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ ++ || cpu_is_at91sam9n12()) + + static LIST_HEAD(clocks); + static DEFINE_SPINLOCK(clk_lock); +diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c +index f44a2e7..944bffb 100644 +--- a/arch/arm/mach-at91/setup.c ++++ b/arch/arm/mach-at91/setup.c +@@ -143,6 +143,11 @@ static void __init soc_detect(u32 dbgu_base) + at91_soc_initdata.type = AT91_SOC_SAM9X5; + at91_boot_soc = at91sam9x5_soc; + break; ++ ++ case ARCH_ID_AT91SAM9N12: ++ at91_soc_initdata.type = AT91_SOC_SAM9N12; ++ at91_boot_soc = at91sam9n12_soc; ++ break; + } + + /* at91sam9g10 */ +@@ -210,6 +215,7 @@ static const char *soc_name[] = { + [AT91_SOC_SAM9G45] = "at91sam9g45", + [AT91_SOC_SAM9RL] = "at91sam9rl", + [AT91_SOC_SAM9X5] = "at91sam9x5", ++ [AT91_SOC_SAM9N12] = "at91sam9n12", + [AT91_SOC_NONE] = "Unknown" + }; + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0040-ARM-at91-Add-DT-description-files-for-AT91SAM9N12-EK.patch b/patches.at91/0040-ARM-at91-Add-DT-description-files-for-AT91SAM9N12-EK.patch new file mode 100644 index 000000000000..b84646a52eb9 --- /dev/null +++ b/patches.at91/0040-ARM-at91-Add-DT-description-files-for-AT91SAM9N12-EK.patch @@ -0,0 +1,338 @@ +From 2fc9a0d7df19f33a08242efb22d64e8d3d0280de Mon Sep 17 00:00:00 2001 +From: Hong Xu +Date: Tue, 17 Apr 2012 14:26:29 +0800 +Subject: ARM: at91: Add DT description files for AT91SAM9N12-EK + +Added AT91SAM9N12 SoC DT file, as well as the board definition +.dts file for AT91SAM9N12-EK. + +Signed-off-by: Hong Xu +Signed-off-by: Nicolas Ferre +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +--- + arch/arm/boot/dts/at91sam9n12.dtsi | 221 ++++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/at91sam9n12ek.dts | 84 ++++++++++++++ + 2 files changed, 305 insertions(+) + create mode 100644 arch/arm/boot/dts/at91sam9n12.dtsi + create mode 100644 arch/arm/boot/dts/at91sam9n12ek.dts + +diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi +new file mode 100644 +index 0000000..cb84de7 +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9n12.dtsi +@@ -0,0 +1,221 @@ ++/* ++ * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC ++ * ++ * Copyright (C) 2012 Atmel, ++ * 2012 Hong Xu ++ * ++ * Licensed under GPLv2 or later. ++ */ ++ ++/include/ "skeleton.dtsi" ++ ++/ { ++ model = "Atmel AT91SAM9N12 SoC"; ++ compatible = "atmel,at91sam9n12"; ++ interrupt-parent = <&aic>; ++ ++ aliases { ++ serial0 = &dbgu; ++ serial1 = &usart0; ++ serial2 = &usart1; ++ serial3 = &usart2; ++ serial4 = &usart3; ++ gpio0 = &pioA; ++ gpio1 = &pioB; ++ gpio2 = &pioC; ++ gpio3 = &pioD; ++ tcb0 = &tcb0; ++ tcb1 = &tcb1; ++ }; ++ cpus { ++ cpu@0 { ++ compatible = "arm,arm926ejs"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++ ahb { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ apb { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ aic: interrupt-controller@fffff000 { ++ #interrupt-cells = <2>; ++ compatible = "atmel,at91rm9200-aic"; ++ interrupt-controller; ++ reg = <0xfffff000 0x200>; ++ }; ++ ++ ramc0: ramc@ffffe800 { ++ compatible = "atmel,at91sam9g45-ddramc"; ++ reg = <0xffffe800 0x200>; ++ }; ++ ++ pmc: pmc@fffffc00 { ++ compatible = "atmel,at91rm9200-pmc"; ++ reg = <0xfffffc00 0x100>; ++ }; ++ ++ rstc@fffffe00 { ++ compatible = "atmel,at91sam9g45-rstc"; ++ reg = <0xfffffe00 0x10>; ++ }; ++ ++ pit: timer@fffffe30 { ++ compatible = "atmel,at91sam9260-pit"; ++ reg = <0xfffffe30 0xf>; ++ interrupts = <1 4>; ++ }; ++ ++ shdwc@fffffe10 { ++ compatible = "atmel,at91sam9x5-shdwc"; ++ reg = <0xfffffe10 0x10>; ++ }; ++ ++ tcb0: timer@f8008000 { ++ compatible = "atmel,at91sam9x5-tcb"; ++ reg = <0xf8008000 0x100>; ++ interrupts = <17 4>; ++ }; ++ ++ tcb1: timer@f800c000 { ++ compatible = "atmel,at91sam9x5-tcb"; ++ reg = <0xf800c000 0x100>; ++ interrupts = <17 4>; ++ }; ++ ++ dma: dma-controller@ffffec00 { ++ compatible = "atmel,at91sam9g45-dma"; ++ reg = <0xffffec00 0x200>; ++ interrupts = <20 4>; ++ }; ++ ++ pioA: gpio@fffff400 { ++ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; ++ reg = <0xfffff400 0x100>; ++ interrupts = <2 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioB: gpio@fffff600 { ++ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; ++ reg = <0xfffff600 0x100>; ++ interrupts = <2 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioC: gpio@fffff800 { ++ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; ++ reg = <0xfffff800 0x100>; ++ interrupts = <3 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ pioD: gpio@fffffa00 { ++ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; ++ reg = <0xfffffa00 0x100>; ++ interrupts = <3 4>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ interrupt-controller; ++ }; ++ ++ dbgu: serial@fffff200 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xfffff200 0x200>; ++ interrupts = <1 4>; ++ status = "disabled"; ++ }; ++ ++ usart0: serial@f801c000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xf801c000 0x4000>; ++ interrupts = <5 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart1: serial@f8020000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xf8020000 0x4000>; ++ interrupts = <6 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart2: serial@f8024000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xf8024000 0x4000>; ++ interrupts = <7 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ ++ usart3: serial@f8028000 { ++ compatible = "atmel,at91sam9260-usart"; ++ reg = <0xf8028000 0x4000>; ++ interrupts = <8 4>; ++ atmel,use-dma-rx; ++ atmel,use-dma-tx; ++ status = "disabled"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ compatible = "atmel,at91rm9200-nand"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = < 0x40000000 0x10000000 ++ 0xffffe000 0x00000600 ++ 0xffffe600 0x00000200 ++ 0x00100000 0x00100000 ++ >; ++ atmel,nand-addr-offset = <21>; ++ atmel,nand-cmd-offset = <22>; ++ gpios = <&pioD 5 0 ++ &pioD 4 0 ++ 0 ++ >; ++ status = "disabled"; ++ }; ++ ++ usb0: ohci@00500000 { ++ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; ++ reg = <0x00500000 0x00100000>; ++ interrupts = <22 4>; ++ status = "disabled"; ++ }; ++ }; ++ ++ i2c@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&pioA 30 0 /* sda */ ++ &pioA 31 0 /* scl */ ++ >; ++ i2c-gpio,sda-open-drain; ++ i2c-gpio,scl-open-drain; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts +new file mode 100644 +index 0000000..f4e43e3 +--- /dev/null ++++ b/arch/arm/boot/dts/at91sam9n12ek.dts +@@ -0,0 +1,84 @@ ++/* ++ * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board ++ * ++ * Copyright (C) 2012 Atmel, ++ * 2012 Hong Xu ++ * ++ * Licensed under GPLv2 or later. ++ */ ++/dts-v1/; ++/include/ "at91sam9n12.dtsi" ++ ++/ { ++ model = "Atmel AT91SAM9N12-EK"; ++ compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; ++ ++ chosen { ++ bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ main_clock: clock@0 { ++ compatible = "atmel,osc", "fixed-clock"; ++ clock-frequency = <16000000>; ++ }; ++ }; ++ ++ ahb { ++ apb { ++ dbgu: serial@fffff200 { ++ status = "okay"; ++ }; ++ }; ++ ++ nand0: nand@40000000 { ++ nand-bus-width = <8>; ++ nand-ecc-mode = "soft"; ++ nand-on-flash-bbt; ++ status = "okay"; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ d8 { ++ label = "d8"; ++ gpios = <&pioB 4 1>; ++ linux,default-trigger = "mmc0"; ++ }; ++ ++ d9 { ++ label = "d6"; ++ gpios = <&pioB 5 1>; ++ linux,default-trigger = "nand-disk"; ++ }; ++ ++ d10 { ++ label = "d7"; ++ gpios = <&pioB 6 0>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ enter { ++ label = "Enter"; ++ gpios = <&pioB 4 1>; ++ linux,code = <28>; ++ gpio-key,wakeup; ++ }; ++ }; ++}; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0041-ARM-at91-remove-two-unused-headers.patch b/patches.at91/0041-ARM-at91-remove-two-unused-headers.patch new file mode 100644 index 000000000000..a118d5ff83b6 --- /dev/null +++ b/patches.at91/0041-ARM-at91-remove-two-unused-headers.patch @@ -0,0 +1,228 @@ +From 2d672820ba5d6f2b3be8f73decfc00d4994af6ba Mon Sep 17 00:00:00 2001 +From: Paul Bolle +Date: Thu, 7 Jun 2012 12:18:46 +0200 +Subject: ARM: at91: remove two unused headers + +Commit 82c583e3ae31ffa76d1280197274cc1e1cde3179 ("AT91RM9200 hardware +headers") introduced arch/arm/mach-at91/include/mach/at91_spi.h and +arch/arm/mach-at91/include/mach/at91_ssc.h. (These files were called +at91rm9200_spi.h and at91rm9200_ssc.h then.) That commit was added in +the v2.6.18 development cycle. + +Nothing includes them now and nothing uses the named constants they +provide. (There's no way these named constants could be used unless +these files were included somehow.) It actually seems these two headers +have never been used since they were added to the tree. They can safely +be removed. + +Signed-off-by: Paul Bolle +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/include/mach/at91_spi.h | 81 ---------------------- + arch/arm/mach-at91/include/mach/at91_ssc.h | 106 ----------------------------- + 2 files changed, 187 deletions(-) + delete mode 100644 arch/arm/mach-at91/include/mach/at91_spi.h + delete mode 100644 arch/arm/mach-at91/include/mach/at91_ssc.h + +diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h +deleted file mode 100644 +index 2f6ba0c..0000000 +--- a/arch/arm/mach-at91/include/mach/at91_spi.h ++++ /dev/null +@@ -1,81 +0,0 @@ +-/* +- * arch/arm/mach-at91/include/mach/at91_spi.h +- * +- * Copyright (C) 2005 Ivan Kokshaysky +- * Copyright (C) SAN People +- * +- * Serial Peripheral Interface (SPI) registers. +- * Based on AT91RM9200 datasheet revision E. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- */ +- +-#ifndef AT91_SPI_H +-#define AT91_SPI_H +- +-#define AT91_SPI_CR 0x00 /* Control Register */ +-#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ +-#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ +-#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ +-#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ +- +-#define AT91_SPI_MR 0x04 /* Mode Register */ +-#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ +-#define AT91_SPI_PS (1 << 1) /* Peripheral Select */ +-#define AT91_SPI_PS_FIXED (0 << 1) +-#define AT91_SPI_PS_VARIABLE (1 << 1) +-#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ +-#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ +-#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ +-#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ +-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ +-#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ +- +-#define AT91_SPI_RDR 0x08 /* Receive Data Register */ +-#define AT91_SPI_RD (0xffff << 0) /* Receive Data */ +-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ +- +-#define AT91_SPI_TDR 0x0c /* Transmit Data Register */ +-#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ +-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ +-#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ +- +-#define AT91_SPI_SR 0x10 /* Status Register */ +-#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ +-#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ +-#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ +-#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ +-#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ +-#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ +-#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ +-#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ +-#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ +-#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ +-#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ +- +-#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ +-#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ +-#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ +- +-#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ +-#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ +-#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ +-#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ +-#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ +-#define AT91_SPI_BITS_8 (0 << 4) +-#define AT91_SPI_BITS_9 (1 << 4) +-#define AT91_SPI_BITS_10 (2 << 4) +-#define AT91_SPI_BITS_11 (3 << 4) +-#define AT91_SPI_BITS_12 (4 << 4) +-#define AT91_SPI_BITS_13 (5 << 4) +-#define AT91_SPI_BITS_14 (6 << 4) +-#define AT91_SPI_BITS_15 (7 << 4) +-#define AT91_SPI_BITS_16 (8 << 4) +-#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ +-#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ +-#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ +- +-#endif +diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h +deleted file mode 100644 +index a81114c..0000000 +--- a/arch/arm/mach-at91/include/mach/at91_ssc.h ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* +- * arch/arm/mach-at91/include/mach/at91_ssc.h +- * +- * Copyright (C) SAN People +- * +- * Serial Synchronous Controller (SSC) registers. +- * Based on AT91RM9200 datasheet revision E. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- */ +- +-#ifndef AT91_SSC_H +-#define AT91_SSC_H +- +-#define AT91_SSC_CR 0x00 /* Control Register */ +-#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ +-#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ +-#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ +-#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ +-#define AT91_SSC_SWRST (1 << 15) /* Software Reset */ +- +-#define AT91_SSC_CMR 0x04 /* Clock Mode Register */ +-#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ +- +-#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ +-#define AT91_SSC_CKS (3 << 0) /* Clock Selection */ +-#define AT91_SSC_CKS_DIV (0 << 0) +-#define AT91_SSC_CKS_CLOCK (1 << 0) +-#define AT91_SSC_CKS_PIN (2 << 0) +-#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ +-#define AT91_SSC_CKO_NONE (0 << 2) +-#define AT91_SSC_CKO_CONTINUOUS (1 << 2) +-#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ +-#define AT91_SSC_CKI_FALLING (0 << 5) +-#define AT91_SSC_CK_RISING (1 << 5) +-#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ +-#define AT91_SSC_CKG_NONE (0 << 6) +-#define AT91_SSC_CKG_RFLOW (1 << 6) +-#define AT91_SSC_CKG_RFHIGH (2 << 6) +-#define AT91_SSC_START (0xf << 8) /* Start Selection */ +-#define AT91_SSC_START_CONTINUOUS (0 << 8) +-#define AT91_SSC_START_TX_RX (1 << 8) +-#define AT91_SSC_START_LOW_RF (2 << 8) +-#define AT91_SSC_START_HIGH_RF (3 << 8) +-#define AT91_SSC_START_FALLING_RF (4 << 8) +-#define AT91_SSC_START_RISING_RF (5 << 8) +-#define AT91_SSC_START_LEVEL_RF (6 << 8) +-#define AT91_SSC_START_EDGE_RF (7 << 8) +-#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ +-#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ +-#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ +- +-#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ +-#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ +-#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ +-#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ +-#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ +-#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ +-#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ +-#define AT91_SSC_FSOS_NONE (0 << 20) +-#define AT91_SSC_FSOS_NEGATIVE (1 << 20) +-#define AT91_SSC_FSOS_POSITIVE (2 << 20) +-#define AT91_SSC_FSOS_LOW (3 << 20) +-#define AT91_SSC_FSOS_HIGH (4 << 20) +-#define AT91_SSC_FSOS_TOGGLE (5 << 20) +-#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ +-#define AT91_SSC_FSEDGE_POSITIVE (0 << 24) +-#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) +- +-#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ +-#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ +-#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ +-#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ +- +-#define AT91_SSC_RHR 0x20 /* Receive Holding Register */ +-#define AT91_SSC_THR 0x24 /* Transmit Holding Register */ +-#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ +-#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ +- +-#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ +-#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ +- +-#define AT91_SSC_SR 0x40 /* Status Register */ +-#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ +-#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ +-#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ +-#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ +-#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ +-#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ +-#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ +-#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ +-#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ +-#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ +-#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ +-#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ +-#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ +-#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ +- +-#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ +-#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ +-#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ +- +-#endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0042-ARM-at91-fix-at91_aic_write-macro.patch b/patches.at91/0042-ARM-at91-fix-at91_aic_write-macro.patch new file mode 100644 index 000000000000..c5cb945c019f --- /dev/null +++ b/patches.at91/0042-ARM-at91-fix-at91_aic_write-macro.patch @@ -0,0 +1,29 @@ +From f7a7be1650e7160181c9ab1c4aeb5dd8b67ac939 Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Thu, 31 May 2012 17:26:05 +0200 +Subject: ARM: at91: fix at91_aic_write macro + +Fix at91_aic_write macro to avoid potential issues. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/include/mach/at91_aic.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h +index 3045781..c1413ed 100644 +--- a/arch/arm/mach-at91/include/mach/at91_aic.h ++++ b/arch/arm/mach-at91/include/mach/at91_aic.h +@@ -23,7 +23,7 @@ extern void __iomem *at91_aic_base; + __raw_readl(at91_aic_base + field) + + #define at91_aic_write(field, value) \ +- __raw_writel(value, at91_aic_base + field); ++ __raw_writel(value, at91_aic_base + field) + #else + .extern at91_aic_base + #endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0043-USB-ohci-at91-use-resource_size-for-memory-io-resour.patch b/patches.at91/0043-USB-ohci-at91-use-resource_size-for-memory-io-resour.patch new file mode 100644 index 000000000000..2f65c9fa7651 --- /dev/null +++ b/patches.at91/0043-USB-ohci-at91-use-resource_size-for-memory-io-resour.patch @@ -0,0 +1,27 @@ +From 6b36e56532a5b9d9f2311165a95f2a0d31c40464 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Wed, 9 May 2012 10:49:41 +0200 +Subject: USB: ohci-at91: use resource_size() for memory/io resource length + +Signed-off-by: Nicolas Ferre +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/ohci-at91.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c +index 55d3d64..84901c3 100644 +--- a/drivers/usb/host/ohci-at91.c ++++ b/drivers/usb/host/ohci-at91.c +@@ -129,7 +129,7 @@ static int __devinit usb_hcd_at91_probe(const struct hc_driver *driver, + if (!hcd) + return -ENOMEM; + hcd->rsrc_start = pdev->resource[0].start; +- hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; ++ hcd->rsrc_len = resource_size(&pdev->resource[0]); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed\n"); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0044-USB-Kconfig-add-Atmel-usba-driver-entry.patch b/patches.at91/0044-USB-Kconfig-add-Atmel-usba-driver-entry.patch new file mode 100644 index 000000000000..782778b7ce0d --- /dev/null +++ b/patches.at91/0044-USB-Kconfig-add-Atmel-usba-driver-entry.patch @@ -0,0 +1,29 @@ +From 4a0e29935e53da412664f85d25d46ba719ec2294 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 19 Jun 2012 13:14:10 +0200 +Subject: USB: Kconfig: add Atmel usba driver entry + +Allow the USBA entry to be selected for every AT91 SoC. +Will allow to select driver for newer SoCs. + +Signed-off-by: Nicolas Ferre +--- + drivers/usb/gadget/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig +index 2633f75..10fea8b 100644 +--- a/drivers/usb/gadget/Kconfig ++++ b/drivers/usb/gadget/Kconfig +@@ -150,7 +150,7 @@ config USB_AT91 + config USB_ATMEL_USBA + tristate "Atmel USBA" + select USB_GADGET_DUALSPEED +- depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 ++ depends on AVR32 || ARCH_AT91 + help + USBA is the integrated high-speed USB Device controller on + the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0045-ARM-at91-clock-fix-PLLA-overclock-warning.patch b/patches.at91/0045-ARM-at91-clock-fix-PLLA-overclock-warning.patch new file mode 100644 index 000000000000..50009b45b6fa --- /dev/null +++ b/patches.at91/0045-ARM-at91-clock-fix-PLLA-overclock-warning.patch @@ -0,0 +1,47 @@ +From 0880824561e6e9769027d83be21e5ab3f8aa9d31 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 9 Jul 2012 21:06:25 +0200 +Subject: ARM: at91/clock: fix PLLA overclock warning + +Fix PLLA overclock warning in relation with datasheet numbers. +Add new > 240 MHz and > 210 MHz SoC categories. + +Reported-by: Jiri Prchal +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/clock.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c +index de2ec6b..188c829 100644 +--- a/arch/arm/mach-at91/clock.c ++++ b/arch/arm/mach-at91/clock.c +@@ -63,6 +63,12 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); + + #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) + ++#define cpu_has_240M_plla() (cpu_is_at91sam9261() \ ++ || cpu_is_at91sam9263() \ ++ || cpu_is_at91sam9rl()) ++ ++#define cpu_has_210M_plla() (cpu_is_at91sam9260()) ++ + #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ + || cpu_is_at91sam9g45() \ + || cpu_is_at91sam9x5() \ +@@ -706,6 +712,12 @@ static int __init at91_pmc_init(unsigned long main_clock) + } else if (cpu_has_800M_plla()) { + if (plla.rate_hz > 800000000) + pll_overclock = true; ++ } else if (cpu_has_240M_plla()) { ++ if (plla.rate_hz > 240000000) ++ pll_overclock = true; ++ } else if (cpu_has_210M_plla()) { ++ if (plla.rate_hz > 210000000) ++ pll_overclock = true; + } else { + if (plla.rate_hz > 209000000) + pll_overclock = true; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0046-ARM-at91-dts-remove-partial-parameter-in-at91sam9g25.patch b/patches.at91/0046-ARM-at91-dts-remove-partial-parameter-in-at91sam9g25.patch new file mode 100644 index 000000000000..721fb1e214f3 --- /dev/null +++ b/patches.at91/0046-ARM-at91-dts-remove-partial-parameter-in-at91sam9g25.patch @@ -0,0 +1,29 @@ +From 5870fd6e3a30ac854a4f38eba8976fbde68fa705 Mon Sep 17 00:00:00 2001 +From: Bo Shen +Date: Fri, 17 Aug 2012 16:23:56 +0800 +Subject: ARM: at91/dts: remove partial parameter in at91sam9g25ek.dts + +Remove the malformed "mem=" bootargs parameter in at91sam9g25ek.dts + +Signed-off-by: Bo Shen +Signed-off-by: Nicolas Ferre +--- + arch/arm/boot/dts/at91sam9g25ek.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts +index 7829a4d..96514c1 100644 +--- a/arch/arm/boot/dts/at91sam9g25ek.dts ++++ b/arch/arm/boot/dts/at91sam9g25ek.dts +@@ -15,7 +15,7 @@ + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { +- bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; ++ bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + }; + + ahb { +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0047-ARM-at91-set-i2c_board_info.type-to-ds1339-directly.patch b/patches.at91/0047-ARM-at91-set-i2c_board_info.type-to-ds1339-directly.patch new file mode 100644 index 000000000000..503985d9b9f9 --- /dev/null +++ b/patches.at91/0047-ARM-at91-set-i2c_board_info.type-to-ds1339-directly.patch @@ -0,0 +1,33 @@ +From 632b3f90968b823b65b84cac6b348b13ad662a95 Mon Sep 17 00:00:00 2001 +From: Paul Bolle +Date: Thu, 24 May 2012 16:30:29 +0200 +Subject: ARM: at91: set i2c_board_info.type to "ds1339" directly + +The single element of the cpu9krea_i2c_devices array (of type struct +i2c_board_info) has its "type" member set twice. First to "rtc-ds1307" +(through the I2C_BOARD_INFO macro) and then directly to "ds1339". Just +set it (once and) directly to "ds1339" instead. + +Signed-off-by: Paul Bolle +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/board-cpu9krea.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c +index 69951ec..ece0d76 100644 +--- a/arch/arm/mach-at91/board-cpu9krea.c ++++ b/arch/arm/mach-at91/board-cpu9krea.c +@@ -253,8 +253,7 @@ static struct gpio_led cpu9krea_leds[] = { + + static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = { + { +- I2C_BOARD_INFO("rtc-ds1307", 0x68), +- .type = "ds1339", ++ I2C_BOARD_INFO("ds1339", 0x68), + }, + }; + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0048-ARM-at91-defconfig-Remove-unaffected-config-option.patch b/patches.at91/0048-ARM-at91-defconfig-Remove-unaffected-config-option.patch new file mode 100644 index 000000000000..2a84b809661f --- /dev/null +++ b/patches.at91/0048-ARM-at91-defconfig-Remove-unaffected-config-option.patch @@ -0,0 +1,123 @@ +From 7b849b56ec5599dbe5454204511d904c0d1c2be4 Mon Sep 17 00:00:00 2001 +From: Richard Genoud +Date: Fri, 22 Jun 2012 15:29:28 +0200 +Subject: ARM: at91/defconfig: Remove unaffected config option + +The commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c removed the use of +CONFIG_MTD_NAND_ATMEL_ECC_NONE and CONFIG_MTD_NAND_ATMEL_ECC_HW but the +Kconfig file was forgotten. + +This patch remove those inoperative options. + +Signed-off-by: Richard Genoud +Signed-off-by: Nicolas Ferre +--- + arch/arm/configs/afeb9260_defconfig | 1 - + arch/arm/configs/at91sam9263_defconfig | 1 - + arch/arm/configs/qil-a9260_defconfig | 1 - + arch/arm/configs/usb-a9260_defconfig | 1 - + drivers/mtd/nand/Kconfig | 40 ---------------------------------- + 5 files changed, 44 deletions(-) + +diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig +index 2afdf67..c285a9d 100644 +--- a/arch/arm/configs/afeb9260_defconfig ++++ b/arch/arm/configs/afeb9260_defconfig +@@ -39,7 +39,6 @@ CONFIG_MTD_BLOCK=y + CONFIG_MTD_DATAFLASH=y + CONFIG_MTD_NAND=y + CONFIG_MTD_NAND_ATMEL=y +-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y + CONFIG_BLK_DEV_RAM=y + CONFIG_BLK_DEV_RAM_SIZE=8192 + CONFIG_ATMEL_SSC=y +diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig +index 1cf9626..585e7e0 100644 +--- a/arch/arm/configs/at91sam9263_defconfig ++++ b/arch/arm/configs/at91sam9263_defconfig +@@ -61,7 +61,6 @@ CONFIG_MTD_DATAFLASH=y + CONFIG_MTD_BLOCK2MTD=y + CONFIG_MTD_NAND=y + CONFIG_MTD_NAND_ATMEL=y +-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y + CONFIG_MTD_UBI=y + CONFIG_MTD_UBI_GLUEBI=y + CONFIG_BLK_DEV_LOOP=y +diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig +index 9160f3b..2bb100b 100644 +--- a/arch/arm/configs/qil-a9260_defconfig ++++ b/arch/arm/configs/qil-a9260_defconfig +@@ -50,7 +50,6 @@ CONFIG_MTD_BLOCK=y + CONFIG_MTD_DATAFLASH=y + CONFIG_MTD_NAND=y + CONFIG_MTD_NAND_ATMEL=y +-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y + CONFIG_BLK_DEV_LOOP=y + # CONFIG_MISC_DEVICES is not set + CONFIG_SCSI=y +diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig +index 2e39f38..a1501e1 100644 +--- a/arch/arm/configs/usb-a9260_defconfig ++++ b/arch/arm/configs/usb-a9260_defconfig +@@ -49,7 +49,6 @@ CONFIG_MTD_BLOCK=y + CONFIG_MTD_DATAFLASH=y + CONFIG_MTD_NAND=y + CONFIG_MTD_NAND_ATMEL=y +-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y + CONFIG_BLK_DEV_LOOP=y + # CONFIG_MISC_DEVICES is not set + CONFIG_SCSI=y +diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig +index 7d17cec..0e43a3f 100644 +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -366,46 +366,6 @@ config MTD_NAND_ATMEL + help + Enables support for NAND Flash / Smart Media Card interface + on Atmel AT91 and AVR32 processors. +-choice +- prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32" +- depends on MTD_NAND_ATMEL +- +-config MTD_NAND_ATMEL_ECC_HW +- bool "Hardware ECC" +- depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32 +- help +- Use hardware ECC instead of software ECC when the chip +- supports it. +- +- The hardware ECC controller is capable of single bit error +- correction and 2-bit random detection per page. +- +- NB : hardware and software ECC schemes are incompatible. +- If you switch from one to another, you'll have to erase your +- mtd partition. +- +- If unsure, say Y +- +-config MTD_NAND_ATMEL_ECC_SOFT +- bool "Software ECC" +- help +- Use software ECC. +- +- NB : hardware and software ECC schemes are incompatible. +- If you switch from one to another, you'll have to erase your +- mtd partition. +- +-config MTD_NAND_ATMEL_ECC_NONE +- bool "No ECC (testing only, DANGEROUS)" +- depends on DEBUG_KERNEL +- help +- No ECC will be used. +- It's not a good idea and it should be reserved for testing +- purpose only. +- +- If unsure, say N +- +-endchoice + + config MTD_NAND_PXA3xx + tristate "Support for NAND flash devices on PXA3xx" +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0049-ARM-at91-fix-missing-interrupt-cells-on-gpio-control.patch b/patches.at91/0049-ARM-at91-fix-missing-interrupt-cells-on-gpio-control.patch new file mode 100644 index 000000000000..06db420f8ecd --- /dev/null +++ b/patches.at91/0049-ARM-at91-fix-missing-interrupt-cells-on-gpio-control.patch @@ -0,0 +1,207 @@ +From 567e6c4f49b1acf13d0e60ba9a6e1faa78f865a1 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu, 13 Sep 2012 12:40:26 +0200 +Subject: ARM: at91: fix missing #interrupt-cells on gpio-controller + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Tested-by: Bo Shen +Signed-off-by: Nicolas Ferre +--- + arch/arm/boot/dts/at91sam9260.dtsi | 3 +++ + arch/arm/boot/dts/at91sam9263.dtsi | 5 +++++ + arch/arm/boot/dts/at91sam9g45.dtsi | 5 +++++ + arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++++ + arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++++ + 5 files changed, 21 insertions(+) + +diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi +index f4605ff..eddc467 100644 +--- a/arch/arm/boot/dts/at91sam9260.dtsi ++++ b/arch/arm/boot/dts/at91sam9260.dtsi +@@ -103,6 +103,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioB: gpio@fffff600 { +@@ -112,6 +113,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioC: gpio@fffff800 { +@@ -121,6 +123,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + dbgu: serial@fffff200 { +diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi +index 0209913..d330de9 100644 +--- a/arch/arm/boot/dts/at91sam9263.dtsi ++++ b/arch/arm/boot/dts/at91sam9263.dtsi +@@ -94,6 +94,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioB: gpio@fffff400 { +@@ -103,6 +104,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioC: gpio@fffff600 { +@@ -112,6 +114,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioD: gpio@fffff800 { +@@ -121,6 +124,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioE: gpio@fffffa00 { +@@ -130,6 +134,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + dbgu: serial@ffffee00 { +diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi +index c804214..d1c497d 100644 +--- a/arch/arm/boot/dts/at91sam9g45.dtsi ++++ b/arch/arm/boot/dts/at91sam9g45.dtsi +@@ -112,6 +112,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioB: gpio@fffff400 { +@@ -121,6 +122,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioC: gpio@fffff600 { +@@ -130,6 +132,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioD: gpio@fffff800 { +@@ -139,6 +142,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioE: gpio@fffffa00 { +@@ -148,6 +152,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + dbgu: serial@ffffee00 { +diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi +index cb84de7..a69e89a 100644 +--- a/arch/arm/boot/dts/at91sam9n12.dtsi ++++ b/arch/arm/boot/dts/at91sam9n12.dtsi +@@ -107,6 +107,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioB: gpio@fffff600 { +@@ -116,6 +117,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioC: gpio@fffff800 { +@@ -125,6 +127,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioD: gpio@fffffa00 { +@@ -134,6 +137,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + dbgu: serial@fffff200 { +diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi +index dd4ed74..80a50864 100644 +--- a/arch/arm/boot/dts/at91sam9x5.dtsi ++++ b/arch/arm/boot/dts/at91sam9x5.dtsi +@@ -114,6 +114,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioB: gpio@fffff600 { +@@ -123,6 +124,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioC: gpio@fffff800 { +@@ -132,6 +134,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + pioD: gpio@fffffa00 { +@@ -141,6 +144,7 @@ + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; ++ #interrupt-cells = <2>; + }; + + dbgu: serial@fffff200 { +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0051-ARM-at91-missing-header-file-for-rtc-at91rm9200.c.patch b/patches.at91/0051-ARM-at91-missing-header-file-for-rtc-at91rm9200.c.patch new file mode 100644 index 000000000000..157177082280 --- /dev/null +++ b/patches.at91/0051-ARM-at91-missing-header-file-for-rtc-at91rm9200.c.patch @@ -0,0 +1,28 @@ +From d20929e0422398f34a241a11d9183fc7750c9f4e Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Wed, 19 Sep 2012 10:02:32 +0200 +Subject: ARM: at91: missing header file for rtc-at91rm9200.c + +Missing asm/io.h inclusion causing issue with __raw_readl and +__raw_writel. + +Signed-off-by: Ludovic Desroches +--- + drivers/rtc/rtc-at91rm9200.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c +index dc474bc..f02acb0 100644 +--- a/drivers/rtc/rtc-at91rm9200.c ++++ b/drivers/rtc/rtc-at91rm9200.c +@@ -28,6 +28,7 @@ + #include + #include + ++#include + #include + + #include +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0052-ASoC-atmel-ssc-include-linux-io.h-for-raw-io.patch b/patches.at91/0052-ASoC-atmel-ssc-include-linux-io.h-for-raw-io.patch new file mode 100644 index 000000000000..f5e8dcfeb5ac --- /dev/null +++ b/patches.at91/0052-ASoC-atmel-ssc-include-linux-io.h-for-raw-io.patch @@ -0,0 +1,37 @@ +From dc55ac7fd56dc3973d15f3a263b29ce222715771 Mon Sep 17 00:00:00 2001 +From: Joachim Eastwood +Date: Thu, 23 Aug 2012 18:14:54 +0200 +Subject: ASoC: atmel-ssc: include linux/io.h for raw io + +Include linux/io.h for raw io operations in atmel-scc header. + +This fixes the following build error: + CC [M] sound/soc/atmel/atmel_ssc_dai.o +sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt': +sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl' +sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown': +sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel' + +Signed-off-by: Joachim Eastwood +Signed-off-by: Nicolas Ferre +Acked-by: Jean-Christophe PLAGNIOL-VILLARD +Signed-off-by: Mark Brown +--- + include/linux/atmel-ssc.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h +index 0602339..4eb3175 100644 +--- a/include/linux/atmel-ssc.h ++++ b/include/linux/atmel-ssc.h +@@ -3,6 +3,7 @@ + + #include + #include ++#include + + struct ssc_device { + struct list_head list; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0053-ARM-at91-aic-can-use-fast-eoi-handler-type.patch b/patches.at91/0053-ARM-at91-aic-can-use-fast-eoi-handler-type.patch new file mode 100644 index 000000000000..6003ca8075ef --- /dev/null +++ b/patches.at91/0053-ARM-at91-aic-can-use-fast-eoi-handler-type.patch @@ -0,0 +1,158 @@ +From adc32a9ee5875fe4c0da12b676b38c696d95437c Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Fri, 25 May 2012 14:11:51 +0200 +Subject: ARM: at91: aic can use fast eoi handler type + +The Advanced Interrupt Controller allows us to use the fast EOI handler type. +It lets us remove the Atmel specific workaround into arch/arm/kernel/irq.c +used to indicate to the AIC the end of the interrupt treatment. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Will Deacon +--- + arch/arm/kernel/irq.c | 10 ---------- + arch/arm/mach-at91/gpio.c | 9 +++++---- + arch/arm/mach-at91/include/mach/irqs.h | 7 ------- + arch/arm/mach-at91/irq.c | 15 ++++++++++++--- + 4 files changed, 17 insertions(+), 24 deletions(-) + +diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c +index 8349d4e..16cedb4 100644 +--- a/arch/arm/kernel/irq.c ++++ b/arch/arm/kernel/irq.c +@@ -40,13 +40,6 @@ + #include + #include + +-/* +- * No architecture-specific irq_finish function defined in arm/arch/irqs.h. +- */ +-#ifndef irq_finish +-#define irq_finish(irq) do { } while (0) +-#endif +- + unsigned long irq_err_count; + + int arch_show_interrupts(struct seq_file *p, int prec) +@@ -85,9 +78,6 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs) + generic_handle_irq(irq); + } + +- /* AT91 specific workaround */ +- irq_finish(irq); +- + irq_exit(); + set_irq_regs(old_regs); + } +diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c +index 325837a..be42cf0 100644 +--- a/arch/arm/mach-at91/gpio.c ++++ b/arch/arm/mach-at91/gpio.c +@@ -26,6 +26,8 @@ + #include + #include + ++#include ++ + #include + #include + +@@ -585,15 +587,14 @@ static struct irq_chip gpio_irqchip = { + + static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) + { ++ struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_data *idata = irq_desc_get_irq_data(desc); +- struct irq_chip *chip = irq_data_get_irq_chip(idata); + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); + void __iomem *pio = at91_gpio->regbase; + unsigned long isr; + int n; + +- /* temporarily mask (level sensitive) parent IRQ */ +- chip->irq_ack(idata); ++ chained_irq_enter(chip, desc); + for (;;) { + /* Reading ISR acks pending (edge triggered) GPIO interrupts. + * When there none are pending, we're finished unless we need +@@ -614,7 +615,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) + n = find_next_bit(&isr, BITS_PER_LONG, n + 1); + } + } +- chip->irq_unmask(idata); ++ chained_irq_exit(chip, desc); + /* now it may re-trigger */ + } + +diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h +index ac8b7df..2d510ee 100644 +--- a/arch/arm/mach-at91/include/mach/irqs.h ++++ b/arch/arm/mach-at91/include/mach/irqs.h +@@ -28,13 +28,6 @@ + + + /* +- * Acknowledge interrupt with AIC after interrupt has been handled. +- * (by kernel/irq.c) +- */ +-#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0) +- +- +-/* + * IRQ interrupt symbols are the AT91xxx_ID_* symbols + * for IRQs handled directly through the AIC, or else the AT91_PIN_* + * symbols in gpio.h for ones handled indirectly as GPIOs. +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index cfcfcbe..2d5d4c8 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -55,6 +55,15 @@ static void at91_aic_unmask_irq(struct irq_data *d) + at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq); + } + ++static void at91_aic_eoi(struct irq_data *d) ++{ ++ /* ++ * Mark end-of-interrupt on AIC, the controller doesn't care about ++ * the value written. Moreover it's a write-only register. ++ */ ++ at91_aic_write(AT91_AIC_EOICR, 0); ++} ++ + unsigned int at91_extern_irq; + + #define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq) +@@ -128,11 +137,11 @@ void at91_irq_resume(void) + + static struct irq_chip at91_aic_chip = { + .name = "AIC", +- .irq_ack = at91_aic_mask_irq, + .irq_mask = at91_aic_mask_irq, + .irq_unmask = at91_aic_unmask_irq, + .irq_set_type = at91_aic_set_type, + .irq_set_wake = at91_aic_set_wake, ++ .irq_eoi = at91_aic_eoi, + }; + + static void __init at91_aic_hw_init(unsigned int spu_vector) +@@ -171,7 +180,7 @@ static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, + /* Active Low interrupt, without priority */ + at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW); + +- irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq); ++ irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + + return 0; +@@ -238,7 +247,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) + /* Active Low interrupt, with the specified priority */ + at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); + +- irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &at91_aic_chip, handle_fasteoi_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0054-ARM-at91-aic-add-dt-support-for-external-irqs.patch b/patches.at91/0054-ARM-at91-aic-add-dt-support-for-external-irqs.patch new file mode 100644 index 000000000000..4850ef400ae8 --- /dev/null +++ b/patches.at91/0054-ARM-at91-aic-add-dt-support-for-external-irqs.patch @@ -0,0 +1,122 @@ +From 6591d7a4f331b00fa020ef27b367239854944459 Mon Sep 17 00:00:00 2001 +From: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon, 9 Apr 2012 19:36:36 +0800 +Subject: ARM: at91: aic add dt support for external irqs + +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +--- + Documentation/devicetree/bindings/arm/atmel-aic.txt | 1 + + arch/arm/boot/dts/at91sam9260.dtsi | 1 + + arch/arm/boot/dts/at91sam9263.dtsi | 1 + + arch/arm/boot/dts/at91sam9g45.dtsi | 1 + + arch/arm/boot/dts/at91sam9x5.dtsi | 1 + + arch/arm/mach-at91/at91sam9x5.c | 2 -- + arch/arm/mach-at91/irq.c | 12 ++++++++++++ + 7 files changed, 17 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt +index aabca4f..1953b0c 100644 +--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt ++++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt +@@ -15,6 +15,7 @@ Required properties: + Valid combinations are 1, 2, 3, 4, 8. + Default flag for internal sources should be set to 4 (active high). + - reg: Should contain AIC registers location and length ++- atmel,external-irqs: u32 array of external irqs. + + Examples: + /* +diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi +index eddc467..fb86de0 100644 +--- a/arch/arm/boot/dts/at91sam9260.dtsi ++++ b/arch/arm/boot/dts/at91sam9260.dtsi +@@ -56,6 +56,7 @@ + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; ++ atmel,external-irqs = <29 30 31>; + }; + + ramc0: ramc@ffffea00 { +diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi +index d330de9..78b2808 100644 +--- a/arch/arm/boot/dts/at91sam9263.dtsi ++++ b/arch/arm/boot/dts/at91sam9263.dtsi +@@ -52,6 +52,7 @@ + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; ++ atmel,external-irqs = <30 31>; + }; + + pmc: pmc@fffffc00 { +diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi +index d1c497d..779ffca 100644 +--- a/arch/arm/boot/dts/at91sam9g45.dtsi ++++ b/arch/arm/boot/dts/at91sam9g45.dtsi +@@ -57,6 +57,7 @@ + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; ++ atmel,external-irqs = <31>; + }; + + ramc0: ramc@ffffe400 { +diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi +index 80a50864..170b6f8 100644 +--- a/arch/arm/boot/dts/at91sam9x5.dtsi ++++ b/arch/arm/boot/dts/at91sam9x5.dtsi +@@ -55,6 +55,7 @@ + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; ++ atmel,external-irqs = <31>; + }; + + ramc0: ramc@ffffe800 { +diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c +index 13c8cae..dce3ff3 100644 +--- a/arch/arm/mach-at91/at91sam9x5.c ++++ b/arch/arm/mach-at91/at91sam9x5.c +@@ -306,8 +306,6 @@ static void __init at91sam9x5_map_io(void) + + void __init at91sam9x5_initialize(void) + { +- at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0); +- + /* Register GPIO subsystem (using DT) */ + at91_gpio_init(NULL, 0); + } +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index 2d5d4c8..df8605f 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -194,6 +194,10 @@ static struct irq_domain_ops at91_aic_irq_ops = { + int __init at91_aic_of_init(struct device_node *node, + struct device_node *parent) + { ++ struct property *prop; ++ const __be32 *p; ++ u32 val; ++ + at91_aic_base = of_iomap(node, 0); + at91_aic_np = node; + +@@ -202,6 +206,14 @@ int __init at91_aic_of_init(struct device_node *node, + if (!at91_aic_domain) + panic("Unable to add AIC irq domain (DT)\n"); + ++ at91_extern_irq = 0; ++ of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) { ++ if (val > 31) ++ pr_warn("AIC: external irq %d > 31 skip it\n", val); ++ else ++ at91_extern_irq |= (1 << val); ++ } ++ + irq_set_default_host(at91_aic_domain); + + at91_aic_hw_init(NR_AIC_IRQS); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0055-ARM-at91-add-of-irq-priorities-support.patch b/patches.at91/0055-ARM-at91-add-of-irq-priorities-support.patch new file mode 100644 index 000000000000..ed2769e343ed --- /dev/null +++ b/patches.at91/0055-ARM-at91-add-of-irq-priorities-support.patch @@ -0,0 +1,883 @@ +From 2e9f08703ba386c61ee33e8a7018ef12c361b463 Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Wed, 20 Jun 2012 16:13:30 +0200 +Subject: ARM: at91: add of irq priorities support + +Add a third cell to define irq priority. + +Signed-off-by: Ludovic Desroches +Reviewed-by: Rob Herring +Signed-off-by: Nicolas Ferre + +Conflicts: + arch/arm/boot/dts/at91sam9260.dtsi + arch/arm/boot/dts/at91sam9g45.dtsi + arch/arm/boot/dts/at91sam9x5.dtsi +--- + .../devicetree/bindings/arm/atmel-aic.txt | 8 +++-- + arch/arm/boot/dts/at91sam9260.dtsi | 34 ++++++++++---------- + arch/arm/boot/dts/at91sam9263.dtsi | 30 +++++++++--------- + arch/arm/boot/dts/at91sam9g45.dtsi | 36 +++++++++++----------- + arch/arm/boot/dts/at91sam9n12.dtsi | 30 +++++++++--------- + arch/arm/boot/dts/at91sam9x5.dtsi | 36 +++++++++++----------- + arch/arm/mach-at91/include/mach/at91_aic.h | 3 ++ + arch/arm/mach-at91/irq.c | 34 ++++++++++++++++++-- + 8 files changed, 122 insertions(+), 89 deletions(-) + +diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt +index 1953b0c..19078bf 100644 +--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt ++++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt +@@ -4,7 +4,7 @@ Required properties: + - compatible: Should be "atmel,-aic" + - interrupt-controller: Identifies the node as an interrupt controller. + - interrupt-parent: For single AIC system, it is an empty property. +-- #interrupt-cells: The number of cells to define the interrupts. It sould be 2. ++- #interrupt-cells: The number of cells to define the interrupts. It sould be 3. + The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). + The second cell is used to specify flags: + bits[3:0] trigger type and level flags: +@@ -14,6 +14,8 @@ Required properties: + 8 = active low level-sensitive. + Valid combinations are 1, 2, 3, 4, 8. + Default flag for internal sources should be set to 4 (active high). ++ The third cell is used to specify the irq priority from 0 (lowest) to 7 ++ (highest). + - reg: Should contain AIC registers location and length + - atmel,external-irqs: u32 array of external irqs. + +@@ -25,7 +27,7 @@ Examples: + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + interrupt-parent; +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + reg = <0xfffff000 0x200>; + }; + +@@ -35,5 +37,5 @@ Examples: + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; +- interrupts = <21 4>; ++ interrupts = <21 4 5>; + }; +diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi +index fb86de0..12df8ca 100644 +--- a/arch/arm/boot/dts/at91sam9260.dtsi ++++ b/arch/arm/boot/dts/at91sam9260.dtsi +@@ -52,7 +52,7 @@ + ranges; + + aic: interrupt-controller@fffff000 { +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; +@@ -82,25 +82,25 @@ + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + }; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; +- interrupts = <17 4 18 4 19 4>; ++ interrupts = <17 4 0 18 4 0 19 4 0>; + }; + + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffdc000 0x100>; +- interrupts = <26 4 27 4 28 4>; ++ interrupts = <26 4 0 27 4 0 28 4 0>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -110,7 +110,7 @@ + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -120,7 +120,7 @@ + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; +- interrupts = <4 4>; ++ interrupts = <4 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -130,14 +130,14 @@ + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; +- interrupts = <6 4>; ++ interrupts = <6 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -146,7 +146,7 @@ + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; +- interrupts = <7 4>; ++ interrupts = <7 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -155,7 +155,7 @@ + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; +- interrupts = <8 4>; ++ interrupts = <8 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -164,7 +164,7 @@ + usart3: serial@fffd0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd0000 0x200>; +- interrupts = <23 4>; ++ interrupts = <23 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -173,7 +173,7 @@ + usart4: serial@fffd4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd4000 0x200>; +- interrupts = <24 4>; ++ interrupts = <24 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -182,7 +182,7 @@ + usart5: serial@fffd8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd8000 0x200>; +- interrupts = <25 4>; ++ interrupts = <25 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -191,14 +191,14 @@ + macb0: ethernet@fffc4000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; +- interrupts = <21 4>; ++ interrupts = <21 4 3>; + status = "disabled"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91rm9200-udc"; + reg = <0xfffa4000 0x4000>; +- interrupts = <10 4>; ++ interrupts = <10 4 2>; + status = "disabled"; + }; + }; +@@ -222,7 +222,7 @@ + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; +- interrupts = <20 4>; ++ interrupts = <20 4 2>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi +index 78b2808..195019b 100644 +--- a/arch/arm/boot/dts/at91sam9263.dtsi ++++ b/arch/arm/boot/dts/at91sam9263.dtsi +@@ -48,7 +48,7 @@ + ranges; + + aic: interrupt-controller@fffff000 { +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; +@@ -69,13 +69,13 @@ + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + }; + + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfff7c000 0x100>; +- interrupts = <19 4>; ++ interrupts = <19 4 0>; + }; + + rstc@fffffd00 { +@@ -91,7 +91,7 @@ + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -101,7 +101,7 @@ + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -111,7 +111,7 @@ + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; +- interrupts = <4 4>; ++ interrupts = <4 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -121,7 +121,7 @@ + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; +- interrupts = <4 4>; ++ interrupts = <4 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -131,7 +131,7 @@ + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; +- interrupts = <4 4>; ++ interrupts = <4 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -141,14 +141,14 @@ + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; +- interrupts = <7 4>; ++ interrupts = <7 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -157,7 +157,7 @@ + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; +- interrupts = <8 4>; ++ interrupts = <8 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -166,7 +166,7 @@ + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; +- interrupts = <9 4>; ++ interrupts = <9 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -175,14 +175,14 @@ + macb0: ethernet@fffbc000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; +- interrupts = <21 4>; ++ interrupts = <21 4 3>; + status = "disabled"; + }; + + usb1: gadget@fff78000 { + compatible = "atmel,at91rm9200-udc"; + reg = <0xfff78000 0x4000>; +- interrupts = <24 4>; ++ interrupts = <24 4 2>; + status = "disabled"; + }; + }; +@@ -206,7 +206,7 @@ + usb0: ohci@00a00000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00a00000 0x100000>; +- interrupts = <29 4>; ++ interrupts = <29 4 2>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi +index 779ffca..6a3ed54 100644 +--- a/arch/arm/boot/dts/at91sam9g45.dtsi ++++ b/arch/arm/boot/dts/at91sam9g45.dtsi +@@ -53,7 +53,7 @@ + ranges; + + aic: interrupt-controller@fffff000 { +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; +@@ -79,7 +79,7 @@ + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + }; + + +@@ -91,25 +91,25 @@ + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfff7c000 0x100>; +- interrupts = <18 4>; ++ interrupts = <18 4 0>; + }; + + tcb1: timer@fffd4000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffd4000 0x100>; +- interrupts = <18 4>; ++ interrupts = <18 4 0>; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; +- interrupts = <21 4>; ++ interrupts = <21 4 0>; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -119,7 +119,7 @@ + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -129,7 +129,7 @@ + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; +- interrupts = <4 4>; ++ interrupts = <4 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -139,7 +139,7 @@ + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; +- interrupts = <5 4>; ++ interrupts = <5 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -149,7 +149,7 @@ + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; +- interrupts = <5 4>; ++ interrupts = <5 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -159,14 +159,14 @@ + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; +- interrupts = <7 4>; ++ interrupts = <7 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -175,7 +175,7 @@ + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; +- interrupts = <8 4>; ++ interrupts = <8 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -184,7 +184,7 @@ + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; +- interrupts = <9 4>; ++ interrupts = <9 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -193,7 +193,7 @@ + usart3: serial@fff98000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff98000 0x200>; +- interrupts = <10 4>; ++ interrupts = <10 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -202,7 +202,7 @@ + macb0: ethernet@fffbc000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; +- interrupts = <25 4>; ++ interrupts = <25 4 3>; + status = "disabled"; + }; + }; +@@ -226,14 +226,14 @@ + usb0: ohci@00700000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00700000 0x100000>; +- interrupts = <22 4>; ++ interrupts = <22 4 2>; + status = "disabled"; + }; + + usb1: ehci@00800000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00800000 0x100000>; +- interrupts = <22 4>; ++ interrupts = <22 4 2>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi +index a69e89a..ef9336a 100644 +--- a/arch/arm/boot/dts/at91sam9n12.dtsi ++++ b/arch/arm/boot/dts/at91sam9n12.dtsi +@@ -50,7 +50,7 @@ + ranges; + + aic: interrupt-controller@fffff000 { +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; +@@ -74,7 +74,7 @@ + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + }; + + shdwc@fffffe10 { +@@ -85,25 +85,25 @@ + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; +- interrupts = <17 4>; ++ interrupts = <17 4 0>; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; +- interrupts = <17 4>; ++ interrupts = <17 4 0>; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; +- interrupts = <20 4>; ++ interrupts = <20 4 0>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -113,7 +113,7 @@ + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -123,7 +123,7 @@ + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -133,7 +133,7 @@ + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -143,14 +143,14 @@ + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x4000>; +- interrupts = <5 4>; ++ interrupts = <5 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -159,7 +159,7 @@ + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x4000>; +- interrupts = <6 4>; ++ interrupts = <6 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -168,7 +168,7 @@ + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x4000>; +- interrupts = <7 4>; ++ interrupts = <7 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -177,7 +177,7 @@ + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x4000>; +- interrupts = <8 4>; ++ interrupts = <8 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -205,7 +205,7 @@ + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x00100000>; +- interrupts = <22 4>; ++ interrupts = <22 4 2>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi +index 170b6f8..fc38d21 100644 +--- a/arch/arm/boot/dts/at91sam9x5.dtsi ++++ b/arch/arm/boot/dts/at91sam9x5.dtsi +@@ -51,7 +51,7 @@ + ranges; + + aic: interrupt-controller@fffff000 { +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; +@@ -81,37 +81,37 @@ + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; +- interrupts = <17 4>; ++ interrupts = <17 4 0>; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; +- interrupts = <17 4>; ++ interrupts = <17 4 0>; + }; + + dma0: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; +- interrupts = <20 4>; ++ interrupts = <20 4 0>; + }; + + dma1: dma-controller@ffffee00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffee00 0x200>; +- interrupts = <21 4>; ++ interrupts = <21 4 0>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -121,7 +121,7 @@ + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; +- interrupts = <2 4>; ++ interrupts = <2 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -131,7 +131,7 @@ + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -141,7 +141,7 @@ + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; +- interrupts = <3 4>; ++ interrupts = <3 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; +@@ -151,14 +151,14 @@ + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; +- interrupts = <1 4>; ++ interrupts = <1 4 7>; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x200>; +- interrupts = <5 4>; ++ interrupts = <5 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -167,7 +167,7 @@ + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x200>; +- interrupts = <6 4>; ++ interrupts = <6 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -176,7 +176,7 @@ + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x200>; +- interrupts = <7 4>; ++ interrupts = <7 4 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; +@@ -185,14 +185,14 @@ + macb0: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; +- interrupts = <24 4>; ++ interrupts = <24 4 3>; + status = "disabled"; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; +- interrupts = <27 4>; ++ interrupts = <27 4 3>; + status = "disabled"; + }; + }; +@@ -215,14 +215,14 @@ + usb0: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; +- interrupts = <22 4>; ++ interrupts = <22 4 2>; + status = "disabled"; + }; + + usb1: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; +- interrupts = <22 4>; ++ interrupts = <22 4 2>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h +index c1413ed..3af7272 100644 +--- a/arch/arm/mach-at91/include/mach/at91_aic.h ++++ b/arch/arm/mach-at91/include/mach/at91_aic.h +@@ -28,6 +28,9 @@ extern void __iomem *at91_aic_base; + .extern at91_aic_base + #endif + ++#define AT91_AIC_IRQ_MIN_PRIORITY 0 ++#define AT91_AIC_IRQ_MAX_PRIORITY 7 ++ + #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ + #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ + #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index df8605f..db8e141 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -42,6 +43,7 @@ + void __iomem *at91_aic_base; + static struct irq_domain *at91_aic_domain; + static struct device_node *at91_aic_np; ++static unsigned int *at91_aic_irq_priorities; + + static void at91_aic_mask_irq(struct irq_data *d) + { +@@ -177,8 +179,9 @@ static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, + /* Put virq number in Source Vector Register */ + at91_aic_write(AT91_AIC_SVR(hw), virq); + +- /* Active Low interrupt, without priority */ +- at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW); ++ /* Active Low interrupt, with priority */ ++ at91_aic_write(AT91_AIC_SMR(hw), ++ AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]); + + irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); +@@ -186,9 +189,28 @@ static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, + return 0; + } + ++static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, ++ const u32 *intspec, unsigned int intsize, ++ irq_hw_number_t *out_hwirq, unsigned int *out_type) ++{ ++ if (WARN_ON(intsize < 3)) ++ return -EINVAL; ++ if (WARN_ON(intspec[0] >= NR_AIC_IRQS)) ++ return -EINVAL; ++ if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ++ || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY))) ++ return -EINVAL; ++ ++ *out_hwirq = intspec[0]; ++ *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; ++ at91_aic_irq_priorities[*out_hwirq] = intspec[2]; ++ ++ return 0; ++} ++ + static struct irq_domain_ops at91_aic_irq_ops = { + .map = at91_aic_irq_map, +- .xlate = irq_domain_xlate_twocell, ++ .xlate = at91_aic_irq_domain_xlate, + }; + + int __init at91_aic_of_init(struct device_node *node, +@@ -198,6 +220,12 @@ int __init at91_aic_of_init(struct device_node *node, + const __be32 *p; + u32 val; + ++ at91_aic_irq_priorities = kzalloc(NR_AIC_IRQS ++ * sizeof(*at91_aic_irq_priorities), ++ GFP_KERNEL); ++ if (!at91_aic_irq_priorities) ++ return -ENOMEM; ++ + at91_aic_base = of_iomap(node, 0); + at91_aic_np = node; + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0056-ARM-at91-remove-static-irq-priorities-for-sam9x5.patch b/patches.at91/0056-ARM-at91-remove-static-irq-priorities-for-sam9x5.patch new file mode 100644 index 000000000000..395295b3151b --- /dev/null +++ b/patches.at91/0056-ARM-at91-remove-static-irq-priorities-for-sam9x5.patch @@ -0,0 +1,69 @@ +From 253f40569228efcd947997772f9e913aef4e8dec Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Fri, 22 Jun 2012 11:41:34 +0200 +Subject: ARM: at91: remove static irq priorities for sam9x5 + +Since irq priorites are managed in DT, static ones are no more required for +sam9x5 which only has DT support. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/at91sam9x5.c | 38 -------------------------------------- + 1 file changed, 38 deletions(-) + +diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c +index dce3ff3..c949dc7 100644 +--- a/arch/arm/mach-at91/at91sam9x5.c ++++ b/arch/arm/mach-at91/at91sam9x5.c +@@ -313,47 +313,9 @@ void __init at91sam9x5_initialize(void) + /* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ +-/* +- * The default interrupt priority levels (0 = lowest, 7 = highest). +- */ +-static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = { +- 7, /* Advanced Interrupt Controller (FIQ) */ +- 7, /* System Peripherals */ +- 1, /* Parallel IO Controller A and B */ +- 1, /* Parallel IO Controller C and D */ +- 4, /* Soft Modem */ +- 5, /* USART 0 */ +- 5, /* USART 1 */ +- 5, /* USART 2 */ +- 5, /* USART 3 */ +- 6, /* Two-Wire Interface 0 */ +- 6, /* Two-Wire Interface 1 */ +- 6, /* Two-Wire Interface 2 */ +- 0, /* Multimedia Card Interface 0 */ +- 5, /* Serial Peripheral Interface 0 */ +- 5, /* Serial Peripheral Interface 1 */ +- 5, /* UART 0 */ +- 5, /* UART 1 */ +- 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +- 0, /* Pulse Width Modulation Controller */ +- 0, /* ADC Controller */ +- 0, /* DMA Controller 0 */ +- 0, /* DMA Controller 1 */ +- 2, /* USB Host High Speed port */ +- 2, /* USB Device High speed port */ +- 3, /* Ethernet MAC 0 */ +- 3, /* LDC Controller or Image Sensor Interface */ +- 0, /* Multimedia Card Interface 1 */ +- 3, /* Ethernet MAC 1 */ +- 4, /* Synchronous Serial Interface */ +- 4, /* CAN Controller 0 */ +- 4, /* CAN Controller 1 */ +- 0, /* Advanced Interrupt Controller (IRQ0) */ +-}; + + struct at91_init_soc __initdata at91sam9x5_soc = { + .map_io = at91sam9x5_map_io, +- .default_irq_priority = at91sam9x5_default_irq_priority, + .register_clocks = at91sam9x5_register_clocks, + .init = at91sam9x5_initialize, + }; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0057-ARM-at91-at91-based-machines-specify-their-own-irq-h.patch b/patches.at91/0057-ARM-at91-at91-based-machines-specify-their-own-irq-h.patch new file mode 100644 index 000000000000..a02a21ce88c4 --- /dev/null +++ b/patches.at91/0057-ARM-at91-at91-based-machines-specify-their-own-irq-h.patch @@ -0,0 +1,903 @@ +From 4d4e7847287b4ad784ac97768d4768bbbfabe8a1 Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Mon, 11 Jun 2012 15:38:03 +0200 +Subject: ARM: at91: at91 based machines specify their own irq handler at run + time + +SOC_AT91SAM9 selects MULTI_IRQ_HANDLER in order to let machines specify their +own IRQ handler at run time. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 1 + + arch/arm/mach-at91/board-1arm.c | 2 ++ + arch/arm/mach-at91/board-afeb-9260v1.c | 2 ++ + arch/arm/mach-at91/board-cam60.c | 2 ++ + arch/arm/mach-at91/board-carmeva.c | 2 ++ + arch/arm/mach-at91/board-cpu9krea.c | 2 ++ + arch/arm/mach-at91/board-cpuat91.c | 2 ++ + arch/arm/mach-at91/board-csb337.c | 2 ++ + arch/arm/mach-at91/board-csb637.c | 2 ++ + arch/arm/mach-at91/board-dt.c | 2 ++ + arch/arm/mach-at91/board-eb01.c | 2 ++ + arch/arm/mach-at91/board-eb9200.c | 2 ++ + arch/arm/mach-at91/board-ecbat91.c | 2 ++ + arch/arm/mach-at91/board-eco920.c | 2 ++ + arch/arm/mach-at91/board-flexibity.c | 2 ++ + arch/arm/mach-at91/board-foxg20.c | 2 ++ + arch/arm/mach-at91/board-gsia18s.c | 2 ++ + arch/arm/mach-at91/board-kafa.c | 2 ++ + arch/arm/mach-at91/board-kb9202.c | 2 ++ + arch/arm/mach-at91/board-neocore926.c | 2 ++ + arch/arm/mach-at91/board-pcontrol-g20.c | 2 ++ + arch/arm/mach-at91/board-picotux200.c | 2 ++ + arch/arm/mach-at91/board-qil-a9260.c | 2 ++ + arch/arm/mach-at91/board-rm9200dk.c | 2 ++ + arch/arm/mach-at91/board-rm9200ek.c | 2 ++ + arch/arm/mach-at91/board-rsi-ews.c | 2 ++ + arch/arm/mach-at91/board-sam9-l9260.c | 2 ++ + arch/arm/mach-at91/board-sam9260ek.c | 2 ++ + arch/arm/mach-at91/board-sam9261ek.c | 2 ++ + arch/arm/mach-at91/board-sam9263ek.c | 2 ++ + arch/arm/mach-at91/board-sam9g20ek.c | 3 +++ + arch/arm/mach-at91/board-sam9m10g45ek.c | 2 ++ + arch/arm/mach-at91/board-sam9rlek.c | 2 ++ + arch/arm/mach-at91/board-snapper9260.c | 2 ++ + arch/arm/mach-at91/board-stamp9g20.c | 3 +++ + arch/arm/mach-at91/board-usb-a926x.c | 4 ++++ + arch/arm/mach-at91/board-yl-9200.c | 2 ++ + arch/arm/mach-at91/include/mach/at91_aic.h | 2 ++ + arch/arm/mach-at91/include/mach/entry-macro.S | 27 --------------------------- + arch/arm/mach-at91/irq.c | 19 +++++++++++++++++++ + 40 files changed, 98 insertions(+), 27 deletions(-) + delete mode 100644 arch/arm/mach-at91/include/mach/entry-macro.S + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 19505c0..e401dea 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -29,6 +29,7 @@ comment "Atmel AT91 Processor" + config SOC_AT91SAM9 + bool + select CPU_ARM926T ++ select MULTI_IRQ_HANDLER + select AT91_SAM9_TIME + select AT91_SAM9_SMC + +diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c +index 271f994..22d8856 100644 +--- a/arch/arm/mach-at91/board-1arm.c ++++ b/arch/arm/mach-at91/board-1arm.c +@@ -36,6 +36,7 @@ + + #include + #include ++#include + + #include "generic.h" + +@@ -91,6 +92,7 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") + /* Maintainer: Lennert Buytenhek */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = onearm_init_early, + .init_irq = at91_init_irq_default, + .init_machine = onearm_board_init, +diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c +index b7d8aa7..de7be19 100644 +--- a/arch/arm/mach-at91/board-afeb-9260v1.c ++++ b/arch/arm/mach-at91/board-afeb-9260v1.c +@@ -44,6 +44,7 @@ + #include + + #include ++#include + + #include "generic.h" + +@@ -212,6 +213,7 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board") + /* Maintainer: Sergey Lapin */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = afeb9260_init_early, + .init_irq = at91_init_irq_default, + .init_machine = afeb9260_board_init, +diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c +index 29d3ef0..477e708 100644 +--- a/arch/arm/mach-at91/board-cam60.c ++++ b/arch/arm/mach-at91/board-cam60.c +@@ -39,6 +39,7 @@ + #include + + #include ++#include + #include + + #include "sam9_smc.h" +@@ -188,6 +189,7 @@ MACHINE_START(CAM60, "KwikByte CAM60") + /* Maintainer: KwikByte */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = cam60_init_early, + .init_irq = at91_init_irq_default, + .init_machine = cam60_board_init, +diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c +index 44328a6..a5b002f 100644 +--- a/arch/arm/mach-at91/board-carmeva.c ++++ b/arch/arm/mach-at91/board-carmeva.c +@@ -36,6 +36,7 @@ + + #include + #include ++#include + + #include "generic.h" + +@@ -158,6 +159,7 @@ MACHINE_START(CARMEVA, "Carmeva") + /* Maintainer: Conitec Datasystems */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = carmeva_init_early, + .init_irq = at91_init_irq_default, + .init_machine = carmeva_board_init, +diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c +index ece0d76..7ddc219 100644 +--- a/arch/arm/mach-at91/board-cpu9krea.c ++++ b/arch/arm/mach-at91/board-cpu9krea.c +@@ -41,6 +41,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -375,6 +376,7 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") + /* Maintainer: Eric Benard - EUKREA Electromatique */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = cpu9krea_init_early, + .init_irq = at91_init_irq_default, + .init_machine = cpu9krea_board_init, +diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c +index 895cf2d..2e6d043 100644 +--- a/arch/arm/mach-at91/board-cpuat91.c ++++ b/arch/arm/mach-at91/board-cpuat91.c +@@ -37,6 +37,7 @@ + #include + + #include ++#include + #include + #include + #include +@@ -178,6 +179,7 @@ MACHINE_START(CPUAT91, "Eukrea") + /* Maintainer: Eric Benard - EUKREA Electromatique */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = cpuat91_init_early, + .init_irq = at91_init_irq_default, + .init_machine = cpuat91_board_init, +diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c +index cd81336..462bc31 100644 +--- a/arch/arm/mach-at91/board-csb337.c ++++ b/arch/arm/mach-at91/board-csb337.c +@@ -39,6 +39,7 @@ + + #include + #include ++#include + + #include "generic.h" + +@@ -252,6 +253,7 @@ MACHINE_START(CSB337, "Cogent CSB337") + /* Maintainer: Bill Gatliff */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = csb337_init_early, + .init_irq = at91_init_irq_default, + .init_machine = csb337_board_init, +diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c +index 7c8b05a..872871a 100644 +--- a/arch/arm/mach-at91/board-csb637.c ++++ b/arch/arm/mach-at91/board-csb637.c +@@ -36,6 +36,7 @@ + + #include + #include ++#include + + #include "generic.h" + +@@ -133,6 +134,7 @@ MACHINE_START(CSB637, "Cogent CSB637") + /* Maintainer: Bill Gatliff */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = csb637_init_early, + .init_irq = at91_init_irq_default, + .init_machine = csb637_board_init, +diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c +index a1fce05..e8f45c4 100644 +--- a/arch/arm/mach-at91/board-dt.c ++++ b/arch/arm/mach-at91/board-dt.c +@@ -16,6 +16,7 @@ + #include + + #include ++#include + + #include + #include +@@ -53,6 +54,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = at91_dt_initialize, + .init_irq = at91_dt_init_irq, + .init_machine = at91_dt_device_init, +diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c +index d2023f2..01f66e9 100644 +--- a/arch/arm/mach-at91/board-eb01.c ++++ b/arch/arm/mach-at91/board-eb01.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include "generic.h" + + static void __init at91eb01_init_irq(void) +@@ -43,6 +44,7 @@ static void __init at91eb01_init_early(void) + MACHINE_START(AT91EB01, "Atmel AT91 EB01") + /* Maintainer: Greg Ungerer */ + .timer = &at91x40_timer, ++ .handle_irq = at91_aic_handle_irq, + .init_early = at91eb01_init_early, + .init_irq = at91eb01_init_irq, + MACHINE_END +diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c +index bd10172..d1e1f3f 100644 +--- a/arch/arm/mach-at91/board-eb9200.c ++++ b/arch/arm/mach-at91/board-eb9200.c +@@ -36,6 +36,7 @@ + #include + + #include ++#include + + #include "generic.h" + +@@ -118,6 +119,7 @@ static void __init eb9200_board_init(void) + MACHINE_START(ATEB9200, "Embest ATEB9200") + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = eb9200_init_early, + .init_irq = at91_init_irq_default, + .init_machine = eb9200_board_init, +diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c +index 89cc372..9c24cb2 100644 +--- a/arch/arm/mach-at91/board-ecbat91.c ++++ b/arch/arm/mach-at91/board-ecbat91.c +@@ -39,6 +39,7 @@ + + #include + #include ++#include + + #include "generic.h" + +@@ -170,6 +171,7 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91") + /* Maintainer: emQbit.com */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ecb_at91init_early, + .init_irq = at91_init_irq_default, + .init_machine = ecb_at91board_init, +diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c +index 558546c..82bdfde 100644 +--- a/arch/arm/mach-at91/board-eco920.c ++++ b/arch/arm/mach-at91/board-eco920.c +@@ -25,6 +25,7 @@ + #include + + #include ++#include + #include + #include + #include +@@ -132,6 +133,7 @@ MACHINE_START(ECO920, "eco920") + /* Maintainer: Sascha Hauer */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = eco920_init_early, + .init_irq = at91_init_irq_default, + .init_machine = eco920_board_init, +diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c +index 47658f7..6cc83a8 100644 +--- a/arch/arm/mach-at91/board-flexibity.c ++++ b/arch/arm/mach-at91/board-flexibity.c +@@ -34,6 +34,7 @@ + + #include + #include ++#include + + #include "generic.h" + +@@ -160,6 +161,7 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect") + /* Maintainer: Maxim Osipov */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = flexibity_init_early, + .init_irq = at91_init_irq_default, + .init_machine = flexibity_board_init, +diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c +index 33411e6..69ab124 100644 +--- a/arch/arm/mach-at91/board-foxg20.c ++++ b/arch/arm/mach-at91/board-foxg20.c +@@ -42,6 +42,7 @@ + #include + + #include ++#include + #include + + #include "sam9_smc.h" +@@ -262,6 +263,7 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20") + /* Maintainer: Sergio Tanzilli */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = foxg20_init_early, + .init_irq = at91_init_irq_default, + .init_machine = foxg20_board_init, +diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c +index 3e0dfa6..a9d5e78 100644 +--- a/arch/arm/mach-at91/board-gsia18s.c ++++ b/arch/arm/mach-at91/board-gsia18s.c +@@ -31,6 +31,7 @@ + #include + + #include ++#include + #include + #include + #include +@@ -575,6 +576,7 @@ static void __init gsia18s_board_init(void) + MACHINE_START(GSIA18S, "GS_IA18_S") + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = gsia18s_init_early, + .init_irq = at91_init_irq_default, + .init_machine = gsia18s_board_init, +diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c +index f260657..64c1dbf 100644 +--- a/arch/arm/mach-at91/board-kafa.c ++++ b/arch/arm/mach-at91/board-kafa.c +@@ -35,6 +35,7 @@ + #include + + #include ++#include + #include + + #include "generic.h" +@@ -93,6 +94,7 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA") + /* Maintainer: Sergei Sharonov */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = kafa_init_early, + .init_irq = at91_init_irq_default, + .init_machine = kafa_board_init, +diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c +index ba39db5..5d96cb8 100644 +--- a/arch/arm/mach-at91/board-kb9202.c ++++ b/arch/arm/mach-at91/board-kb9202.c +@@ -37,6 +37,7 @@ + + #include + #include ++#include + #include + #include + +@@ -133,6 +134,7 @@ MACHINE_START(KB9200, "KB920x") + /* Maintainer: KwikByte, Inc. */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = kb9202_init_early, + .init_irq = at91_init_irq_default, + .init_machine = kb9202_board_init, +diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c +index d2f4cc1..18103c5d 100644 +--- a/arch/arm/mach-at91/board-neocore926.c ++++ b/arch/arm/mach-at91/board-neocore926.c +@@ -45,6 +45,7 @@ + + #include + #include ++#include + #include + + #include "sam9_smc.h" +@@ -378,6 +379,7 @@ MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") + /* Maintainer: ADENEO */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = neocore926_init_early, + .init_irq = at91_init_irq_default, + .init_machine = neocore926_board_init, +diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c +index 7fe6383..9ca3e32 100644 +--- a/arch/arm/mach-at91/board-pcontrol-g20.c ++++ b/arch/arm/mach-at91/board-pcontrol-g20.c +@@ -30,6 +30,7 @@ + #include + + #include ++#include + #include + #include + +@@ -218,6 +219,7 @@ MACHINE_START(PCONTROL_G20, "PControl G20") + /* Maintainer: pgsellmann@portner-elektronik.at */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = pcontrol_g20_init_early, + .init_irq = at91_init_irq_default, + .init_machine = pcontrol_g20_board_init, +diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c +index b45c0a5..1270655 100644 +--- a/arch/arm/mach-at91/board-picotux200.c ++++ b/arch/arm/mach-at91/board-picotux200.c +@@ -38,6 +38,7 @@ + #include + + #include ++#include + #include + #include + +@@ -120,6 +121,7 @@ MACHINE_START(PICOTUX2XX, "picotux 200") + /* Maintainer: Kleinhenz Elektronik GmbH */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = picotux200_init_early, + .init_irq = at91_init_irq_default, + .init_machine = picotux200_board_init, +diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c +index 0c61bf0..bf351e2 100644 +--- a/arch/arm/mach-at91/board-qil-a9260.c ++++ b/arch/arm/mach-at91/board-qil-a9260.c +@@ -41,6 +41,7 @@ + + #include + #include ++#include + #include + #include + +@@ -258,6 +259,7 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260") + /* Maintainer: calao-systems */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c +index afd7a47..cc2bf97 100644 +--- a/arch/arm/mach-at91/board-rm9200dk.c ++++ b/arch/arm/mach-at91/board-rm9200dk.c +@@ -40,6 +40,7 @@ + + #include + #include ++#include + #include + #include + +@@ -223,6 +224,7 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") + /* Maintainer: SAN People/Atmel */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = dk_init_early, + .init_irq = at91_init_irq_default, + .init_machine = dk_board_init, +diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c +index 2b15b8a..62e19e6 100644 +--- a/arch/arm/mach-at91/board-rm9200ek.c ++++ b/arch/arm/mach-at91/board-rm9200ek.c +@@ -40,6 +40,7 @@ + + #include + #include ++#include + #include + #include + +@@ -190,6 +191,7 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") + /* Maintainer: SAN People/Atmel */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c +index 24ab9be..c3b43ae 100644 +--- a/arch/arm/mach-at91/board-rsi-ews.c ++++ b/arch/arm/mach-at91/board-rsi-ews.c +@@ -26,6 +26,7 @@ + + #include + #include ++#include + + #include + +@@ -225,6 +226,7 @@ MACHINE_START(RSI_EWS, "RSI EWS") + /* Maintainer: Josef Holzmayr */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = rsi_ews_init_early, + .init_irq = at91_init_irq_default, + .init_machine = rsi_ews_board_init, +diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c +index cdd21f2..7bf6da7 100644 +--- a/arch/arm/mach-at91/board-sam9-l9260.c ++++ b/arch/arm/mach-at91/board-sam9-l9260.c +@@ -38,6 +38,7 @@ + #include + + #include ++#include + #include + + #include "sam9_smc.h" +@@ -202,6 +203,7 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") + /* Maintainer: Olimex */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c +index 7b3c391..889c1bf 100644 +--- a/arch/arm/mach-at91/board-sam9260ek.c ++++ b/arch/arm/mach-at91/board-sam9260ek.c +@@ -42,6 +42,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -344,6 +345,7 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c +index 2736453..2269be5 100644 +--- a/arch/arm/mach-at91/board-sam9261ek.c ++++ b/arch/arm/mach-at91/board-sam9261ek.c +@@ -46,6 +46,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -615,6 +616,7 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c +index 983cb98..82adf58 100644 +--- a/arch/arm/mach-at91/board-sam9263ek.c ++++ b/arch/arm/mach-at91/board-sam9263ek.c +@@ -45,6 +45,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -443,6 +444,7 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c +index 3d61553..da6d019 100644 +--- a/arch/arm/mach-at91/board-sam9g20ek.c ++++ b/arch/arm/mach-at91/board-sam9g20ek.c +@@ -42,6 +42,7 @@ + #include + + #include ++#include + #include + #include + +@@ -399,6 +400,7 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +@@ -408,6 +410,7 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c +index 9a87f0b..d1882d5 100644 +--- a/arch/arm/mach-at91/board-sam9m10g45ek.c ++++ b/arch/arm/mach-at91/board-sam9m10g45ek.c +@@ -41,6 +41,7 @@ + #include + + #include ++#include + #include + #include + #include +@@ -491,6 +492,7 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c +index be3239f..e7dc3ea 100644 +--- a/arch/arm/mach-at91/board-sam9rlek.c ++++ b/arch/arm/mach-at91/board-sam9rlek.c +@@ -31,6 +31,7 @@ + + #include + #include ++#include + #include + #include + +@@ -319,6 +320,7 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") + /* Maintainer: Atmel */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c +index 9d446f1..a4e031a 100644 +--- a/arch/arm/mach-at91/board-snapper9260.c ++++ b/arch/arm/mach-at91/board-snapper9260.c +@@ -33,6 +33,7 @@ + + #include + #include ++#include + #include + + #include "sam9_smc.h" +@@ -178,6 +179,7 @@ static void __init snapper9260_board_init(void) + MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = snapper9260_init_early, + .init_irq = at91_init_irq_default, + .init_machine = snapper9260_board_init, +diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c +index ee86f9d..29eae16 100644 +--- a/arch/arm/mach-at91/board-stamp9g20.c ++++ b/arch/arm/mach-at91/board-stamp9g20.c +@@ -26,6 +26,7 @@ + #include + + #include ++#include + #include + + #include "sam9_smc.h" +@@ -287,6 +288,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20") + /* Maintainer: taskit GmbH */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = stamp9g20_init_early, + .init_irq = at91_init_irq_default, + .init_machine = portuxg20_board_init, +@@ -296,6 +298,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20") + /* Maintainer: taskit GmbH */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = stamp9g20_init_early, + .init_irq = at91_init_irq_default, + .init_machine = stamp9g20evb_board_init, +diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c +index 95393fc..c1476b9 100644 +--- a/arch/arm/mach-at91/board-usb-a926x.c ++++ b/arch/arm/mach-at91/board-usb-a926x.c +@@ -42,6 +42,7 @@ + + #include + #include ++#include + #include + #include + +@@ -358,6 +359,7 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263") + /* Maintainer: calao-systems */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +@@ -367,6 +369,7 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260") + /* Maintainer: calao-systems */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +@@ -376,6 +379,7 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0") + /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ + .timer = &at91sam926x_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c +index d56665e..516d340 100644 +--- a/arch/arm/mach-at91/board-yl-9200.c ++++ b/arch/arm/mach-at91/board-yl-9200.c +@@ -44,6 +44,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -590,6 +591,7 @@ MACHINE_START(YL9200, "uCdragon YL-9200") + /* Maintainer: S.Birtles */ + .timer = &at91rm9200_timer, + .map_io = at91_map_io, ++ .handle_irq = at91_aic_handle_irq, + .init_early = yl9200_init_early, + .init_irq = at91_init_irq_default, + .init_machine = yl9200_board_init, +diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h +index 3af7272..7867378 100644 +--- a/arch/arm/mach-at91/include/mach/at91_aic.h ++++ b/arch/arm/mach-at91/include/mach/at91_aic.h +@@ -65,4 +65,6 @@ extern void __iomem *at91_aic_base; + #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ + #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ + ++void at91_aic_handle_irq(struct pt_regs *regs); ++ + #endif +diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S +deleted file mode 100644 +index 903bf20..0000000 +--- a/arch/arm/mach-at91/include/mach/entry-macro.S ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* +- * arch/arm/mach-at91/include/mach/entry-macro.S +- * +- * Copyright (C) 2003-2005 SAN People +- * +- * Low-level IRQ helper macros for AT91RM9200 platforms +- * +- * This file is licensed under the terms of the GNU General Public +- * License version 2. This program is licensed "as is" without any +- * warranty of any kind, whether express or implied. +- */ +- +-#include +-#include +- +- .macro get_irqnr_preamble, base, tmp +- ldr \base, =at91_aic_base @ base virtual address of AIC peripheral +- ldr \base, [\base] +- .endm +- +- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +- ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) +- ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number +- teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt +- streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. +- .endm +- +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index db8e141..390d4df 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -36,6 +36,7 @@ + #include + #include + ++#include + #include + #include + #include +@@ -45,6 +46,24 @@ static struct irq_domain *at91_aic_domain; + static struct device_node *at91_aic_np; + static unsigned int *at91_aic_irq_priorities; + ++asmlinkage void __exception_irq_entry at91_aic_handle_irq(struct pt_regs *regs) ++{ ++ u32 irqnr; ++ u32 irqstat; ++ ++ irqnr = at91_aic_read(AT91_AIC_IVR); ++ irqstat = at91_aic_read(AT91_AIC_ISR); ++ ++ /* ++ * ISR value is 0 when there is no current interrupt or when there is ++ * a spurious interrupt ++ */ ++ if (!irqstat) ++ at91_aic_write(AT91_AIC_EOICR, 0); ++ else ++ handle_IRQ(irqnr, regs); ++} ++ + static void at91_aic_mask_irq(struct irq_data *d) + { + /* Disable interrupt on AIC */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0058-ARM-at91-sparse-irq-support.patch b/patches.at91/0058-ARM-at91-sparse-irq-support.patch new file mode 100644 index 000000000000..0947785f2886 --- /dev/null +++ b/patches.at91/0058-ARM-at91-sparse-irq-support.patch @@ -0,0 +1,1578 @@ +From 6fdddfc0d9b97a191bf49bb1b180822f156c515c Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Thu, 21 Jun 2012 14:47:27 +0200 +Subject: ARM: at91: sparse irq support + +Enable sparse irq support for multisoc image. It involves to add the +NR_IRQS_LEGACY offset to static SoC irq number definitions since NR_IRQS_LEGACY +irq descs are allocated before AIC requests irq descs allocation. +Move NR_AIC_IRQS macro to a more appropiate place with the purpose to +remove mach/irqs.h later. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Nicolas Ferre + +Conflicts: + arch/arm/mach-at91/at91sam9260_devices.c + arch/arm/mach-at91/at91sam9g45_devices.c +--- + arch/arm/mach-at91/Kconfig | 1 + + arch/arm/mach-at91/at91rm9200.c | 1 + + arch/arm/mach-at91/at91rm9200_devices.c | 84 +++++++++++------------ + arch/arm/mach-at91/at91sam9260.c | 1 + + arch/arm/mach-at91/at91sam9260_devices.c | 88 ++++++++++++------------ + arch/arm/mach-at91/at91sam9261.c | 1 + + arch/arm/mach-at91/at91sam9261_devices.c | 68 +++++++++---------- + arch/arm/mach-at91/at91sam9263.c | 1 + + arch/arm/mach-at91/at91sam9263_devices.c | 80 +++++++++++----------- + arch/arm/mach-at91/at91sam926x_time.c | 2 +- + arch/arm/mach-at91/at91sam9g45.c | 1 + + arch/arm/mach-at91/at91sam9g45_devices.c | 104 ++++++++++++++--------------- + arch/arm/mach-at91/at91sam9rl.c | 1 + + arch/arm/mach-at91/at91sam9rl_devices.c | 76 ++++++++++----------- + arch/arm/mach-at91/at91x40.c | 1 + + arch/arm/mach-at91/include/mach/at91_aic.h | 3 + + arch/arm/mach-at91/include/mach/irqs.h | 12 ---- + arch/arm/mach-at91/irq.c | 6 +- + arch/arm/mach-at91/pm.c | 1 + + 19 files changed, 267 insertions(+), 265 deletions(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index e401dea..7d0c40a 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -30,6 +30,7 @@ config SOC_AT91SAM9 + bool + select CPU_ARM926T + select MULTI_IRQ_HANDLER ++ select SPARSE_IRQ + select AT91_SAM9_TIME + select AT91_SAM9_SMC + +diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c +index d50da1a..801c30b 100644 +--- a/arch/arm/mach-at91/at91rm9200.c ++++ b/arch/arm/mach-at91/at91rm9200.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c +index 99affb5..04d69d3 100644 +--- a/arch/arm/mach-at91/at91rm9200_devices.c ++++ b/arch/arm/mach-at91/at91rm9200_devices.c +@@ -41,8 +41,8 @@ static struct resource usbh_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_UHP, +- .end = AT91RM9200_ID_UHP, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -94,8 +94,8 @@ static struct resource udc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_UDP, +- .end = AT91RM9200_ID_UDP, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -145,8 +145,8 @@ static struct resource eth_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_EMAC, +- .end = AT91RM9200_ID_EMAC, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_MCI, +- .end = AT91RM9200_ID_MCI, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -488,8 +488,8 @@ static struct resource twi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_TWI, +- .end = AT91RM9200_ID_TWI, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -532,8 +532,8 @@ static struct resource spi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_SPI, +- .end = AT91RM9200_ID_SPI, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -598,18 +598,18 @@ static struct resource tcb0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_TC0, +- .end = AT91RM9200_ID_TC0, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0, + .flags = IORESOURCE_IRQ, + }, + [2] = { +- .start = AT91RM9200_ID_TC1, +- .end = AT91RM9200_ID_TC1, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1, + .flags = IORESOURCE_IRQ, + }, + [3] = { +- .start = AT91RM9200_ID_TC2, +- .end = AT91RM9200_ID_TC2, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -628,18 +628,18 @@ static struct resource tcb1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_TC3, +- .end = AT91RM9200_ID_TC3, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3, + .flags = IORESOURCE_IRQ, + }, + [2] = { +- .start = AT91RM9200_ID_TC4, +- .end = AT91RM9200_ID_TC4, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4, + .flags = IORESOURCE_IRQ, + }, + [3] = { +- .start = AT91RM9200_ID_TC5, +- .end = AT91RM9200_ID_TC5, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -673,8 +673,8 @@ static struct resource rtc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -729,8 +729,8 @@ static struct resource ssc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_SSC0, +- .end = AT91RM9200_ID_SSC0, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -771,8 +771,8 @@ static struct resource ssc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_SSC1, +- .end = AT91RM9200_ID_SSC1, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -813,8 +813,8 @@ static struct resource ssc2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_SSC2, +- .end = AT91RM9200_ID_SSC2, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -897,8 +897,8 @@ static struct resource dbgu_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -935,8 +935,8 @@ static struct resource uart0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_US0, +- .end = AT91RM9200_ID_US0, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -984,8 +984,8 @@ static struct resource uart1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_US1, +- .end = AT91RM9200_ID_US1, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1035,8 +1035,8 @@ static struct resource uart2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_US2, +- .end = AT91RM9200_ID_US2, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1078,8 +1078,8 @@ static struct resource uart3_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91RM9200_ID_US3, +- .end = AT91RM9200_ID_US3, ++ .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3, ++ .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3, + .flags = IORESOURCE_IRQ, + }, + }; +diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c +index a27bbec..c644131 100644 +--- a/arch/arm/mach-at91/at91sam9260.c ++++ b/arch/arm/mach-at91/at91sam9260.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + +diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c +index d556de1..43e60fb 100644 +--- a/arch/arm/mach-at91/at91sam9260_devices.c ++++ b/arch/arm/mach-at91/at91sam9260_devices.c +@@ -42,8 +42,8 @@ static struct resource usbh_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_UHP, +- .end = AT91SAM9260_ID_UHP, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -95,8 +95,8 @@ static struct resource udc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_UDP, +- .end = AT91SAM9260_ID_UDP, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -146,8 +146,8 @@ static struct resource eth_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_EMAC, +- .end = AT91SAM9260_ID_EMAC, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -220,8 +220,8 @@ static struct resource mmc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_MCI, +- .end = AT91SAM9260_ID_MCI, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -302,8 +302,8 @@ static struct resource mmc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_MCI, +- .end = AT91SAM9260_ID_MCI, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -493,8 +493,8 @@ static struct resource twi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_TWI, +- .end = AT91SAM9260_ID_TWI, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -537,8 +537,8 @@ static struct resource spi0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_SPI0, +- .end = AT91SAM9260_ID_SPI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -563,8 +563,8 @@ static struct resource spi1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_SPI1, +- .end = AT91SAM9260_ID_SPI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -649,18 +649,18 @@ static struct resource tcb0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_TC0, +- .end = AT91SAM9260_ID_TC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0, + .flags = IORESOURCE_IRQ, + }, + [2] = { +- .start = AT91SAM9260_ID_TC1, +- .end = AT91SAM9260_ID_TC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1, + .flags = IORESOURCE_IRQ, + }, + [3] = { +- .start = AT91SAM9260_ID_TC2, +- .end = AT91SAM9260_ID_TC2, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -679,18 +679,18 @@ static struct resource tcb1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_TC3, +- .end = AT91SAM9260_ID_TC3, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3, + .flags = IORESOURCE_IRQ, + }, + [2] = { +- .start = AT91SAM9260_ID_TC4, +- .end = AT91SAM9260_ID_TC4, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4, + .flags = IORESOURCE_IRQ, + }, + [3] = { +- .start = AT91SAM9260_ID_TC5, +- .end = AT91SAM9260_ID_TC5, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -804,8 +804,8 @@ static struct resource ssc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_SSC, +- .end = AT91SAM9260_ID_SSC, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -879,8 +879,8 @@ static struct resource dbgu_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -917,8 +917,8 @@ static struct resource uart0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_US0, +- .end = AT91SAM9260_ID_US0, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US0, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -968,8 +968,8 @@ static struct resource uart1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_US1, +- .end = AT91SAM9260_ID_US1, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US1, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1011,8 +1011,8 @@ static struct resource uart2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_US2, +- .end = AT91SAM9260_ID_US2, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US2, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1054,8 +1054,8 @@ static struct resource uart3_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_US3, +- .end = AT91SAM9260_ID_US3, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US3, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US3, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1097,8 +1097,8 @@ static struct resource uart4_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_US4, +- .end = AT91SAM9260_ID_US4, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US4, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US4, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1135,8 +1135,8 @@ static struct resource uart5_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9260_ID_US5, +- .end = AT91SAM9260_ID_US5, ++ .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US5, ++ .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US5, + .flags = IORESOURCE_IRQ, + }, + }; +diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c +index c77d503..f40762c 100644 +--- a/arch/arm/mach-at91/at91sam9261.c ++++ b/arch/arm/mach-at91/at91sam9261.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + +diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c +index 9295e90..8df5c1b 100644 +--- a/arch/arm/mach-at91/at91sam9261_devices.c ++++ b/arch/arm/mach-at91/at91sam9261_devices.c +@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_UHP, +- .end = AT91SAM9261_ID_UHP, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -98,8 +98,8 @@ static struct resource udc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_UDP, +- .end = AT91SAM9261_ID_UDP, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -148,8 +148,8 @@ static struct resource mmc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_MCI, +- .end = AT91SAM9261_ID_MCI, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -310,8 +310,8 @@ static struct resource twi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_TWI, +- .end = AT91SAM9261_ID_TWI, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -354,8 +354,8 @@ static struct resource spi0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_SPI0, +- .end = AT91SAM9261_ID_SPI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -380,8 +380,8 @@ static struct resource spi1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_SPI1, +- .end = AT91SAM9261_ID_SPI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -468,8 +468,8 @@ static struct resource lcdc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_LCDC, +- .end = AT91SAM9261_ID_LCDC, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC, + .flags = IORESOURCE_IRQ, + }, + #if defined(CONFIG_FB_INTSRAM) +@@ -566,18 +566,18 @@ static struct resource tcb_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_TC0, +- .end = AT91SAM9261_ID_TC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0, + .flags = IORESOURCE_IRQ, + }, + [2] = { +- .start = AT91SAM9261_ID_TC1, +- .end = AT91SAM9261_ID_TC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1, + .flags = IORESOURCE_IRQ, + }, + [3] = { +- .start = AT91SAM9261_ID_TC2, +- .end = AT91SAM9261_ID_TC2, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -689,8 +689,8 @@ static struct resource ssc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_SSC0, +- .end = AT91SAM9261_ID_SSC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -731,8 +731,8 @@ static struct resource ssc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_SSC1, +- .end = AT91SAM9261_ID_SSC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -773,8 +773,8 @@ static struct resource ssc2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_SSC2, +- .end = AT91SAM9261_ID_SSC2, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -857,8 +857,8 @@ static struct resource dbgu_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -895,8 +895,8 @@ static struct resource uart0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_US0, +- .end = AT91SAM9261_ID_US0, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -938,8 +938,8 @@ static struct resource uart1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_US1, +- .end = AT91SAM9261_ID_US1, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -981,8 +981,8 @@ static struct resource uart2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9261_ID_US2, +- .end = AT91SAM9261_ID_US2, ++ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2, ++ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2, + .flags = IORESOURCE_IRQ, + }, + }; +diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c +index ed91c7e..84b3810 100644 +--- a/arch/arm/mach-at91/at91sam9263.c ++++ b/arch/arm/mach-at91/at91sam9263.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include + #include + +diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c +index 175e000..eb6bbf8 100644 +--- a/arch/arm/mach-at91/at91sam9263_devices.c ++++ b/arch/arm/mach-at91/at91sam9263_devices.c +@@ -44,8 +44,8 @@ static struct resource usbh_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_UHP, +- .end = AT91SAM9263_ID_UHP, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -104,8 +104,8 @@ static struct resource udc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_UDP, +- .end = AT91SAM9263_ID_UDP, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -155,8 +155,8 @@ static struct resource eth_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_EMAC, +- .end = AT91SAM9263_ID_EMAC, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -229,8 +229,8 @@ static struct resource mmc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_MCI0, +- .end = AT91SAM9263_ID_MCI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -254,8 +254,8 @@ static struct resource mmc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_MCI1, +- .end = AT91SAM9263_ID_MCI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -567,8 +567,8 @@ static struct resource twi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_TWI, +- .end = AT91SAM9263_ID_TWI, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -611,8 +611,8 @@ static struct resource spi0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_SPI0, +- .end = AT91SAM9263_ID_SPI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -637,8 +637,8 @@ static struct resource spi1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_SPI1, +- .end = AT91SAM9263_ID_SPI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_AC97C, +- .end = AT91SAM9263_ID_AC97C, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -776,8 +776,8 @@ static struct resource can_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_CAN, +- .end = AT91SAM9263_ID_CAN, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -816,8 +816,8 @@ static struct resource lcdc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_LCDC, +- .end = AT91SAM9263_ID_LCDC, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -883,8 +883,8 @@ struct resource isi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_ISI, +- .end = AT91SAM9263_ID_ISI, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -940,8 +940,8 @@ static struct resource tcb_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_TCB, +- .end = AT91SAM9263_ID_TCB, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1108,8 +1108,8 @@ static struct resource pwm_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_PWMC, +- .end = AT91SAM9263_ID_PWMC, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1161,8 +1161,8 @@ static struct resource ssc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_SSC0, +- .end = AT91SAM9263_ID_SSC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1203,8 +1203,8 @@ static struct resource ssc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_SSC1, +- .end = AT91SAM9263_ID_SSC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1284,8 +1284,8 @@ static struct resource dbgu_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1322,8 +1322,8 @@ static struct resource uart0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_US0, +- .end = AT91SAM9263_ID_US0, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US0, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1365,8 +1365,8 @@ static struct resource uart1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_US1, +- .end = AT91SAM9263_ID_US1, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US1, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1408,8 +1408,8 @@ static struct resource uart2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9263_ID_US2, +- .end = AT91SAM9263_ID_US2, ++ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US2, ++ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US2, + .flags = IORESOURCE_IRQ, + }, + }; +diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c +index a94758b..ffc0957 100644 +--- a/arch/arm/mach-at91/at91sam926x_time.c ++++ b/arch/arm/mach-at91/at91sam926x_time.c +@@ -137,7 +137,7 @@ static struct irqaction at91sam926x_pit_irq = { + .name = "at91_tick", + .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = at91sam926x_pit_interrupt, +- .irq = AT91_ID_SYS, ++ .irq = NR_IRQS_LEGACY + AT91_ID_SYS, + }; + + static void at91sam926x_pit_reset(void) +diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c +index f205449..55d2959 100644 +--- a/arch/arm/mach-at91/at91sam9g45.c ++++ b/arch/arm/mach-at91/at91sam9g45.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include + #include + +diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c +index 35bd42d..7a3f0b3 100644 +--- a/arch/arm/mach-at91/at91sam9g45_devices.c ++++ b/arch/arm/mach-at91/at91sam9g45_devices.c +@@ -50,8 +50,8 @@ static struct resource hdmac_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_DMA, +- .end = AT91SAM9G45_ID_DMA, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -91,8 +91,8 @@ static struct resource usbh_ohci_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_UHPHS, +- .end = AT91SAM9G45_ID_UHPHS, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -153,8 +153,8 @@ static struct resource usbh_ehci_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_UHPHS, +- .end = AT91SAM9G45_ID_UHPHS, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -210,8 +210,8 @@ static struct resource usba_udc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [2] = { +- .start = AT91SAM9G45_ID_UDPHS, +- .end = AT91SAM9G45_ID_UDPHS, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -293,8 +293,8 @@ static struct resource eth_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_EMAC, +- .end = AT91SAM9G45_ID_EMAC, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -367,8 +367,8 @@ static struct resource mmc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_MCI0, +- .end = AT91SAM9G45_ID_MCI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -392,8 +392,8 @@ static struct resource mmc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_MCI1, +- .end = AT91SAM9G45_ID_MCI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -643,8 +643,8 @@ static struct resource twi0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_TWI0, +- .end = AT91SAM9G45_ID_TWI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -663,8 +663,8 @@ static struct resource twi1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_TWI1, +- .end = AT91SAM9G45_ID_TWI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -718,8 +718,8 @@ static struct resource spi0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_SPI0, +- .end = AT91SAM9G45_ID_SPI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -744,8 +744,8 @@ static struct resource spi1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_SPI1, +- .end = AT91SAM9G45_ID_SPI1, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -832,8 +832,8 @@ static struct resource ac97_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_AC97C, +- .end = AT91SAM9G45_ID_AC97C, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -885,8 +885,8 @@ struct resource isi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_ISI, +- .end = AT91SAM9G45_ID_ISI, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -977,8 +977,8 @@ static struct resource lcdc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_LCDC, +- .end = AT91SAM9G45_ID_LCDC, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1052,8 +1052,8 @@ static struct resource tcb0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_TCB, +- .end = AT91SAM9G45_ID_TCB, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1073,8 +1073,8 @@ static struct resource tcb1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_TCB, +- .end = AT91SAM9G45_ID_TCB, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1108,8 +1108,8 @@ static struct resource rtc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1145,8 +1145,8 @@ static struct resource tsadcc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_TSC, +- .end = AT91SAM9G45_ID_TSC, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, + .flags = IORESOURCE_IRQ, + } + }; +@@ -1300,8 +1300,8 @@ static struct resource pwm_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_PWMC, +- .end = AT91SAM9G45_ID_PWMC, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1353,8 +1353,8 @@ static struct resource ssc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_SSC0, +- .end = AT91SAM9G45_ID_SSC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1395,8 +1395,8 @@ static struct resource ssc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_SSC1, +- .end = AT91SAM9G45_ID_SSC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1475,8 +1475,8 @@ static struct resource dbgu_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1513,8 +1513,8 @@ static struct resource uart0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_US0, +- .end = AT91SAM9G45_ID_US0, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1556,8 +1556,8 @@ static struct resource uart1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_US1, +- .end = AT91SAM9G45_ID_US1, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1599,8 +1599,8 @@ static struct resource uart2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_US2, +- .end = AT91SAM9G45_ID_US2, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1642,8 +1642,8 @@ static struct resource uart3_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9G45_ID_US3, +- .end = AT91SAM9G45_ID_US3, ++ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3, ++ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3, + .flags = IORESOURCE_IRQ, + }, + }; +diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c +index e420085..72ce50a 100644 +--- a/arch/arm/mach-at91/at91sam9rl.c ++++ b/arch/arm/mach-at91/at91sam9rl.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + +diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c +index 9c0b148..f09fff9 100644 +--- a/arch/arm/mach-at91/at91sam9rl_devices.c ++++ b/arch/arm/mach-at91/at91sam9rl_devices.c +@@ -41,8 +41,8 @@ static struct resource hdmac_resources[] = { + .flags = IORESOURCE_MEM, + }, + [2] = { +- .start = AT91SAM9RL_ID_DMA, +- .end = AT91SAM9RL_ID_DMA, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -84,8 +84,8 @@ static struct resource usba_udc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [2] = { +- .start = AT91SAM9RL_ID_UDPHS, +- .end = AT91SAM9RL_ID_UDPHS, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -172,8 +172,8 @@ static struct resource mmc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_MCI, +- .end = AT91SAM9RL_ID_MCI, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -339,8 +339,8 @@ static struct resource twi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_TWI0, +- .end = AT91SAM9RL_ID_TWI0, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -383,8 +383,8 @@ static struct resource spi_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_SPI, +- .end = AT91SAM9RL_ID_SPI, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -452,8 +452,8 @@ static struct resource ac97_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_AC97C, +- .end = AT91SAM9RL_ID_AC97C, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -507,8 +507,8 @@ static struct resource lcdc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_LCDC, +- .end = AT91SAM9RL_ID_LCDC, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -574,18 +574,18 @@ static struct resource tcb_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_TC0, +- .end = AT91SAM9RL_ID_TC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, + .flags = IORESOURCE_IRQ, + }, + [2] = { +- .start = AT91SAM9RL_ID_TC1, +- .end = AT91SAM9RL_ID_TC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, + .flags = IORESOURCE_IRQ, + }, + [3] = { +- .start = AT91SAM9RL_ID_TC2, +- .end = AT91SAM9RL_ID_TC2, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -621,8 +621,8 @@ static struct resource tsadcc_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_TSC, +- .end = AT91SAM9RL_ID_TSC, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, + .flags = IORESOURCE_IRQ, + } + }; +@@ -768,8 +768,8 @@ static struct resource pwm_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_PWMC, +- .end = AT91SAM9RL_ID_PWMC, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -821,8 +821,8 @@ static struct resource ssc0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_SSC0, +- .end = AT91SAM9RL_ID_SSC0, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -863,8 +863,8 @@ static struct resource ssc1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_SSC1, +- .end = AT91SAM9RL_ID_SSC1, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -943,8 +943,8 @@ static struct resource dbgu_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91_ID_SYS, +- .end = AT91_ID_SYS, ++ .start = NR_IRQS_LEGACY + AT91_ID_SYS, ++ .end = NR_IRQS_LEGACY + AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -981,8 +981,8 @@ static struct resource uart0_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_US0, +- .end = AT91SAM9RL_ID_US0, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1032,8 +1032,8 @@ static struct resource uart1_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_US1, +- .end = AT91SAM9RL_ID_US1, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1075,8 +1075,8 @@ static struct resource uart2_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_US2, +- .end = AT91SAM9RL_ID_US2, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, + .flags = IORESOURCE_IRQ, + }, + }; +@@ -1118,8 +1118,8 @@ static struct resource uart3_resources[] = { + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = AT91SAM9RL_ID_US3, +- .end = AT91SAM9RL_ID_US3, ++ .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, ++ .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, + .flags = IORESOURCE_IRQ, + }, + }; +diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c +index d62fe09..4c0f5fd 100644 +--- a/arch/arm/mach-at91/at91x40.c ++++ b/arch/arm/mach-at91/at91x40.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include "generic.h" +diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h +index 7867378..fd42a85 100644 +--- a/arch/arm/mach-at91/include/mach/at91_aic.h ++++ b/arch/arm/mach-at91/include/mach/at91_aic.h +@@ -28,6 +28,9 @@ extern void __iomem *at91_aic_base; + .extern at91_aic_base + #endif + ++/* Number of irq lines managed by AIC */ ++#define NR_AIC_IRQS 32 ++ + #define AT91_AIC_IRQ_MIN_PRIORITY 0 + #define AT91_AIC_IRQ_MAX_PRIORITY 7 + +diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h +index 2d510ee..cab60d5 100644 +--- a/arch/arm/mach-at91/include/mach/irqs.h ++++ b/arch/arm/mach-at91/include/mach/irqs.h +@@ -22,18 +22,6 @@ + #define __ASM_ARCH_IRQS_H + + #include +-#include +- +-#define NR_AIC_IRQS 32 +- +- +-/* +- * IRQ interrupt symbols are the AT91xxx_ID_* symbols +- * for IRQs handled directly through the AIC, or else the AT91_PIN_* +- * symbols in gpio.h for ones handled indirectly as GPIOs. +- * We make provision for 5 banks of GPIO. +- */ +-#define NR_IRQS (NR_AIC_IRQS + (5 * 32)) + + /* FIQ is AIC source 0. */ + #define FIQ_START AT91_ID_FIQ +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index 390d4df..75ca2f4 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -41,6 +41,8 @@ + #include + #include + ++#include ++ + void __iomem *at91_aic_base; + static struct irq_domain *at91_aic_domain; + static struct device_node *at91_aic_np; +@@ -302,11 +304,11 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) + */ + for (i = 0; i < NR_AIC_IRQS; i++) { + /* Put hardware irq number in Source Vector Register: */ +- at91_aic_write(AT91_AIC_SVR(i), i); ++ at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i); + /* Active Low interrupt, with the specified priority */ + at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); + +- irq_set_chip_and_handler(i, &at91_aic_chip, handle_fasteoi_irq); ++ irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index 1bfaad6..2c2d865 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -25,6 +25,7 @@ + #include + #include + ++#include + #include + #include + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0059-ARM-at91-remove-mach-irqs.h.patch b/patches.at91/0059-ARM-at91-remove-mach-irqs.h.patch new file mode 100644 index 000000000000..17aa40e9ef30 --- /dev/null +++ b/patches.at91/0059-ARM-at91-remove-mach-irqs.h.patch @@ -0,0 +1,53 @@ +From 45fba6f03c7b2ec9fd1b0d37715c6e8b9ebb3a4d Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Thu, 14 Jun 2012 15:41:04 +0200 +Subject: ARM: at91: remove mach/irqs.h + +mach/irqs only defines FIQ_START which doesn't appear to be used anywhere +so remove it. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/include/mach/irqs.h | 29 ----------------------------- + 1 file changed, 29 deletions(-) + delete mode 100644 arch/arm/mach-at91/include/mach/irqs.h + +diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h +deleted file mode 100644 +index cab60d5..0000000 +--- a/arch/arm/mach-at91/include/mach/irqs.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-/* +- * arch/arm/mach-at91/include/mach/irqs.h +- * +- * Copyright (C) 2004 SAN People +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-#ifndef __ASM_ARCH_IRQS_H +-#define __ASM_ARCH_IRQS_H +- +-#include +- +-/* FIQ is AIC source 0. */ +-#define FIQ_START AT91_ID_FIQ +- +-#endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0060-ARM-at91-add-AIC5-support.patch b/patches.at91/0060-ARM-at91-add-AIC5-support.patch new file mode 100644 index 000000000000..feaacd1db0f4 --- /dev/null +++ b/patches.at91/0060-ARM-at91-add-AIC5-support.patch @@ -0,0 +1,606 @@ +From 2ab4fd505a722e59d1a7b02d4b8fe5a89bc2f761 Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Wed, 30 May 2012 10:01:09 +0200 +Subject: ARM: at91: add AIC5 support + +The number of lines of AIC5 has increased from 32 to 128. Due to this +increase, a source select register has been introduced for the interrupt +line selection. Moreover, register mapping has been changed. For that reasons, +we need some dedicated callbacks for AIC5. +Power management is also concerned by these changes. On suspend, we can't get +the whole interrupt mask register as before, we have to read this register 128 +times. To reduce this overhead, a snapshot of the whole IMR is maintained. + +Signed-off-by: Ludovic Desroches +Signed-off-by: Nicolas Ferre +--- + arch/arm/mach-at91/generic.h | 2 + + arch/arm/mach-at91/include/mach/at91_aic.h | 26 +++ + arch/arm/mach-at91/irq.c | 343 ++++++++++++++++++++++++----- + 3 files changed, 314 insertions(+), 57 deletions(-) + +diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h +index 0a60bf8..f496506 100644 +--- a/arch/arm/mach-at91/generic.h ++++ b/arch/arm/mach-at91/generic.h +@@ -29,6 +29,8 @@ extern void __init at91x40_init_interrupts(unsigned int priority[]); + extern void __init at91_aic_init(unsigned int priority[]); + extern int __init at91_aic_of_init(struct device_node *node, + struct device_node *parent); ++extern int __init at91_aic5_of_init(struct device_node *node, ++ struct device_node *parent); + + + /* Timer */ +diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h +index fd42a85..eaea661 100644 +--- a/arch/arm/mach-at91/include/mach/at91_aic.h ++++ b/arch/arm/mach-at91/include/mach/at91_aic.h +@@ -30,11 +30,16 @@ extern void __iomem *at91_aic_base; + + /* Number of irq lines managed by AIC */ + #define NR_AIC_IRQS 32 ++#define NR_AIC5_IRQS 128 ++ ++#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */ ++#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */ + + #define AT91_AIC_IRQ_MIN_PRIORITY 0 + #define AT91_AIC_IRQ_MAX_PRIORITY 7 + + #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ ++#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */ + #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ + #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ + #define AT91_AIC_SRCTYPE_LOW (0 << 5) +@@ -43,31 +48,52 @@ extern void __iomem *at91_aic_base; + #define AT91_AIC_SRCTYPE_RISING (3 << 5) + + #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ ++#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */ + #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ ++#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */ + #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ ++#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */ + #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ ++#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */ + #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ + + #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ ++#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */ ++#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */ ++#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */ ++#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */ + #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ ++#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */ + #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ ++#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */ + #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ + #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ + + #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ ++#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */ + #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ ++#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */ + #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ ++#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */ + #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ ++#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */ + #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ ++#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */ + #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ ++#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */ + #define AT91_AIC_DCR 0x138 /* Debug Control Register */ ++#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */ + #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ + #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ + + #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ ++#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */ + #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ ++#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */ + #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ ++#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */ + + void at91_aic_handle_irq(struct pt_regs *regs); ++void at91_aic5_handle_irq(struct pt_regs *regs); + + #endif +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index 75ca2f4..c5eaaa0 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -46,9 +47,116 @@ + void __iomem *at91_aic_base; + static struct irq_domain *at91_aic_domain; + static struct device_node *at91_aic_np; ++static unsigned int n_irqs = NR_AIC_IRQS; ++static unsigned long at91_aic_caps = 0; + static unsigned int *at91_aic_irq_priorities; + +-asmlinkage void __exception_irq_entry at91_aic_handle_irq(struct pt_regs *regs) ++/* AIC5 introduces a Source Select Register */ ++#define AT91_AIC_CAP_AIC5 (1 << 0) ++#define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5) ++ ++#ifdef CONFIG_PM ++ ++static unsigned long *wakeups; ++static unsigned long *backups; ++ ++#define set_backup(bit) set_bit(bit, backups) ++#define clear_backup(bit) clear_bit(bit, backups) ++ ++static int at91_aic_pm_init(void) ++{ ++ backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL); ++ if (!backups) ++ return -ENOMEM; ++ ++ wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL); ++ if (!wakeups) { ++ kfree(backups); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int at91_aic_set_wake(struct irq_data *d, unsigned value) ++{ ++ if (unlikely(d->hwirq >= n_irqs)) ++ return -EINVAL; ++ ++ if (value) ++ set_bit(d->hwirq, wakeups); ++ else ++ clear_bit(d->hwirq, wakeups); ++ ++ return 0; ++} ++ ++void at91_irq_suspend(void) ++{ ++ int i = 0, bit; ++ ++ if (has_aic5()) { ++ /* disable enabled irqs */ ++ while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { ++ at91_aic_write(AT91_AIC5_SSR, ++ bit & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IDCR, 1); ++ i = bit; ++ } ++ /* enable wakeup irqs */ ++ i = 0; ++ while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { ++ at91_aic_write(AT91_AIC5_SSR, ++ bit & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IECR, 1); ++ i = bit; ++ } ++ } else { ++ at91_aic_write(AT91_AIC_IDCR, *backups); ++ at91_aic_write(AT91_AIC_IECR, *wakeups); ++ } ++} ++ ++void at91_irq_resume(void) ++{ ++ int i = 0, bit; ++ ++ if (has_aic5()) { ++ /* disable wakeup irqs */ ++ while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { ++ at91_aic_write(AT91_AIC5_SSR, ++ bit & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IDCR, 1); ++ i = bit; ++ } ++ /* enable irqs disabled for suspend */ ++ i = 0; ++ while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { ++ at91_aic_write(AT91_AIC5_SSR, ++ bit & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IECR, 1); ++ i = bit; ++ } ++ } else { ++ at91_aic_write(AT91_AIC_IDCR, *wakeups); ++ at91_aic_write(AT91_AIC_IECR, *backups); ++ } ++} ++ ++#else ++static inline int at91_aic_pm_init(void) ++{ ++ return 0; ++} ++ ++#define set_backup(bit) ++#define clear_backup(bit) ++#define at91_aic_set_wake NULL ++ ++#endif /* CONFIG_PM */ ++ ++asmlinkage void __exception_irq_entry ++at91_aic_handle_irq(struct pt_regs *regs) + { + u32 irqnr; + u32 irqstat; +@@ -66,16 +174,53 @@ asmlinkage void __exception_irq_entry at91_aic_handle_irq(struct pt_regs *regs) + handle_IRQ(irqnr, regs); + } + ++asmlinkage void __exception_irq_entry ++at91_aic5_handle_irq(struct pt_regs *regs) ++{ ++ u32 irqnr; ++ u32 irqstat; ++ ++ irqnr = at91_aic_read(AT91_AIC5_IVR); ++ irqstat = at91_aic_read(AT91_AIC5_ISR); ++ ++ if (!irqstat) ++ at91_aic_write(AT91_AIC5_EOICR, 0); ++ else ++ handle_IRQ(irqnr, regs); ++} ++ + static void at91_aic_mask_irq(struct irq_data *d) + { + /* Disable interrupt on AIC */ + at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq); ++ /* Update ISR cache */ ++ clear_backup(d->hwirq); ++} ++ ++static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d) ++{ ++ /* Disable interrupt on AIC5 */ ++ at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IDCR, 1); ++ /* Update ISR cache */ ++ clear_backup(d->hwirq); + } + + static void at91_aic_unmask_irq(struct irq_data *d) + { + /* Enable interrupt on AIC */ + at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq); ++ /* Update ISR cache */ ++ set_backup(d->hwirq); ++} ++ ++static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d) ++{ ++ /* Enable interrupt on AIC5 */ ++ at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IECR, 1); ++ /* Update ISR cache */ ++ set_backup(d->hwirq); + } + + static void at91_aic_eoi(struct irq_data *d) +@@ -87,13 +232,18 @@ static void at91_aic_eoi(struct irq_data *d) + at91_aic_write(AT91_AIC_EOICR, 0); + } + +-unsigned int at91_extern_irq; ++static void __maybe_unused at91_aic5_eoi(struct irq_data *d) ++{ ++ at91_aic_write(AT91_AIC5_EOICR, 0); ++} + +-#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq) ++unsigned long *at91_extern_irq; + +-static int at91_aic_set_type(struct irq_data *d, unsigned type) ++#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq) ++ ++static int at91_aic_compute_srctype(struct irq_data *d, unsigned type) + { +- unsigned int smr, srctype; ++ int srctype; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: +@@ -106,58 +256,44 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type) + if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ + srctype = AT91_AIC_SRCTYPE_LOW; + else +- return -EINVAL; ++ srctype = -EINVAL; + break; + case IRQ_TYPE_EDGE_FALLING: + if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ + srctype = AT91_AIC_SRCTYPE_FALLING; + else +- return -EINVAL; ++ srctype = -EINVAL; + break; + default: +- return -EINVAL; ++ srctype = -EINVAL; + } + +- smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE; +- at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype); +- return 0; ++ return srctype; + } + +-#ifdef CONFIG_PM +- +-static u32 wakeups; +-static u32 backups; +- +-static int at91_aic_set_wake(struct irq_data *d, unsigned value) ++static int at91_aic_set_type(struct irq_data *d, unsigned type) + { +- if (unlikely(d->hwirq >= NR_AIC_IRQS)) +- return -EINVAL; +- +- if (value) +- wakeups |= (1 << d->hwirq); +- else +- wakeups &= ~(1 << d->hwirq); ++ unsigned int smr; ++ int srctype; ++ ++ srctype = at91_aic_compute_srctype(d, type); ++ if (srctype < 0) ++ return srctype; ++ ++ if (has_aic5()) { ++ at91_aic_write(AT91_AIC5_SSR, ++ d->hwirq & AT91_AIC5_INTSEL_MSK); ++ smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE; ++ at91_aic_write(AT91_AIC5_SMR, smr | srctype); ++ } else { ++ smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) ++ & ~AT91_AIC_SRCTYPE; ++ at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype); ++ } + + return 0; + } + +-void at91_irq_suspend(void) +-{ +- backups = at91_aic_read(AT91_AIC_IMR); +- at91_aic_write(AT91_AIC_IDCR, backups); +- at91_aic_write(AT91_AIC_IECR, wakeups); +-} +- +-void at91_irq_resume(void) +-{ +- at91_aic_write(AT91_AIC_IDCR, wakeups); +- at91_aic_write(AT91_AIC_IECR, backups); +-} +- +-#else +-#define at91_aic_set_wake NULL +-#endif +- + static struct irq_chip at91_aic_chip = { + .name = "AIC", + .irq_mask = at91_aic_mask_irq, +@@ -193,6 +329,35 @@ static void __init at91_aic_hw_init(unsigned int spu_vector) + at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); + } + ++static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector) ++{ ++ int i; ++ ++ /* ++ * Perform 8 End Of Interrupt Command to make sure AIC ++ * will not Lock out nIRQ ++ */ ++ for (i = 0; i < 8; i++) ++ at91_aic_write(AT91_AIC5_EOICR, 0); ++ ++ /* ++ * Spurious Interrupt ID in Spurious Vector Register. ++ * When there is no current interrupt, the IRQ Vector Register ++ * reads the value stored in AIC_SPU ++ */ ++ at91_aic_write(AT91_AIC5_SPU, spu_vector); ++ ++ /* No debugging in AIC: Debug (Protect) Control Register */ ++ at91_aic_write(AT91_AIC5_DCR, 0); ++ ++ /* Disable and clear all interrupts initially */ ++ for (i = 0; i < n_irqs; i++) { ++ at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK); ++ at91_aic_write(AT91_AIC5_IDCR, 1); ++ at91_aic_write(AT91_AIC5_ICCR, 1); ++ } ++} ++ + #if defined(CONFIG_OF) + static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +@@ -210,13 +375,31 @@ static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, + return 0; + } + ++static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq, ++ irq_hw_number_t hw) ++{ ++ at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK); ++ ++ /* Put virq number in Source Vector Register */ ++ at91_aic_write(AT91_AIC5_SVR, virq); ++ ++ /* Active Low interrupt, with priority */ ++ at91_aic_write(AT91_AIC5_SMR, ++ AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]); ++ ++ irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); ++ set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); ++ ++ return 0; ++} ++ + static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, + const u32 *intspec, unsigned int intsize, + irq_hw_number_t *out_hwirq, unsigned int *out_type) + { + if (WARN_ON(intsize < 3)) + return -EINVAL; +- if (WARN_ON(intspec[0] >= NR_AIC_IRQS)) ++ if (WARN_ON(intspec[0] >= n_irqs)) + return -EINVAL; + if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) + || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY))) +@@ -234,14 +417,24 @@ static struct irq_domain_ops at91_aic_irq_ops = { + .xlate = at91_aic_irq_domain_xlate, + }; + +-int __init at91_aic_of_init(struct device_node *node, +- struct device_node *parent) ++int __init at91_aic_of_common_init(struct device_node *node, ++ struct device_node *parent) + { + struct property *prop; + const __be32 *p; + u32 val; + +- at91_aic_irq_priorities = kzalloc(NR_AIC_IRQS ++ at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs) ++ * sizeof(*at91_extern_irq), GFP_KERNEL); ++ if (!at91_extern_irq) ++ return -ENOMEM; ++ ++ if (at91_aic_pm_init()) { ++ kfree(at91_extern_irq); ++ return -ENOMEM; ++ } ++ ++ at91_aic_irq_priorities = kzalloc(n_irqs + * sizeof(*at91_aic_irq_priorities), + GFP_KERNEL); + if (!at91_aic_irq_priorities) +@@ -250,22 +443,56 @@ int __init at91_aic_of_init(struct device_node *node, + at91_aic_base = of_iomap(node, 0); + at91_aic_np = node; + +- at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS, ++ at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs, + &at91_aic_irq_ops, NULL); + if (!at91_aic_domain) + panic("Unable to add AIC irq domain (DT)\n"); + +- at91_extern_irq = 0; + of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) { +- if (val > 31) +- pr_warn("AIC: external irq %d > 31 skip it\n", val); ++ if (val >= n_irqs) ++ pr_warn("AIC: external irq %d >= %d skip it\n", ++ val, n_irqs); + else +- at91_extern_irq |= (1 << val); ++ set_bit(val, at91_extern_irq); + } + + irq_set_default_host(at91_aic_domain); + +- at91_aic_hw_init(NR_AIC_IRQS); ++ return 0; ++} ++ ++int __init at91_aic_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ int err; ++ ++ err = at91_aic_of_common_init(node, parent); ++ if (err) ++ return err; ++ ++ at91_aic_hw_init(n_irqs); ++ ++ return 0; ++} ++ ++int __init at91_aic5_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ int err; ++ ++ at91_aic_caps |= AT91_AIC_CAP_AIC5; ++ n_irqs = NR_AIC5_IRQS; ++ at91_aic_chip.irq_ack = at91_aic5_mask_irq; ++ at91_aic_chip.irq_mask = at91_aic5_mask_irq; ++ at91_aic_chip.irq_unmask = at91_aic5_unmask_irq; ++ at91_aic_chip.irq_eoi = at91_aic5_eoi; ++ at91_aic_irq_ops.map = at91_aic5_irq_map; ++ ++ err = at91_aic_of_common_init(node, parent); ++ if (err) ++ return err; ++ ++ at91_aic5_hw_init(n_irqs); + + return 0; + } +@@ -274,22 +501,25 @@ int __init at91_aic_of_init(struct device_node *node, + /* + * Initialize the AIC interrupt controller. + */ +-void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) ++void __init at91_aic_init(unsigned int *priority) + { + unsigned int i; + int irq_base; + ++ if (at91_aic_pm_init()) ++ panic("Unable to allocate bit maps\n"); ++ + at91_aic_base = ioremap(AT91_AIC, 512); + if (!at91_aic_base) + panic("Unable to ioremap AIC registers\n"); + + /* Add irq domain for AIC */ +- irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0); ++ irq_base = irq_alloc_descs(-1, 0, n_irqs, 0); + if (irq_base < 0) { + WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n"); + irq_base = 0; + } +- at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS, ++ at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs, + irq_base, 0, + &irq_domain_simple_ops, NULL); + +@@ -302,15 +532,14 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) + * The IVR is used by macro get_irqnr_and_base to read and verify. + * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. + */ +- for (i = 0; i < NR_AIC_IRQS; i++) { ++ for (i = 0; i < n_irqs; i++) { + /* Put hardware irq number in Source Vector Register: */ + at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i); + /* Active Low interrupt, with the specified priority */ + at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); +- + irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + +- at91_aic_hw_init(NR_AIC_IRQS); ++ at91_aic_hw_init(n_irqs); + } +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0061-dt-add-property-iteration-helpers.patch b/patches.at91/0061-dt-add-property-iteration-helpers.patch new file mode 100644 index 000000000000..40f12e568a15 --- /dev/null +++ b/patches.at91/0061-dt-add-property-iteration-helpers.patch @@ -0,0 +1,129 @@ +From b0a2eb064f2171838c4562f34eb1e492ce0361d5 Mon Sep 17 00:00:00 2001 +From: Stephen Warren +Date: Wed, 4 Apr 2012 09:27:46 -0600 +Subject: dt: add property iteration helpers + +This patch adds macros of_property_for_each_u32() and +of_property_for_each_string(), which iterate over an array of values +within a device-tree property. Usage is for example: + +struct property *prop; +const __be32 *p; +u32 u; +of_property_for_each_u32(np, "propname", prop, p, u) + printk("U32 value: %x\n", u); + +struct property *prop; +const char *s; +of_property_for_each_string(np, "propname", prop, s) + printk("String value: %s\n", s); + +Based on work by Rob Herring + +Cc: Grant Likely +Signed-off-by: Stephen Warren +Acked-by: Rob Herring +Signed-off-by: Linus Walleij +--- + drivers/of/base.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/of.h | 35 +++++++++++++++++++++++++++++++++++ + 2 files changed, 76 insertions(+) + +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node * + return id; + } + EXPORT_SYMBOL_GPL(of_alias_get_id); ++ ++const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, ++ u32 *pu) ++{ ++ const void *curv = cur; ++ ++ if (!prop) ++ return NULL; ++ ++ if (!cur) { ++ curv = prop->value; ++ goto out_val; ++ } ++ ++ curv += sizeof(*cur); ++ if (curv >= prop->value + prop->length) ++ return NULL; ++ ++out_val: ++ *pu = be32_to_cpup(curv); ++ return curv; ++} ++EXPORT_SYMBOL_GPL(of_prop_next_u32); ++ ++const char *of_prop_next_string(struct property *prop, const char *cur) ++{ ++ const void *curv = cur; ++ ++ if (!prop) ++ return NULL; ++ ++ if (!cur) ++ return prop->value; ++ ++ curv += strlen(cur) + 1; ++ if (curv >= prop->value + prop->length) ++ return NULL; ++ ++ return curv; ++} ++EXPORT_SYMBOL_GPL(of_prop_next_string); +--- a/include/linux/of.h ++++ b/include/linux/of.h +@@ -260,6 +260,37 @@ extern void of_detach_node(struct device + #endif + + #define of_match_ptr(_ptr) (_ptr) ++ ++/* ++ * struct property *prop; ++ * const __be32 *p; ++ * u32 u; ++ * ++ * of_property_for_each_u32(np, "propname", prop, p, u) ++ * printk("U32 value: %x\n", u); ++ */ ++const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, ++ u32 *pu); ++#define of_property_for_each_u32(np, propname, prop, p, u) \ ++ for (prop = of_find_property(np, propname, NULL), \ ++ p = of_prop_next_u32(prop, NULL, &u); \ ++ p; \ ++ p = of_prop_next_u32(prop, p, &u)) ++ ++/* ++ * struct property *prop; ++ * const char *s; ++ * ++ * of_property_for_each_string(np, "propname", prop, s) ++ * printk("String value: %s\n", s); ++ */ ++const char *of_prop_next_string(struct property *prop, const char *cur); ++#define of_property_for_each_string(np, propname, prop, s) \ ++ for (prop = of_find_property(np, propname, NULL), \ ++ s = of_prop_next_string(prop, NULL); \ ++ s; \ ++ s = of_prop_next_string(prop, s)) ++ + #else /* CONFIG_OF */ + + static inline const char* of_node_full_name(struct device_node *np) +@@ -355,6 +386,10 @@ static inline int of_machine_is_compatib + + #define of_match_ptr(_ptr) NULL + #define of_match_node(_matches, _node) NULL ++#define of_property_for_each_u32(np, propname, prop, p, u) \ ++ while (0) ++#define of_property_for_each_string(np, propname, prop, s) \ ++ while (0) + #endif /* CONFIG_OF */ + + #ifndef of_node_to_nid diff --git a/patches.at91/0062-ARM-at91-fix-new-build-errors.patch b/patches.at91/0062-ARM-at91-fix-new-build-errors.patch new file mode 100644 index 000000000000..b26870b9f081 --- /dev/null +++ b/patches.at91/0062-ARM-at91-fix-new-build-errors.patch @@ -0,0 +1,95 @@ +From a00b0ccc24fe0904fa187dd320709da1b6f44c90 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Wed, 4 Jul 2012 07:45:16 +0000 +Subject: ARM: at91: fix new build errors + +MULTI_IRQ_HANDLER and SPARSE_IRQ are now required everywhere because +mach/irqs.h and mach/entry-macros.S are gone but the symbols are +only selected for AT91SAM9, not for the NOMMU parts. + +A few files now need to include linux/io.h directly, which used to +be included through other headers that have changed. + +The new at91_aic_irq_priorities variable is only used with CONFIG_OF +enabled and should not be visible otherwise. + +Signed-off-by: Arnd Bergmann +Acked-by: Ludovic Desroches +Acked-by: Nicolas Ferre +--- + arch/arm/mach-at91/Kconfig | 4 ++++ + arch/arm/mach-at91/at91x40.c | 1 + + arch/arm/mach-at91/irq.c | 3 ++- + drivers/rtc/rtc-at91rm9200.c | 1 + + 4 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 7d0c40a..c8050b1 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -37,6 +37,8 @@ config SOC_AT91SAM9 + config SOC_AT91RM9200 + bool "AT91RM9200" + select CPU_ARM920T ++ select MULTI_IRQ_HANDLER ++ select SPARSE_IRQ + select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 + +@@ -142,6 +144,8 @@ config ARCH_AT91SAM9G45 + config ARCH_AT91X40 + bool "AT91x40" + depends on !MMU ++ select MULTI_IRQ_HANDLER ++ select SPARSE_IRQ + select ARCH_USES_GETTIMEOFFSET + + endchoice +diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c +index 4c0f5fd..46090e6 100644 +--- a/arch/arm/mach-at91/at91x40.c ++++ b/arch/arm/mach-at91/at91x40.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c +index c5eaaa0..1e02c0e 100644 +--- a/arch/arm/mach-at91/irq.c ++++ b/arch/arm/mach-at91/irq.c +@@ -49,7 +49,6 @@ static struct irq_domain *at91_aic_domain; + static struct device_node *at91_aic_np; + static unsigned int n_irqs = NR_AIC_IRQS; + static unsigned long at91_aic_caps = 0; +-static unsigned int *at91_aic_irq_priorities; + + /* AIC5 introduces a Source Select Register */ + #define AT91_AIC_CAP_AIC5 (1 << 0) +@@ -359,6 +358,8 @@ static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector) + } + + #if defined(CONFIG_OF) ++static unsigned int *at91_aic_irq_priorities; ++ + static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) + { +diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c +index f02acb0..a4c78c0 100644 +--- a/drivers/rtc/rtc-at91rm9200.c ++++ b/drivers/rtc/rtc-at91rm9200.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include + #include +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0063-dmaengine-at_hdmac-remove-some-at_dma_slave-comments.patch b/patches.at91/0063-dmaengine-at_hdmac-remove-some-at_dma_slave-comments.patch new file mode 100644 index 000000000000..64a2b3ea490b --- /dev/null +++ b/patches.at91/0063-dmaengine-at_hdmac-remove-some-at_dma_slave-comments.patch @@ -0,0 +1,32 @@ +From 0144b540ede14f0e1c1f3d084e4d48552a347b6a Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 10 May 2012 12:17:39 +0200 +Subject: dmaengine: at_hdmac: remove some at_dma_slave comments + +These comments were covering removed struct at_dma_slave fields. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Vinod Koul +--- + arch/arm/mach-at91/include/mach/at_hdmac.h | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h +index fff48d1..810a13e 100644 +--- a/arch/arm/mach-at91/include/mach/at_hdmac.h ++++ b/arch/arm/mach-at91/include/mach/at_hdmac.h +@@ -26,11 +26,6 @@ struct at_dma_platform_data { + /** + * struct at_dma_slave - Controller-specific information about a slave + * @dma_dev: required DMA master device +- * @tx_reg: physical address of data register used for +- * memory-to-peripheral transfers +- * @rx_reg: physical address of data register used for +- * peripheral-to-memory transfers +- * @reg_width: peripheral register width + * @cfg: Platform-specific initializer for the CFG register + * @ctrla: Platform-specific initializer for the CTRLA register + */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0064-dmaengine-at_hdmac-remove-ATC_DEFAULT_CTRLA-constant.patch b/patches.at91/0064-dmaengine-at_hdmac-remove-ATC_DEFAULT_CTRLA-constant.patch new file mode 100644 index 000000000000..ff3c21c85f24 --- /dev/null +++ b/patches.at91/0064-dmaengine-at_hdmac-remove-ATC_DEFAULT_CTRLA-constant.patch @@ -0,0 +1,66 @@ +From 6a24ecd4c954856980e2c5be94c85d97bf6a47d6 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 10 May 2012 12:17:40 +0200 +Subject: dmaengine: at_hdmac: remove ATC_DEFAULT_CTRLA constant + +Not needed constant that was set to 0. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Vinod Koul +--- + drivers/dma/at_hdmac.c | 12 +++++------- + 1 file changed, 5 insertions(+), 7 deletions(-) + +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -39,7 +39,6 @@ + */ + + #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) +-#define ATC_DEFAULT_CTRLA (0) + #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ + |ATC_DIF(AT_DMA_MEM_IF)) + +@@ -574,7 +573,6 @@ atc_prep_dma_memcpy(struct dma_chan *cha + return NULL; + } + +- ctrla = ATC_DEFAULT_CTRLA; + ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN + | ATC_SRC_ADDR_MODE_INCR + | ATC_DST_ADDR_MODE_INCR +@@ -585,13 +583,13 @@ atc_prep_dma_memcpy(struct dma_chan *cha + * of the most common optimization. + */ + if (!((src | dest | len) & 3)) { +- ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; ++ ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; + src_width = dst_width = 2; + } else if (!((src | dest | len) & 1)) { +- ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; ++ ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; + src_width = dst_width = 1; + } else { +- ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; ++ ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; + src_width = dst_width = 0; + } + +@@ -668,7 +666,7 @@ atc_prep_slave_sg(struct dma_chan *chan, + return NULL; + } + +- ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; ++ ctrla = atslave->ctrla; + ctrlb = ATC_IEN; + + switch (direction) { +@@ -812,7 +810,7 @@ atc_dma_cyclic_fill_desc(struct dma_chan + u32 ctrla; + + /* prepare common CRTLA value */ +- ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla ++ ctrla = atslave->ctrla + | ATC_DST_WIDTH(reg_width) + | ATC_SRC_WIDTH(reg_width) + | period_len >> reg_width; diff --git a/patches.at91/0065-dmaengine-at_hdmac-take-maxburst-from-slave-configur.patch b/patches.at91/0065-dmaengine-at_hdmac-take-maxburst-from-slave-configur.patch new file mode 100644 index 000000000000..2dc96e7fde2f --- /dev/null +++ b/patches.at91/0065-dmaengine-at_hdmac-take-maxburst-from-slave-configur.patch @@ -0,0 +1,129 @@ +From a692d1243e4c2513c96f00b9be1ab36fb65d2992 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 10 May 2012 12:17:41 +0200 +Subject: dmaengine: at_hdmac: take maxburst from slave configuration + +The maxburst/chunk size was taken from the private slave DMA data structure. +Use the common API provided by DMA_SLAVE_CONFIG to setup src/dst maxburst +values. +The ctrla field is not needed anymore in the slave private structure nor the +header constants that were located in an architecture specific directory. +The at91sam9g45_devices.c file that was using this platform data is also +modified to remove this now useless data. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Vinod Koul +--- + arch/arm/mach-at91/at91sam9g45_devices.c | 1 - + arch/arm/mach-at91/include/mach/at_hdmac.h | 21 --------------------- + drivers/dma/at_hdmac.c | 7 ++++--- + drivers/dma/at_hdmac_regs.h | 21 ++++++++++++++++++++- + 4 files changed, 24 insertions(+), 26 deletions(-) + +--- a/arch/arm/mach-at91/at91sam9g45_devices.c ++++ b/arch/arm/mach-at91/at91sam9g45_devices.c +@@ -433,7 +433,6 @@ void __init at91_add_device_mci(short mm + atslave->dma_dev = &at_hdmac_device.dev; + atslave->cfg = ATC_FIFOCFG_HALFFIFO + | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW; +- atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16; + if (mmc_id == 0) /* MCI0 */ + atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0) + | ATC_DST_PER(AT_DMA_ID_MCI0); +--- a/arch/arm/mach-at91/include/mach/at_hdmac.h ++++ b/arch/arm/mach-at91/include/mach/at_hdmac.h +@@ -27,12 +27,10 @@ struct at_dma_platform_data { + * struct at_dma_slave - Controller-specific information about a slave + * @dma_dev: required DMA master device + * @cfg: Platform-specific initializer for the CFG register +- * @ctrla: Platform-specific initializer for the CTRLA register + */ + struct at_dma_slave { + struct device *dma_dev; + u32 cfg; +- u32 ctrla; + }; + + +@@ -59,24 +57,5 @@ struct at_dma_slave { + #define ATC_FIFOCFG_HALFFIFO (0x1 << 28) + #define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28) + +-/* Platform-configurable bits in CTRLA */ +-#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */ +-#define ATC_SCSIZE_1 (0x0 << 16) +-#define ATC_SCSIZE_4 (0x1 << 16) +-#define ATC_SCSIZE_8 (0x2 << 16) +-#define ATC_SCSIZE_16 (0x3 << 16) +-#define ATC_SCSIZE_32 (0x4 << 16) +-#define ATC_SCSIZE_64 (0x5 << 16) +-#define ATC_SCSIZE_128 (0x6 << 16) +-#define ATC_SCSIZE_256 (0x7 << 16) +-#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */ +-#define ATC_DCSIZE_1 (0x0 << 20) +-#define ATC_DCSIZE_4 (0x1 << 20) +-#define ATC_DCSIZE_8 (0x2 << 20) +-#define ATC_DCSIZE_16 (0x3 << 20) +-#define ATC_DCSIZE_32 (0x4 << 20) +-#define ATC_DCSIZE_64 (0x5 << 20) +-#define ATC_DCSIZE_128 (0x6 << 20) +-#define ATC_DCSIZE_256 (0x7 << 20) + + #endif /* AT_HDMAC_H */ +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -666,7 +666,8 @@ atc_prep_slave_sg(struct dma_chan *chan, + return NULL; + } + +- ctrla = atslave->ctrla; ++ ctrla = ATC_SCSIZE(sconfig->src_maxburst) ++ | ATC_DCSIZE(sconfig->dst_maxburst); + ctrlb = ATC_IEN; + + switch (direction) { +@@ -805,12 +806,12 @@ atc_dma_cyclic_fill_desc(struct dma_chan + enum dma_transfer_direction direction) + { + struct at_dma_chan *atchan = to_at_dma_chan(chan); +- struct at_dma_slave *atslave = chan->private; + struct dma_slave_config *sconfig = &atchan->dma_sconfig; + u32 ctrla; + + /* prepare common CRTLA value */ +- ctrla = atslave->ctrla ++ ctrla = ATC_SCSIZE(sconfig->src_maxburst) ++ | ATC_DCSIZE(sconfig->dst_maxburst) + | ATC_DST_WIDTH(reg_width) + | ATC_SRC_WIDTH(reg_width) + | period_len >> reg_width; +--- a/drivers/dma/at_hdmac_regs.h ++++ b/drivers/dma/at_hdmac_regs.h +@@ -87,7 +87,26 @@ + /* Bitfields in CTRLA */ + #define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */ + #define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */ +-/* Chunck Tranfer size definitions are in at_hdmac.h */ ++#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */ ++#define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16)) ++#define ATC_SCSIZE_1 (0x0 << 16) ++#define ATC_SCSIZE_4 (0x1 << 16) ++#define ATC_SCSIZE_8 (0x2 << 16) ++#define ATC_SCSIZE_16 (0x3 << 16) ++#define ATC_SCSIZE_32 (0x4 << 16) ++#define ATC_SCSIZE_64 (0x5 << 16) ++#define ATC_SCSIZE_128 (0x6 << 16) ++#define ATC_SCSIZE_256 (0x7 << 16) ++#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */ ++#define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20)) ++#define ATC_DCSIZE_1 (0x0 << 20) ++#define ATC_DCSIZE_4 (0x1 << 20) ++#define ATC_DCSIZE_8 (0x2 << 20) ++#define ATC_DCSIZE_16 (0x3 << 20) ++#define ATC_DCSIZE_32 (0x4 << 20) ++#define ATC_DCSIZE_64 (0x5 << 20) ++#define ATC_DCSIZE_128 (0x6 << 20) ++#define ATC_DCSIZE_256 (0x7 << 20) + #define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */ + #define ATC_SRC_WIDTH(x) ((x) << 24) + #define ATC_SRC_WIDTH_BYTE (0x0 << 24) diff --git a/patches.at91/0066-dmaengine-at_hdmac-trivial-fix-comment-in-header.patch b/patches.at91/0066-dmaengine-at_hdmac-trivial-fix-comment-in-header.patch new file mode 100644 index 000000000000..60572dc4f2a8 --- /dev/null +++ b/patches.at91/0066-dmaengine-at_hdmac-trivial-fix-comment-in-header.patch @@ -0,0 +1,36 @@ +From e7d260949873bedcc9fe6cd9f60eb1d99359d119 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 12 Jun 2012 10:34:52 +0200 +Subject: dmaengine: at_hdmac: trivial: fix comment in header + +Not all Atmel SoCs were pointed out in header comment which was bringing +confusion. Remove the truncated list of supported devices, replace by the +only one that is not supported. + +Reported-by: Elen Song +Signed-off-by: Nicolas Ferre +--- + drivers/dma/at_hdmac.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c +index 7292aa8..bb16013 100644 +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -9,10 +9,9 @@ + * (at your option) any later version. + * + * +- * This supports the Atmel AHB DMA Controller, +- * +- * The driver has currently been tested with the Atmel AT91SAM9RL +- * and AT91SAM9G45 series. ++ * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. ++ * The only Atmel DMA Controller that is not covered by this driver is the one ++ * found on AT91SAM9263. + */ + + #include +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0069-AT91-Remove-fixed-mapping-for-AT91RM9200-ethernet.patch b/patches.at91/0069-AT91-Remove-fixed-mapping-for-AT91RM9200-ethernet.patch new file mode 100644 index 000000000000..d2942666314b --- /dev/null +++ b/patches.at91/0069-AT91-Remove-fixed-mapping-for-AT91RM9200-ethernet.patch @@ -0,0 +1,1121 @@ +From 272e7886507edd10614cdb998e2374afd122149e Mon Sep 17 00:00:00 2001 +From: Andrew Victor +Date: Thu, 26 Apr 2012 00:30:42 +0000 +Subject: AT91: Remove fixed mapping for AT91RM9200 ethernet + +The AT91RM9200 Ethernet controller still has a fixed IO mapping. +So: +* Remove the fixed IO mapping and AT91_VA_BASE_EMAC definition. +* Pass the physical base-address via platform-resources to the driver. +* Convert at91_ether.c driver to perform an ioremap(). +* Ethernet PHY detection needs to be performed during the driver +initialization process, it can no longer be done first. + +Signed-off-by: Andrew Victor +Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +Signed-off-by: Nicolas Ferre +Signed-off-by: David S. Miller +--- + arch/arm/mach-at91/at91rm9200.c | 10 - + arch/arm/mach-at91/at91rm9200_devices.c | 4 +- + arch/arm/mach-at91/include/mach/hardware.h | 1 - + drivers/net/ethernet/cadence/at91_ether.c | 527 ++++++++++++++++------------- + drivers/net/ethernet/cadence/at91_ether.h | 1 + + 5 files changed, 287 insertions(+), 256 deletions(-) + +diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c +index 801c30b..6f50c67 100644 +--- a/arch/arm/mach-at91/at91rm9200.c ++++ b/arch/arm/mach-at91/at91rm9200.c +@@ -27,15 +27,6 @@ + #include "clock.h" + #include "sam9_smc.h" + +-static struct map_desc at91rm9200_io_desc[] __initdata = { +- { +- .virtual = AT91_VA_BASE_EMAC, +- .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), +- .length = SZ_16K, +- .type = MT_DEVICE, +- }, +-}; +- + /* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ +@@ -304,7 +295,6 @@ static void __init at91rm9200_map_io(void) + { + /* Map peripherals */ + at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); +- iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); + } + + static void __init at91rm9200_ioremap_registers(void) +diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c +index 04d69d3..01fb732 100644 +--- a/arch/arm/mach-at91/at91rm9200_devices.c ++++ b/arch/arm/mach-at91/at91rm9200_devices.c +@@ -140,8 +140,8 @@ static struct macb_platform_data eth_data; + + static struct resource eth_resources[] = { + [0] = { +- .start = AT91_VA_BASE_EMAC, +- .end = AT91_VA_BASE_EMAC + SZ_16K - 1, ++ .start = AT91RM9200_BASE_EMAC, ++ .end = AT91RM9200_BASE_EMAC + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { +diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h +index 24b46bd..09242b6 100644 +--- a/arch/arm/mach-at91/include/mach/hardware.h ++++ b/arch/arm/mach-at91/include/mach/hardware.h +@@ -85,7 +85,6 @@ + * Virtual to Physical Address mapping for IO devices. + */ + #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) +-#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) + + /* Internal SRAM is mapped below the IO devices */ + #define AT91_SRAM_MAX SZ_1M +diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c +index 9061170..62761e1 100644 +--- a/drivers/net/ethernet/cadence/at91_ether.c ++++ b/drivers/net/ethernet/cadence/at91_ether.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -51,21 +52,17 @@ + /* + * Read from a EMAC register. + */ +-static inline unsigned long at91_emac_read(unsigned int reg) ++static inline unsigned long at91_emac_read(struct at91_private *lp, unsigned int reg) + { +- void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; +- +- return __raw_readl(emac_base + reg); ++ return __raw_readl(lp->emac_base + reg); + } + + /* + * Write to a EMAC register. + */ +-static inline void at91_emac_write(unsigned int reg, unsigned long value) ++static inline void at91_emac_write(struct at91_private *lp, unsigned int reg, unsigned long value) + { +- void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; +- +- __raw_writel(value, emac_base + reg); ++ __raw_writel(value, lp->emac_base + reg); + } + + /* ........................... PHY INTERFACE ........................... */ +@@ -75,32 +72,33 @@ static inline void at91_emac_write(unsigned int reg, unsigned long value) + * When not called from an interrupt-handler, access to the PHY must be + * protected by a spinlock. + */ +-static void enable_mdi(void) ++static void enable_mdi(struct at91_private *lp) + { + unsigned long ctl; + +- ctl = at91_emac_read(AT91_EMAC_CTL); +- at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ ++ ctl = at91_emac_read(lp, AT91_EMAC_CTL); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ + } + + /* + * Disable the MDIO bit in the MAC control register + */ +-static void disable_mdi(void) ++static void disable_mdi(struct at91_private *lp) + { + unsigned long ctl; + +- ctl = at91_emac_read(AT91_EMAC_CTL); +- at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ ++ ctl = at91_emac_read(lp, AT91_EMAC_CTL); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ + } + + /* + * Wait until the PHY operation is complete. + */ +-static inline void at91_phy_wait(void) { ++static inline void at91_phy_wait(struct at91_private *lp) ++{ + unsigned long timeout = jiffies + 2; + +- while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { ++ while (!(at91_emac_read(lp, AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { + if (time_after(jiffies, timeout)) { + printk("at91_ether: MIO timeout\n"); + break; +@@ -113,28 +111,28 @@ static inline void at91_phy_wait(void) { + * Write value to the a PHY register + * Note: MDI interface is assumed to already have been enabled. + */ +-static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) ++static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int value) + { +- at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W ++ at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W + | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); + + /* Wait until IDLE bit in Network Status register is cleared */ +- at91_phy_wait(); ++ at91_phy_wait(lp); + } + + /* + * Read value stored in a PHY register. + * Note: MDI interface is assumed to already have been enabled. + */ +-static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) ++static void read_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int *value) + { +- at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R ++ at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R + | ((phy_addr & 0x1f) << 23) | (address << 18)); + + /* Wait until IDLE bit in Network Status register is cleared */ +- at91_phy_wait(); ++ at91_phy_wait(lp); + +- *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; ++ *value = at91_emac_read(lp, AT91_EMAC_MAN) & AT91_EMAC_DATA; + } + + /* ........................... PHY MANAGEMENT .......................... */ +@@ -158,13 +156,13 @@ static void update_linkspeed(struct net_device *dev, int silent) + } + + /* Link up, or auto-negotiation still in progress */ +- read_phy(lp->phy_address, MII_BMSR, &bmsr); +- read_phy(lp->phy_address, MII_BMCR, &bmcr); ++ read_phy(lp, lp->phy_address, MII_BMSR, &bmsr); ++ read_phy(lp, lp->phy_address, MII_BMCR, &bmcr); + if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ + if (!(bmsr & BMSR_ANEGCOMPLETE)) + return; /* Do nothing - another interrupt generated when negotiation complete */ + +- read_phy(lp->phy_address, MII_LPA, &lpa); ++ read_phy(lp, lp->phy_address, MII_LPA, &lpa); + if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; + else speed = SPEED_10; + if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; +@@ -175,7 +173,7 @@ static void update_linkspeed(struct net_device *dev, int silent) + } + + /* Update the MAC */ +- mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); ++ mac_cfg = at91_emac_read(lp, AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); + if (speed == SPEED_100) { + if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ + mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; +@@ -186,7 +184,7 @@ static void update_linkspeed(struct net_device *dev, int silent) + mac_cfg |= AT91_EMAC_FD; + else {} /* 10 Half Duplex */ + } +- at91_emac_write(AT91_EMAC_CFG, mac_cfg); ++ at91_emac_write(lp, AT91_EMAC_CFG, mac_cfg); + + if (!silent) + printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); +@@ -207,34 +205,34 @@ static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) + * level-triggering. We therefore have to check if the PHY actually has + * an IRQ pending. + */ +- enable_mdi(); ++ enable_mdi(lp); + if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { +- read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ ++ read_phy(lp, lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ + if (!(phy & (1 << 0))) + goto done; + } + else if (lp->phy_type == MII_LXT971A_ID) { +- read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ ++ read_phy(lp, lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ + if (!(phy & (1 << 2))) + goto done; + } + else if (lp->phy_type == MII_BCM5221_ID) { +- read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ ++ read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ + if (!(phy & (1 << 0))) + goto done; + } + else if (lp->phy_type == MII_KS8721_ID) { +- read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ ++ read_phy(lp, lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ + if (!(phy & ((1 << 2) | 1))) + goto done; + } +- else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ +- read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); ++ else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ ++ read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &phy); + if (!(phy & ((1 << 2) | 1))) + goto done; + } + else if (lp->phy_type == MII_DP83848_ID) { +- read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ ++ read_phy(lp, lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ + if (!(phy & (1 << 7))) + goto done; + } +@@ -242,7 +240,7 @@ static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) + update_linkspeed(dev, 0); + + done: +- disable_mdi(); ++ disable_mdi(lp); + + return IRQ_HANDLED; + } +@@ -273,41 +271,41 @@ static void enable_phyirq(struct net_device *dev) + } + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + + if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ +- read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr); + dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ +- write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr); + } + else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ +- read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr); + dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ +- write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr); + } + else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ + dsintr = (1 << 15) | ( 1 << 14); +- write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr); + } + else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ + dsintr = (1 << 10) | ( 1 << 8); +- write_phy(lp->phy_address, MII_TPISTATUS, dsintr); ++ write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr); + } + else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ +- read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr); + dsintr = dsintr | 0x500; /* set bits 8, 10 */ +- write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr); + } + else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ +- read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr); + dsintr = dsintr | 0x3c; /* set bits 2..5 */ +- write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); +- read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); ++ write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr); ++ read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr); + dsintr = dsintr | 0x3; /* set bits 0,1 */ +- write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr); + } + +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + } + +@@ -326,43 +324,43 @@ static void disable_phyirq(struct net_device *dev) + } + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + + if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ +- read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr); + dsintr = dsintr | 0xf00; /* set bits 8..11 */ +- write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr); + } + else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ +- read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr); + dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ +- write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr); + } + else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ +- read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &dsintr); + dsintr = ~(1 << 14); +- write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr); + } + else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ +- read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); ++ read_phy(lp, lp->phy_address, MII_TPISTATUS, &dsintr); + dsintr = ~((1 << 10) | (1 << 8)); +- write_phy(lp->phy_address, MII_TPISTATUS, dsintr); ++ write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr); + } + else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ +- read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr); + dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ +- write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr); + } + else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ +- read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); ++ read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr); + dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ +- write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); +- read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); ++ write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr); ++ read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr); + dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ +- write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); ++ write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr); + } + +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + + irq_number = lp->board_data.phy_irq_pin; +@@ -379,17 +377,17 @@ static void reset_phy(struct net_device *dev) + unsigned int bmcr; + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + + /* Perform PHY reset */ +- write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); ++ write_phy(lp, lp->phy_address, MII_BMCR, BMCR_RESET); + + /* Wait until PHY reset is complete */ + do { +- read_phy(lp->phy_address, MII_BMCR, &bmcr); ++ read_phy(lp, lp->phy_address, MII_BMCR, &bmcr); + } while (!(bmcr & BMCR_RESET)); + +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + } + #endif +@@ -399,13 +397,37 @@ static void at91ether_check_link(unsigned long dev_id) + struct net_device *dev = (struct net_device *) dev_id; + struct at91_private *lp = netdev_priv(dev); + +- enable_mdi(); ++ enable_mdi(lp); + update_linkspeed(dev, 1); +- disable_mdi(); ++ disable_mdi(lp); + + mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); + } + ++/* ++ * Perform any PHY-specific initialization. ++ */ ++static void __init initialize_phy(struct at91_private *lp) ++{ ++ unsigned int val; ++ ++ spin_lock_irq(&lp->lock); ++ enable_mdi(lp); ++ ++ if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { ++ read_phy(lp, lp->phy_address, MII_DSCR_REG, &val); ++ if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ ++ lp->phy_media = PORT_FIBRE; ++ } else if (machine_is_csb337()) { ++ /* mix link activity status into LED2 link state */ ++ write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x0d22); ++ } else if (machine_is_ecbat91()) ++ write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x156A); ++ ++ disable_mdi(lp); ++ spin_unlock_irq(&lp->lock); ++} ++ + /* ......................... ADDRESS MANAGEMENT ........................ */ + + /* +@@ -454,17 +476,19 @@ static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, + */ + static void __init get_mac_address(struct net_device *dev) + { ++ struct at91_private *lp = netdev_priv(dev); ++ + /* Check Specific-Address 1 */ +- if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) ++ if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA1H), at91_emac_read(lp, AT91_EMAC_SA1L))) + return; + /* Check Specific-Address 2 */ +- if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) ++ if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA2H), at91_emac_read(lp, AT91_EMAC_SA2L))) + return; + /* Check Specific-Address 3 */ +- if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) ++ if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA3H), at91_emac_read(lp, AT91_EMAC_SA3L))) + return; + /* Check Specific-Address 4 */ +- if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) ++ if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA4H), at91_emac_read(lp, AT91_EMAC_SA4L))) + return; + + printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); +@@ -475,11 +499,13 @@ static void __init get_mac_address(struct net_device *dev) + */ + static void update_mac_address(struct net_device *dev) + { +- at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); +- at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); ++ struct at91_private *lp = netdev_priv(dev); + +- at91_emac_write(AT91_EMAC_SA2L, 0); +- at91_emac_write(AT91_EMAC_SA2H, 0); ++ at91_emac_write(lp, AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); ++ at91_emac_write(lp, AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); ++ ++ at91_emac_write(lp, AT91_EMAC_SA2L, 0); ++ at91_emac_write(lp, AT91_EMAC_SA2H, 0); + } + + /* +@@ -559,6 +585,7 @@ static int hash_get_index(__u8 *addr) + */ + static void at91ether_sethashtable(struct net_device *dev) + { ++ struct at91_private *lp = netdev_priv(dev); + struct netdev_hw_addr *ha; + unsigned long mc_filter[2]; + unsigned int bitnr; +@@ -570,8 +597,8 @@ static void at91ether_sethashtable(struct net_device *dev) + mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); + } + +- at91_emac_write(AT91_EMAC_HSL, mc_filter[0]); +- at91_emac_write(AT91_EMAC_HSH, mc_filter[1]); ++ at91_emac_write(lp, AT91_EMAC_HSL, mc_filter[0]); ++ at91_emac_write(lp, AT91_EMAC_HSH, mc_filter[1]); + } + + /* +@@ -579,9 +606,10 @@ static void at91ether_sethashtable(struct net_device *dev) + */ + static void at91ether_set_multicast_list(struct net_device *dev) + { ++ struct at91_private *lp = netdev_priv(dev); + unsigned long cfg; + +- cfg = at91_emac_read(AT91_EMAC_CFG); ++ cfg = at91_emac_read(lp, AT91_EMAC_CFG); + + if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ + cfg |= AT91_EMAC_CAF; +@@ -589,34 +617,37 @@ static void at91ether_set_multicast_list(struct net_device *dev) + cfg &= ~AT91_EMAC_CAF; + + if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ +- at91_emac_write(AT91_EMAC_HSH, -1); +- at91_emac_write(AT91_EMAC_HSL, -1); ++ at91_emac_write(lp, AT91_EMAC_HSH, -1); ++ at91_emac_write(lp, AT91_EMAC_HSL, -1); + cfg |= AT91_EMAC_MTI; + } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */ + at91ether_sethashtable(dev); + cfg |= AT91_EMAC_MTI; + } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ +- at91_emac_write(AT91_EMAC_HSH, 0); +- at91_emac_write(AT91_EMAC_HSL, 0); ++ at91_emac_write(lp, AT91_EMAC_HSH, 0); ++ at91_emac_write(lp, AT91_EMAC_HSL, 0); + cfg &= ~AT91_EMAC_MTI; + } + +- at91_emac_write(AT91_EMAC_CFG, cfg); ++ at91_emac_write(lp, AT91_EMAC_CFG, cfg); + } + + /* ......................... ETHTOOL SUPPORT ........................... */ + + static int mdio_read(struct net_device *dev, int phy_id, int location) + { ++ struct at91_private *lp = netdev_priv(dev); + unsigned int value; + +- read_phy(phy_id, location, &value); ++ read_phy(lp, phy_id, location, &value); + return value; + } + + static void mdio_write(struct net_device *dev, int phy_id, int location, int value) + { +- write_phy(phy_id, location, value); ++ struct at91_private *lp = netdev_priv(dev); ++ ++ write_phy(lp, phy_id, location, value); + } + + static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +@@ -625,11 +656,11 @@ static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cm + int ret; + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + + ret = mii_ethtool_gset(&lp->mii, cmd); + +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + + if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ +@@ -646,11 +677,11 @@ static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cm + int ret; + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + + ret = mii_ethtool_sset(&lp->mii, cmd); + +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + + return ret; +@@ -662,11 +693,11 @@ static int at91ether_nwayreset(struct net_device *dev) + int ret; + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + + ret = mii_nway_restart(&lp->mii); + +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + + return ret; +@@ -696,9 +727,9 @@ static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) + return -EINVAL; + + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + + return res; +@@ -731,11 +762,11 @@ static void at91ether_start(struct net_device *dev) + lp->rxBuffIndex = 0; + + /* Program address of descriptor list in Rx Buffer Queue register */ +- at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); ++ at91_emac_write(lp, AT91_EMAC_RBQP, (unsigned long) dlist_phys); + + /* Enable Receive and Transmit */ +- ctl = at91_emac_read(AT91_EMAC_CTL); +- at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); ++ ctl = at91_emac_read(lp, AT91_EMAC_CTL); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); + } + + /* +@@ -752,8 +783,8 @@ static int at91ether_open(struct net_device *dev) + clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ + + /* Clear internal statistics */ +- ctl = at91_emac_read(AT91_EMAC_CTL); +- at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); ++ ctl = at91_emac_read(lp, AT91_EMAC_CTL); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); + + /* Update the MAC address (incase user has changed it) */ + update_mac_address(dev); +@@ -762,15 +793,15 @@ static int at91ether_open(struct net_device *dev) + enable_phyirq(dev); + + /* Enable MAC interrupts */ +- at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA ++ at91_emac_write(lp, AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA + | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM + | AT91_EMAC_ROVR | AT91_EMAC_ABT); + + /* Determine current link speed */ + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + update_linkspeed(dev, 0); +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + + at91ether_start(dev); +@@ -787,14 +818,14 @@ static int at91ether_close(struct net_device *dev) + unsigned long ctl; + + /* Disable Receiver and Transmitter */ +- ctl = at91_emac_read(AT91_EMAC_CTL); +- at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); ++ ctl = at91_emac_read(lp, AT91_EMAC_CTL); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); + + /* Disable PHY interrupt */ + disable_phyirq(dev); + + /* Disable MAC interrupts */ +- at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA ++ at91_emac_write(lp, AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA + | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM + | AT91_EMAC_ROVR | AT91_EMAC_ABT); + +@@ -812,7 +843,7 @@ static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) + { + struct at91_private *lp = netdev_priv(dev); + +- if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { ++ if (at91_emac_read(lp, AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { + netif_stop_queue(dev); + + /* Store packet information (to free when Tx completed) */ +@@ -822,9 +853,9 @@ static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) + dev->stats.tx_bytes += skb->len; + + /* Set address of the data in the Transmit Address register */ +- at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); ++ at91_emac_write(lp, AT91_EMAC_TAR, lp->skb_physaddr); + /* Set length of the packet in the Transmit Control register */ +- at91_emac_write(AT91_EMAC_TCR, skb->len); ++ at91_emac_write(lp, AT91_EMAC_TCR, skb->len); + + } else { + printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n"); +@@ -841,31 +872,32 @@ static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) + */ + static struct net_device_stats *at91ether_stats(struct net_device *dev) + { ++ struct at91_private *lp = netdev_priv(dev); + int ale, lenerr, seqe, lcol, ecol; + + if (netif_running(dev)) { +- dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ +- ale = at91_emac_read(AT91_EMAC_ALE); ++ dev->stats.rx_packets += at91_emac_read(lp, AT91_EMAC_OK); /* Good frames received */ ++ ale = at91_emac_read(lp, AT91_EMAC_ALE); + dev->stats.rx_frame_errors += ale; /* Alignment errors */ +- lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); ++ lenerr = at91_emac_read(lp, AT91_EMAC_ELR) + at91_emac_read(lp, AT91_EMAC_USF); + dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ +- seqe = at91_emac_read(AT91_EMAC_SEQE); ++ seqe = at91_emac_read(lp, AT91_EMAC_SEQE); + dev->stats.rx_crc_errors += seqe; /* CRC error */ +- dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ ++ dev->stats.rx_fifo_errors += at91_emac_read(lp, AT91_EMAC_DRFC);/* Receive buffer not available */ + dev->stats.rx_errors += (ale + lenerr + seqe +- + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); ++ + at91_emac_read(lp, AT91_EMAC_CDE) + at91_emac_read(lp, AT91_EMAC_RJB)); + +- dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ +- dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ +- dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ +- dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ ++ dev->stats.tx_packets += at91_emac_read(lp, AT91_EMAC_FRA); /* Frames successfully transmitted */ ++ dev->stats.tx_fifo_errors += at91_emac_read(lp, AT91_EMAC_TUE); /* Transmit FIFO underruns */ ++ dev->stats.tx_carrier_errors += at91_emac_read(lp, AT91_EMAC_CSE); /* Carrier Sense errors */ ++ dev->stats.tx_heartbeat_errors += at91_emac_read(lp, AT91_EMAC_SQEE);/* Heartbeat error */ + +- lcol = at91_emac_read(AT91_EMAC_LCOL); +- ecol = at91_emac_read(AT91_EMAC_ECOL); ++ lcol = at91_emac_read(lp, AT91_EMAC_LCOL); ++ ecol = at91_emac_read(lp, AT91_EMAC_ECOL); + dev->stats.tx_window_errors += lcol; /* Late collisions */ + dev->stats.tx_aborted_errors += ecol; /* 16 collisions */ + +- dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); ++ dev->stats.collisions += (at91_emac_read(lp, AT91_EMAC_SCOL) + at91_emac_read(lp, AT91_EMAC_MCOL) + lcol + ecol); + } + return &dev->stats; + } +@@ -922,7 +954,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id) + + /* MAC Interrupt Status register indicates what interrupts are pending. + It is automatically cleared once read. */ +- intstatus = at91_emac_read(AT91_EMAC_ISR); ++ intstatus = at91_emac_read(lp, AT91_EMAC_ISR); + + if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ + at91ether_rx(dev); +@@ -942,9 +974,9 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id) + + /* Work-around for Errata #11 */ + if (intstatus & AT91_EMAC_RBNA) { +- ctl = at91_emac_read(AT91_EMAC_CTL); +- at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); +- at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); ++ ctl = at91_emac_read(lp, AT91_EMAC_CTL); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); ++ at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE); + } + + if (intstatus & AT91_EMAC_ROVR) +@@ -980,189 +1012,199 @@ static const struct net_device_ops at91ether_netdev_ops = { + }; + + /* +- * Initialize the ethernet interface ++ * Detect the PHY type, and its address. + */ +-static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, +- struct platform_device *pdev, struct clk *ether_clk) ++static int __init at91ether_phy_detect(struct at91_private *lp) ++{ ++ unsigned int phyid1, phyid2; ++ unsigned long phy_id; ++ unsigned short phy_address = 0; ++ ++ while (phy_address < PHY_MAX_ADDR) { ++ /* Read the PHY ID registers */ ++ enable_mdi(lp); ++ read_phy(lp, phy_address, MII_PHYSID1, &phyid1); ++ read_phy(lp, phy_address, MII_PHYSID2, &phyid2); ++ disable_mdi(lp); ++ ++ phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); ++ switch (phy_id) { ++ case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ ++ case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ ++ case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ ++ case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ ++ case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ ++ case MII_DP83847_ID: /* National Semiconductor DP83847: */ ++ case MII_DP83848_ID: /* National Semiconductor DP83848: */ ++ case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ ++ case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ ++ case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ ++ case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ ++ /* store detected values */ ++ lp->phy_type = phy_id; /* Type of PHY connected */ ++ lp->phy_address = phy_address; /* MDI address of PHY */ ++ return 1; ++ } ++ ++ phy_address++; ++ } ++ ++ return 0; /* not detected */ ++} ++ ++ ++/* ++ * Detect MAC & PHY and perform ethernet interface initialization ++ */ ++static int __init at91ether_probe(struct platform_device *pdev) + { + struct macb_platform_data *board_data = pdev->dev.platform_data; ++ struct resource *regs; + struct net_device *dev; + struct at91_private *lp; +- unsigned int val; + int res; + ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) ++ return -ENOENT; ++ + dev = alloc_etherdev(sizeof(struct at91_private)); + if (!dev) + return -ENOMEM; + +- dev->base_addr = AT91_VA_BASE_EMAC; +- dev->irq = AT91RM9200_ID_EMAC; ++ lp = netdev_priv(dev); ++ lp->board_data = *board_data; ++ spin_lock_init(&lp->lock); ++ ++ dev->base_addr = regs->start; /* physical base address */ ++ lp->emac_base = ioremap(regs->start, regs->end - regs->start + 1); ++ if (!lp->emac_base) { ++ res = -ENOMEM; ++ goto err_free_dev; ++ } ++ ++ /* Clock */ ++ lp->ether_clk = clk_get(&pdev->dev, "ether_clk"); ++ if (IS_ERR(lp->ether_clk)) { ++ res = -ENODEV; ++ goto err_ioumap; ++ } ++ clk_enable(lp->ether_clk); + + /* Install the interrupt handler */ ++ dev->irq = platform_get_irq(pdev, 0); + if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { +- free_netdev(dev); +- return -EBUSY; ++ res = -EBUSY; ++ goto err_disable_clock; + } + + /* Allocate memory for DMA Receive descriptors */ +- lp = netdev_priv(dev); + lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); + if (lp->dlist == NULL) { +- free_irq(dev->irq, dev); +- free_netdev(dev); +- return -ENOMEM; ++ res = -ENOMEM; ++ goto err_free_irq; + } +- lp->board_data = *board_data; +- lp->ether_clk = ether_clk; +- platform_set_drvdata(pdev, dev); +- +- spin_lock_init(&lp->lock); + + ether_setup(dev); + dev->netdev_ops = &at91ether_netdev_ops; + dev->ethtool_ops = &at91ether_ethtool_ops; +- ++ platform_set_drvdata(pdev, dev); + SET_NETDEV_DEV(dev, &pdev->dev); + + get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ + update_mac_address(dev); /* Program ethernet address into MAC */ + +- at91_emac_write(AT91_EMAC_CTL, 0); ++ at91_emac_write(lp, AT91_EMAC_CTL, 0); + +- if (lp->board_data.is_rmii) +- at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); ++ if (board_data->is_rmii) ++ at91_emac_write(lp, AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); + else +- at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); ++ at91_emac_write(lp, AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); + +- /* Perform PHY-specific initialization */ +- spin_lock_irq(&lp->lock); +- enable_mdi(); +- if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { +- read_phy(phy_address, MII_DSCR_REG, &val); +- if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ +- lp->phy_media = PORT_FIBRE; +- } else if (machine_is_csb337()) { +- /* mix link activity status into LED2 link state */ +- write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); +- } else if (machine_is_ecbat91()) +- write_phy(phy_address, MII_LEDCTRL_REG, 0x156A); ++ /* Detect PHY */ ++ if (!at91ether_phy_detect(lp)) { ++ printk(KERN_ERR "at91_ether: Could not detect ethernet PHY\n"); ++ res = -ENODEV; ++ goto err_free_dmamem; ++ } + +- disable_mdi(); +- spin_unlock_irq(&lp->lock); ++ initialize_phy(lp); + + lp->mii.dev = dev; /* Support for ethtool */ + lp->mii.mdio_read = mdio_read; + lp->mii.mdio_write = mdio_write; +- lp->mii.phy_id = phy_address; ++ lp->mii.phy_id = lp->phy_address; + lp->mii.phy_id_mask = 0x1f; + lp->mii.reg_num_mask = 0x1f; + +- lp->phy_type = phy_type; /* Type of PHY connected */ +- lp->phy_address = phy_address; /* MDI address of PHY */ +- + /* Register the network interface */ + res = register_netdev(dev); +- if (res) { +- free_irq(dev->irq, dev); +- free_netdev(dev); +- dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); +- return res; +- } ++ if (res) ++ goto err_free_dmamem; + + /* Determine current link speed */ + spin_lock_irq(&lp->lock); +- enable_mdi(); ++ enable_mdi(lp); + update_linkspeed(dev, 0); +- disable_mdi(); ++ disable_mdi(lp); + spin_unlock_irq(&lp->lock); + netif_carrier_off(dev); /* will be enabled in open() */ + + /* If board has no PHY IRQ, use a timer to poll the PHY */ +- if (!gpio_is_valid(lp->board_data.phy_irq_pin)) { ++ if (gpio_is_valid(lp->board_data.phy_irq_pin)) { ++ gpio_request(board_data->phy_irq_pin, "ethernet_phy"); ++ } else { ++ /* If board has no PHY IRQ, use a timer to poll the PHY */ + init_timer(&lp->check_timer); + lp->check_timer.data = (unsigned long)dev; + lp->check_timer.function = at91ether_check_link; +- } else if (lp->board_data.phy_irq_pin >= 32) +- gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); ++ } + + /* Display ethernet banner */ + printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n", + dev->name, (uint) dev->base_addr, dev->irq, +- at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", +- at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", ++ at91_emac_read(lp, AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", ++ at91_emac_read(lp, AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", + dev->dev_addr); +- if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) ++ if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) + printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); +- else if (phy_type == MII_LXT971A_ID) ++ else if (lp->phy_type == MII_LXT971A_ID) + printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); +- else if (phy_type == MII_RTL8201_ID) ++ else if (lp->phy_type == MII_RTL8201_ID) + printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); +- else if (phy_type == MII_BCM5221_ID) ++ else if (lp->phy_type == MII_BCM5221_ID) + printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); +- else if (phy_type == MII_DP83847_ID) ++ else if (lp->phy_type == MII_DP83847_ID) + printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); +- else if (phy_type == MII_DP83848_ID) ++ else if (lp->phy_type == MII_DP83848_ID) + printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name); +- else if (phy_type == MII_AC101L_ID) ++ else if (lp->phy_type == MII_AC101L_ID) + printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); +- else if (phy_type == MII_KS8721_ID) ++ else if (lp->phy_type == MII_KS8721_ID) + printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); +- else if (phy_type == MII_T78Q21x3_ID) ++ else if (lp->phy_type == MII_T78Q21x3_ID) + printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name); +- else if (phy_type == MII_LAN83C185_ID) ++ else if (lp->phy_type == MII_LAN83C185_ID) + printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name); + +- return 0; +-} +- +-/* +- * Detect MAC and PHY and perform initialization +- */ +-static int __init at91ether_probe(struct platform_device *pdev) +-{ +- unsigned int phyid1, phyid2; +- int detected = -1; +- unsigned long phy_id; +- unsigned short phy_address = 0; +- struct clk *ether_clk; +- +- ether_clk = clk_get(&pdev->dev, "ether_clk"); +- if (IS_ERR(ether_clk)) { +- printk(KERN_ERR "at91_ether: no clock defined\n"); +- return -ENODEV; +- } +- clk_enable(ether_clk); /* Enable Peripheral clock */ +- +- while ((detected != 0) && (phy_address < 32)) { +- /* Read the PHY ID registers */ +- enable_mdi(); +- read_phy(phy_address, MII_PHYSID1, &phyid1); +- read_phy(phy_address, MII_PHYSID2, &phyid2); +- disable_mdi(); +- +- phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); +- switch (phy_id) { +- case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ +- case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ +- case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ +- case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ +- case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ +- case MII_DP83847_ID: /* National Semiconductor DP83847: */ +- case MII_DP83848_ID: /* National Semiconductor DP83848: */ +- case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ +- case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ +- case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ +- case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ +- detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); +- break; +- } ++ clk_disable(lp->ether_clk); /* Disable Peripheral clock */ + +- phy_address++; +- } ++ return 0; + +- clk_disable(ether_clk); /* Disable Peripheral clock */ + +- return detected; ++err_free_dmamem: ++ platform_set_drvdata(pdev, NULL); ++ dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); ++err_free_irq: ++ free_irq(dev->irq, dev); ++err_disable_clock: ++ clk_disable(lp->ether_clk); ++ clk_put(lp->ether_clk); ++err_ioumap: ++ iounmap(lp->emac_base); ++err_free_dev: ++ free_netdev(dev); ++ return res; + } + + static int __devexit at91ether_remove(struct platform_device *pdev) +@@ -1170,8 +1212,7 @@ static int __devexit at91ether_remove(struct platform_device *pdev) + struct net_device *dev = platform_get_drvdata(pdev); + struct at91_private *lp = netdev_priv(dev); + +- if (gpio_is_valid(lp->board_data.phy_irq_pin) && +- lp->board_data.phy_irq_pin >= 32) ++ if (gpio_is_valid(lp->board_data.phy_irq_pin)) + gpio_free(lp->board_data.phy_irq_pin); + + unregister_netdev(dev); +diff --git a/drivers/net/ethernet/cadence/at91_ether.h b/drivers/net/ethernet/cadence/at91_ether.h +index 3725fbb0..0ef6328 100644 +--- a/drivers/net/ethernet/cadence/at91_ether.h ++++ b/drivers/net/ethernet/cadence/at91_ether.h +@@ -88,6 +88,7 @@ struct at91_private + struct macb_platform_data board_data; /* board-specific + * configuration (shared with + * macb for common data */ ++ void __iomem *emac_base; /* base register address */ + struct clk *ether_clk; /* clock */ + + /* PHY */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0070-net-at91_ether-use-gpio_to_irq-for-phy-IRQ-line.patch b/patches.at91/0070-net-at91_ether-use-gpio_to_irq-for-phy-IRQ-line.patch new file mode 100644 index 000000000000..07c79ae37969 --- /dev/null +++ b/patches.at91/0070-net-at91_ether-use-gpio_to_irq-for-phy-IRQ-line.patch @@ -0,0 +1,62 @@ +From 4c7f53afde86fed3bbc8cb4583b46e0b154ca01f Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 26 Apr 2012 00:30:43 +0000 +Subject: net/at91_ether: use gpio_to_irq for phy IRQ line + +Use the gpio_to_irq() function to retrieve the phy IRQ line +from the GPIO pin specification. +This fix is needed now that we have moved to irqdomains on AT91. + +Reported-by: Jamie Iles +Signed-off-by: Nicolas Ferre +Cc: Andrew Victor +Cc: David S. Miller +Cc: netdev@vger.kernel.org +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/at91_ether.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c +index 62761e1..7788419 100644 +--- a/drivers/net/ethernet/cadence/at91_ether.c ++++ b/drivers/net/ethernet/cadence/at91_ether.c +@@ -263,7 +263,7 @@ static void enable_phyirq(struct net_device *dev) + return; + } + +- irq_number = lp->board_data.phy_irq_pin; ++ irq_number = gpio_to_irq(lp->board_data.phy_irq_pin); + status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); + if (status) { + printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); +@@ -363,7 +363,7 @@ static void disable_phyirq(struct net_device *dev) + disable_mdi(lp); + spin_unlock_irq(&lp->lock); + +- irq_number = lp->board_data.phy_irq_pin; ++ irq_number = gpio_to_irq(lp->board_data.phy_irq_pin); + free_irq(irq_number, dev); /* Free interrupt handler */ + } + +@@ -1234,7 +1234,7 @@ static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) + + if (netif_running(net_dev)) { + if (gpio_is_valid(lp->board_data.phy_irq_pin)) { +- int phy_irq = lp->board_data.phy_irq_pin; ++ int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin); + disable_irq(phy_irq); + } + +@@ -1258,7 +1258,7 @@ static int at91ether_resume(struct platform_device *pdev) + netif_start_queue(net_dev); + + if (gpio_is_valid(lp->board_data.phy_irq_pin)) { +- int phy_irq = lp->board_data.phy_irq_pin; ++ int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin); + enable_irq(phy_irq); + } + } +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0071-net-macb-manage-carrier-state-with-call-to-netif_car.patch b/patches.at91/0071-net-macb-manage-carrier-state-with-call-to-netif_car.patch new file mode 100644 index 000000000000..de3a73a9d785 --- /dev/null +++ b/patches.at91/0071-net-macb-manage-carrier-state-with-call-to-netif_car.patch @@ -0,0 +1,67 @@ +From 7753ed0e33522a318f41773a78c2900a038c23be Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 3 Jul 2012 23:14:13 +0000 +Subject: net/macb: manage carrier state with call to netif_carrier_{on|off}() + +OFF carrier state is setup in probe() open() and suspend() functions. +The carrier ON state is managed in macb_handle_link_change(). + +Signed-off-by: Nicolas Ferre +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/cadence/macb.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index c4834c2..6100b85 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -179,13 +179,16 @@ static void macb_handle_link_change(struct net_device *dev) + spin_unlock_irqrestore(&bp->lock, flags); + + if (status_change) { +- if (phydev->link) ++ if (phydev->link) { ++ netif_carrier_on(dev); + netdev_info(dev, "link up (%d/%s)\n", + phydev->speed, + phydev->duplex == DUPLEX_FULL ? + "Full" : "Half"); +- else ++ } else { ++ netif_carrier_off(dev); + netdev_info(dev, "link down\n"); ++ } + } + } + +@@ -1033,6 +1036,9 @@ static int macb_open(struct net_device *dev) + + netdev_dbg(bp->dev, "open\n"); + ++ /* carrier starts down */ ++ netif_carrier_off(dev); ++ + /* if the phy is not yet register, retry later*/ + if (!bp->phy_dev) + return -EAGAIN; +@@ -1405,6 +1411,8 @@ static int __init macb_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, dev); + ++ netif_carrier_off(dev); ++ + netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n", + macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr, + dev->irq, dev->dev_addr); +@@ -1468,6 +1476,7 @@ static int macb_suspend(struct platform_device *pdev, pm_message_t state) + struct net_device *netdev = platform_get_drvdata(pdev); + struct macb *bp = netdev_priv(netdev); + ++ netif_carrier_off(netdev); + netif_device_detach(netdev); + + clk_disable(bp->hclk); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0072-ALSA-atmel-ac97c-correct-the-unexpected-behavior-whe.patch b/patches.at91/0072-ALSA-atmel-ac97c-correct-the-unexpected-behavior-whe.patch new file mode 100644 index 000000000000..d8a89a2cc953 --- /dev/null +++ b/patches.at91/0072-ALSA-atmel-ac97c-correct-the-unexpected-behavior-whe.patch @@ -0,0 +1,35 @@ +From dbbe3702cb9bf1aa4e07dc6fe2cce479f75ab39e Mon Sep 17 00:00:00 2001 +From: Bo Shen +Date: Fri, 11 May 2012 17:39:28 +0800 +Subject: ALSA: atmel/ac97c: correct the unexpected behavior when using + uninitial value for reset pin + +When pdata->reset_pin is passed with a negative value (means gpio +is invalid), then chip->reset_pin will not be assigned to a vaule, +it will use default value 0. This will cause unexpected behavior. + +So, add this patch to correct. + +Signed-off-by: Bo Shen +Acked-by: Nicolas Ferre +Signed-off-by: Takashi Iwai +--- + sound/atmel/ac97c.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/atmel/ac97c.c b/sound/atmel/ac97c.c +index 115313e..f5ded64 100644 +--- a/sound/atmel/ac97c.c ++++ b/sound/atmel/ac97c.c +@@ -991,6 +991,8 @@ static int __devinit atmel_ac97c_probe(struct platform_device *pdev) + gpio_direction_output(pdata->reset_pin, 1); + chip->reset_pin = pdata->reset_pin; + } ++ } else { ++ chip->reset_pin = -EINVAL; + } + + snd_card_set_dev(card, &pdev->dev); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0073-MTD-at91-extract-hw-ecc-initialization-to-one-functi.patch b/patches.at91/0073-MTD-at91-extract-hw-ecc-initialization-to-one-functi.patch new file mode 100644 index 000000000000..436c88279c1f --- /dev/null +++ b/patches.at91/0073-MTD-at91-extract-hw-ecc-initialization-to-one-functi.patch @@ -0,0 +1,188 @@ +From 37a9c14614a63c3e5fed9d6cb18638d765a65f80 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Thu, 31 May 2012 18:09:20 +0800 +Subject: MTD: at91: extract hw ecc initialization to one function + +This patch moves hw ecc initialization code to one function. + +Signed-off-by: Hong Xu +Signed-off-by: Josh Wu +--- + drivers/mtd/nand/atmel_nand.c | 127 ++++++++++++++++++++++-------------------- + 1 file changed, 66 insertions(+), 61 deletions(-) + +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index 2165576..4ea0a04 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -523,6 +523,66 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host, + } + #endif + ++static int __init atmel_hw_nand_init_params(struct platform_device *pdev, ++ struct atmel_nand_host *host) ++{ ++ struct mtd_info *mtd = &host->mtd; ++ struct nand_chip *nand_chip = &host->nand_chip; ++ struct resource *regs; ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!regs) { ++ dev_err(host->dev, ++ "Can't get I/O resource regs, use software ECC\n"); ++ nand_chip->ecc.mode = NAND_ECC_SOFT; ++ return 0; ++ } ++ ++ host->ecc = ioremap(regs->start, resource_size(regs)); ++ if (host->ecc == NULL) { ++ dev_err(host->dev, "ioremap failed\n"); ++ return -EIO; ++ } ++ ++ /* ECC is calculated for the whole page (1 step) */ ++ nand_chip->ecc.size = mtd->writesize; ++ ++ /* set ECC page size and oob layout */ ++ switch (mtd->writesize) { ++ case 512: ++ nand_chip->ecc.layout = &atmel_oobinfo_small; ++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); ++ break; ++ case 1024: ++ nand_chip->ecc.layout = &atmel_oobinfo_large; ++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); ++ break; ++ case 2048: ++ nand_chip->ecc.layout = &atmel_oobinfo_large; ++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); ++ break; ++ case 4096: ++ nand_chip->ecc.layout = &atmel_oobinfo_large; ++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); ++ break; ++ default: ++ /* page size not handled by HW ECC */ ++ /* switching back to soft ECC */ ++ nand_chip->ecc.mode = NAND_ECC_SOFT; ++ return 0; ++ } ++ ++ /* set up for HW ECC */ ++ nand_chip->ecc.calculate = atmel_nand_calculate; ++ nand_chip->ecc.correct = atmel_nand_correct; ++ nand_chip->ecc.hwctl = atmel_nand_hwctl; ++ nand_chip->ecc.read_page = atmel_nand_read_page; ++ nand_chip->ecc.bytes = 4; ++ nand_chip->ecc.strength = 1; ++ ++ return 0; ++} ++ + /* + * Probe for the NAND device. + */ +@@ -531,7 +591,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev) + struct atmel_nand_host *host; + struct mtd_info *mtd; + struct nand_chip *nand_chip; +- struct resource *regs; + struct resource *mem; + struct mtd_part_parser_data ppdata = {}; + int res; +@@ -583,29 +642,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev) + nand_chip->dev_ready = atmel_nand_device_ready; + + nand_chip->ecc.mode = host->board.ecc_mode; +- +- regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); +- if (!regs && nand_chip->ecc.mode == NAND_ECC_HW) { +- printk(KERN_ERR "atmel_nand: can't get I/O resource " +- "regs\nFalling back on software ECC\n"); +- nand_chip->ecc.mode = NAND_ECC_SOFT; +- } +- +- if (nand_chip->ecc.mode == NAND_ECC_HW) { +- host->ecc = ioremap(regs->start, resource_size(regs)); +- if (host->ecc == NULL) { +- printk(KERN_ERR "atmel_nand: ioremap failed\n"); +- res = -EIO; +- goto err_ecc_ioremap; +- } +- nand_chip->ecc.calculate = atmel_nand_calculate; +- nand_chip->ecc.correct = atmel_nand_correct; +- nand_chip->ecc.hwctl = atmel_nand_hwctl; +- nand_chip->ecc.read_page = atmel_nand_read_page; +- nand_chip->ecc.bytes = 4; +- nand_chip->ecc.strength = 1; +- } +- + nand_chip->chip_delay = 20; /* 20us command delay time */ + + if (host->board.bus_width_16) /* 16-bit bus width */ +@@ -657,40 +693,9 @@ static int __init atmel_nand_probe(struct platform_device *pdev) + } + + if (nand_chip->ecc.mode == NAND_ECC_HW) { +- /* ECC is calculated for the whole page (1 step) */ +- nand_chip->ecc.size = mtd->writesize; +- +- /* set ECC page size and oob layout */ +- switch (mtd->writesize) { +- case 512: +- nand_chip->ecc.layout = &atmel_oobinfo_small; +- ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); +- break; +- case 1024: +- nand_chip->ecc.layout = &atmel_oobinfo_large; +- ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); +- break; +- case 2048: +- nand_chip->ecc.layout = &atmel_oobinfo_large; +- ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); +- break; +- case 4096: +- nand_chip->ecc.layout = &atmel_oobinfo_large; +- ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); +- break; +- default: +- /* page size not handled by HW ECC */ +- /* switching back to soft ECC */ +- nand_chip->ecc.mode = NAND_ECC_SOFT; +- nand_chip->ecc.calculate = NULL; +- nand_chip->ecc.correct = NULL; +- nand_chip->ecc.hwctl = NULL; +- nand_chip->ecc.read_page = NULL; +- nand_chip->ecc.postpad = 0; +- nand_chip->ecc.prepad = 0; +- nand_chip->ecc.bytes = 0; +- break; +- } ++ res = atmel_hw_nand_init_params(pdev, host); ++ if (res != 0) ++ goto err_hw_ecc; + } + + /* second phase scan */ +@@ -707,15 +712,15 @@ static int __init atmel_nand_probe(struct platform_device *pdev) + return res; + + err_scan_tail: ++ if (host->ecc) ++ iounmap(host->ecc); ++err_hw_ecc: + err_scan_ident: + err_no_card: + atmel_nand_disable(host); + platform_set_drvdata(pdev, NULL); + if (host->dma_chan) + dma_release_channel(host->dma_chan); +- if (host->ecc) +- iounmap(host->ecc); +-err_ecc_ioremap: + iounmap(host->io_base); + err_nand_ioremap: + kfree(host); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0074-MTD-at91-add-dt-parameters-for-Atmel-PMECC.patch b/patches.at91/0074-MTD-at91-add-dt-parameters-for-Atmel-PMECC.patch new file mode 100644 index 000000000000..b1711f6c37c1 --- /dev/null +++ b/patches.at91/0074-MTD-at91-add-dt-parameters-for-Atmel-PMECC.patch @@ -0,0 +1,157 @@ +From 7f3d2c9c00b937d2932b337fe259dd4f56c048b7 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Tue, 26 Jun 2012 17:42:22 +0800 +Subject: MTD: at91: add dt parameters for Atmel PMECC + +Add DT support for PMECC parameters. + +Signed-off-by: Hong Xu +Signed-off-by: Josh Wu +Acked-by: Nicolas Ferre +--- + .../devicetree/bindings/mtd/atmel-nand.txt | 40 ++++++++++++++++- + drivers/mtd/nand/atmel_nand.c | 52 +++++++++++++++++++++- + 2 files changed, 90 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt +index a200695..d555421 100644 +--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt ++++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt +@@ -3,7 +3,9 @@ Atmel NAND flash + Required properties: + - compatible : "atmel,at91rm9200-nand". + - reg : should specify localbus address and size used for the chip, +- and if availlable the ECC. ++ and hardware ECC controller if available. ++ If the hardware ECC is PMECC, it should contain address and size for ++ PMECC, PMECC Error Location controller and ROM which has lookup tables. + - atmel,nand-addr-offset : offset for the address latch. + - atmel,nand-cmd-offset : offset for the command latch. + - #address-cells, #size-cells : Must be present if the device has sub-nodes +@@ -16,6 +18,15 @@ Optional properties: + - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. + Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", + "soft_bch". ++- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware. ++ Only supported by at91sam9x5 or later sam9 product. ++- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC ++ Controller. Supported values are: 2, 4, 8, 12, 24. ++- atmel,pmecc-sector-size : sector size for ECC computation. Supported values ++ are: 512, 1024. ++- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM ++ for different sector size. First one is for sector size 512, the next is for ++ sector size 1024. + - nand-bus-width : 8 or 16 bus width if not present 8 + - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false + +@@ -39,3 +50,30 @@ nand0: nand@40000000,0 { + ... + }; + }; ++ ++/* for PMECC supported chips */ ++nand0: nand@40000000 { ++ compatible = "atmel,at91rm9200-nand"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = < 0x40000000 0x10000000 /* bus addr & size */ ++ 0xffffe000 0x00000600 /* PMECC addr & size */ ++ 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ ++ 0x00100000 0x00100000 /* ROM addr & size */ ++ >; ++ atmel,nand-addr-offset = <21>; /* ale */ ++ atmel,nand-cmd-offset = <22>; /* cle */ ++ nand-on-flash-bbt; ++ nand-ecc-mode = "hw"; ++ atmel,has-pmecc; /* enable PMECC */ ++ atmel,pmecc-cap = <2>; ++ atmel,pmecc-sector-size = <512>; ++ atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; ++ gpios = <&pioD 5 0 /* rdy */ ++ &pioD 4 0 /* nce */ ++ 0 /* cd */ ++ >; ++ partition@0 { ++ ... ++ }; ++}; +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index 4ea0a04..712a705 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -93,6 +93,11 @@ struct atmel_nand_host { + + struct completion comp; + struct dma_chan *dma_chan; ++ ++ bool has_pmecc; ++ u8 pmecc_corr_cap; ++ u16 pmecc_sector_size; ++ u32 pmecc_lookup_table_offset; + }; + + static int cpu_has_dma(void) +@@ -477,7 +482,8 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) + static int __devinit atmel_of_init_port(struct atmel_nand_host *host, + struct device_node *np) + { +- u32 val; ++ u32 val, table_offset; ++ u32 offset[2]; + int ecc_mode; + struct atmel_nand_data *board = &host->board; + enum of_gpio_flags flags; +@@ -513,6 +519,50 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host, + board->enable_pin = of_get_gpio(np, 1); + board->det_pin = of_get_gpio(np, 2); + ++ host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc"); ++ ++ if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc) ++ return 0; /* Not using PMECC */ ++ ++ /* use PMECC, get correction capability, sector size and lookup ++ * table offset. ++ */ ++ if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) { ++ dev_err(host->dev, "Cannot decide PMECC Capability\n"); ++ return -EINVAL; ++ } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) && ++ (val != 24)) { ++ dev_err(host->dev, ++ "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n", ++ val); ++ return -EINVAL; ++ } ++ host->pmecc_corr_cap = (u8)val; ++ ++ if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) { ++ dev_err(host->dev, "Cannot decide PMECC Sector Size\n"); ++ return -EINVAL; ++ } else if ((val != 512) && (val != 1024)) { ++ dev_err(host->dev, ++ "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n", ++ val); ++ return -EINVAL; ++ } ++ host->pmecc_sector_size = (u16)val; ++ ++ if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset", ++ offset, 2) != 0) { ++ dev_err(host->dev, "Cannot get PMECC lookup table offset\n"); ++ return -EINVAL; ++ } ++ table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1]; ++ ++ if (!table_offset) { ++ dev_err(host->dev, "Invalid PMECC lookup table offset\n"); ++ return -EINVAL; ++ } ++ host->pmecc_lookup_table_offset = table_offset; ++ + return 0; + } + #else +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0075-MTD-at91-atmel_nand-Update-driver-to-support-Program.patch b/patches.at91/0075-MTD-at91-atmel_nand-Update-driver-to-support-Program.patch new file mode 100644 index 000000000000..df8ea11c4f2d --- /dev/null +++ b/patches.at91/0075-MTD-at91-atmel_nand-Update-driver-to-support-Program.patch @@ -0,0 +1,959 @@ +From 6dc4ff786c62fa34390607264d4d3ec54e22d5b7 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Fri, 29 Jun 2012 15:29:21 +0800 +Subject: MTD: at91: atmel_nand: Update driver to support Programmable Multibit + ECC controller + +The Programmable Multibit ECC (PMECC) controller is a programmable binary +BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller +can be used to support both SLC and MLC NAND Flash devices. It supports to +generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. + +To use PMECC in this driver, the user needs to set the address and size of +PMECC, PMECC error location controllers and ROM. And also needs to pass the +correction capability, the sector size and ROM lookup table offsets via dt. + +This driver has been tested on AT91SAM9X5-EK and AT91SAM9N12-EK with JFFS2, +YAFFS2, UBIFS and mtd-utils. + +Signed-off-by: Hong Xu +Signed-off-by: Josh Wu +Tested-by: Richard Genoud +Acked-by: Nicolas Ferre +--- + drivers/mtd/nand/atmel_nand.c | 747 +++++++++++++++++++++++++++++++++++++- + drivers/mtd/nand/atmel_nand_ecc.h | 114 +++++- + 2 files changed, 859 insertions(+), 2 deletions(-) + +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index 712a705..42b64fb 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -15,6 +15,8 @@ + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * ++ * Add Programmable Multibit ECC support for various AT91 SoC ++ * (C) Copyright 2012 ATMEL, Hong Xu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +@@ -98,8 +100,31 @@ struct atmel_nand_host { + u8 pmecc_corr_cap; + u16 pmecc_sector_size; + u32 pmecc_lookup_table_offset; ++ ++ int pmecc_bytes_per_sector; ++ int pmecc_sector_number; ++ int pmecc_degree; /* Degree of remainders */ ++ int pmecc_cw_len; /* Length of codeword */ ++ ++ void __iomem *pmerrloc_base; ++ void __iomem *pmecc_rom_base; ++ ++ /* lookup table for alpha_to and index_of */ ++ void __iomem *pmecc_alpha_to; ++ void __iomem *pmecc_index_of; ++ ++ /* data for pmecc computation */ ++ int16_t *pmecc_partial_syn; ++ int16_t *pmecc_si; ++ int16_t *pmecc_smu; /* Sigma table */ ++ int16_t *pmecc_lmu; /* polynomal order */ ++ int *pmecc_mu; ++ int *pmecc_dmu; ++ int *pmecc_delta; + }; + ++static struct nand_ecclayout atmel_pmecc_oobinfo; ++ + static int cpu_has_dma(void) + { + return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); +@@ -293,6 +318,703 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) + } + + /* ++ * Return number of ecc bytes per sector according to sector size and ++ * correction capability ++ * ++ * Following table shows what at91 PMECC supported: ++ * Correction Capability Sector_512_bytes Sector_1024_bytes ++ * ===================== ================ ================= ++ * 2-bits 4-bytes 4-bytes ++ * 4-bits 7-bytes 7-bytes ++ * 8-bits 13-bytes 14-bytes ++ * 12-bits 20-bytes 21-bytes ++ * 24-bits 39-bytes 42-bytes ++ */ ++static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size) ++{ ++ int m = 12 + sector_size / 512; ++ return (m * cap + 7) / 8; ++} ++ ++static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout, ++ int oobsize, int ecc_len) ++{ ++ int i; ++ ++ layout->eccbytes = ecc_len; ++ ++ /* ECC will occupy the last ecc_len bytes continuously */ ++ for (i = 0; i < ecc_len; i++) ++ layout->eccpos[i] = oobsize - ecc_len + i; ++ ++ layout->oobfree[0].offset = 2; ++ layout->oobfree[0].length = ++ oobsize - ecc_len - layout->oobfree[0].offset; ++} ++ ++static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host) ++{ ++ int table_size; ++ ++ table_size = host->pmecc_sector_size == 512 ? ++ PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024; ++ ++ return host->pmecc_rom_base + host->pmecc_lookup_table_offset + ++ table_size * sizeof(int16_t); ++} ++ ++static void pmecc_data_free(struct atmel_nand_host *host) ++{ ++ kfree(host->pmecc_partial_syn); ++ kfree(host->pmecc_si); ++ kfree(host->pmecc_lmu); ++ kfree(host->pmecc_smu); ++ kfree(host->pmecc_mu); ++ kfree(host->pmecc_dmu); ++ kfree(host->pmecc_delta); ++} ++ ++static int __devinit pmecc_data_alloc(struct atmel_nand_host *host) ++{ ++ const int cap = host->pmecc_corr_cap; ++ ++ host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t), ++ GFP_KERNEL); ++ host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL); ++ host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL); ++ host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t), ++ GFP_KERNEL); ++ host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); ++ host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); ++ host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); ++ ++ if (host->pmecc_partial_syn && ++ host->pmecc_si && ++ host->pmecc_lmu && ++ host->pmecc_smu && ++ host->pmecc_mu && ++ host->pmecc_dmu && ++ host->pmecc_delta) ++ return 0; ++ ++ /* error happened */ ++ pmecc_data_free(host); ++ return -ENOMEM; ++} ++ ++static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ int i; ++ uint32_t value; ++ ++ /* Fill odd syndromes */ ++ for (i = 0; i < host->pmecc_corr_cap; i++) { ++ value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2); ++ if (i & 1) ++ value >>= 16; ++ value &= 0xffff; ++ host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value; ++ } ++} ++ ++static void pmecc_substitute(struct mtd_info *mtd) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ int16_t __iomem *alpha_to = host->pmecc_alpha_to; ++ int16_t __iomem *index_of = host->pmecc_index_of; ++ int16_t *partial_syn = host->pmecc_partial_syn; ++ const int cap = host->pmecc_corr_cap; ++ int16_t *si; ++ int i, j; ++ ++ /* si[] is a table that holds the current syndrome value, ++ * an element of that table belongs to the field ++ */ ++ si = host->pmecc_si; ++ ++ memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1)); ++ ++ /* Computation 2t syndromes based on S(x) */ ++ /* Odd syndromes */ ++ for (i = 1; i < 2 * cap; i += 2) { ++ for (j = 0; j < host->pmecc_degree; j++) { ++ if (partial_syn[i] & ((unsigned short)0x1 << j)) ++ si[i] = readw_relaxed(alpha_to + i * j) ^ si[i]; ++ } ++ } ++ /* Even syndrome = (Odd syndrome) ** 2 */ ++ for (i = 2, j = 1; j <= cap; i = ++j << 1) { ++ if (si[j] == 0) { ++ si[i] = 0; ++ } else { ++ int16_t tmp; ++ ++ tmp = readw_relaxed(index_of + si[j]); ++ tmp = (tmp * 2) % host->pmecc_cw_len; ++ si[i] = readw_relaxed(alpha_to + tmp); ++ } ++ } ++ ++ return; ++} ++ ++static void pmecc_get_sigma(struct mtd_info *mtd) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ ++ int16_t *lmu = host->pmecc_lmu; ++ int16_t *si = host->pmecc_si; ++ int *mu = host->pmecc_mu; ++ int *dmu = host->pmecc_dmu; /* Discrepancy */ ++ int *delta = host->pmecc_delta; /* Delta order */ ++ int cw_len = host->pmecc_cw_len; ++ const int16_t cap = host->pmecc_corr_cap; ++ const int num = 2 * cap + 1; ++ int16_t __iomem *index_of = host->pmecc_index_of; ++ int16_t __iomem *alpha_to = host->pmecc_alpha_to; ++ int i, j, k; ++ uint32_t dmu_0_count, tmp; ++ int16_t *smu = host->pmecc_smu; ++ ++ /* index of largest delta */ ++ int ro; ++ int largest; ++ int diff; ++ ++ dmu_0_count = 0; ++ ++ /* First Row */ ++ ++ /* Mu */ ++ mu[0] = -1; ++ ++ memset(smu, 0, sizeof(int16_t) * num); ++ smu[0] = 1; ++ ++ /* discrepancy set to 1 */ ++ dmu[0] = 1; ++ /* polynom order set to 0 */ ++ lmu[0] = 0; ++ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; ++ ++ /* Second Row */ ++ ++ /* Mu */ ++ mu[1] = 0; ++ /* Sigma(x) set to 1 */ ++ memset(&smu[num], 0, sizeof(int16_t) * num); ++ smu[num] = 1; ++ ++ /* discrepancy set to S1 */ ++ dmu[1] = si[1]; ++ ++ /* polynom order set to 0 */ ++ lmu[1] = 0; ++ ++ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; ++ ++ /* Init the Sigma(x) last row */ ++ memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num); ++ ++ for (i = 1; i <= cap; i++) { ++ mu[i + 1] = i << 1; ++ /* Begin Computing Sigma (Mu+1) and L(mu) */ ++ /* check if discrepancy is set to 0 */ ++ if (dmu[i] == 0) { ++ dmu_0_count++; ++ ++ tmp = ((cap - (lmu[i] >> 1) - 1) / 2); ++ if ((cap - (lmu[i] >> 1) - 1) & 0x1) ++ tmp += 2; ++ else ++ tmp += 1; ++ ++ if (dmu_0_count == tmp) { ++ for (j = 0; j <= (lmu[i] >> 1) + 1; j++) ++ smu[(cap + 1) * num + j] = ++ smu[i * num + j]; ++ ++ lmu[cap + 1] = lmu[i]; ++ return; ++ } ++ ++ /* copy polynom */ ++ for (j = 0; j <= lmu[i] >> 1; j++) ++ smu[(i + 1) * num + j] = smu[i * num + j]; ++ ++ /* copy previous polynom order to the next */ ++ lmu[i + 1] = lmu[i]; ++ } else { ++ ro = 0; ++ largest = -1; ++ /* find largest delta with dmu != 0 */ ++ for (j = 0; j < i; j++) { ++ if ((dmu[j]) && (delta[j] > largest)) { ++ largest = delta[j]; ++ ro = j; ++ } ++ } ++ ++ /* compute difference */ ++ diff = (mu[i] - mu[ro]); ++ ++ /* Compute degree of the new smu polynomial */ ++ if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff)) ++ lmu[i + 1] = lmu[i]; ++ else ++ lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2; ++ ++ /* Init smu[i+1] with 0 */ ++ for (k = 0; k < num; k++) ++ smu[(i + 1) * num + k] = 0; ++ ++ /* Compute smu[i+1] */ ++ for (k = 0; k <= lmu[ro] >> 1; k++) { ++ int16_t a, b, c; ++ ++ if (!(smu[ro * num + k] && dmu[i])) ++ continue; ++ a = readw_relaxed(index_of + dmu[i]); ++ b = readw_relaxed(index_of + dmu[ro]); ++ c = readw_relaxed(index_of + smu[ro * num + k]); ++ tmp = a + (cw_len - b) + c; ++ a = readw_relaxed(alpha_to + tmp % cw_len); ++ smu[(i + 1) * num + (k + diff)] = a; ++ } ++ ++ for (k = 0; k <= lmu[i] >> 1; k++) ++ smu[(i + 1) * num + k] ^= smu[i * num + k]; ++ } ++ ++ /* End Computing Sigma (Mu+1) and L(mu) */ ++ /* In either case compute delta */ ++ delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1; ++ ++ /* Do not compute discrepancy for the last iteration */ ++ if (i >= cap) ++ continue; ++ ++ for (k = 0; k <= (lmu[i + 1] >> 1); k++) { ++ tmp = 2 * (i - 1); ++ if (k == 0) { ++ dmu[i + 1] = si[tmp + 3]; ++ } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) { ++ int16_t a, b, c; ++ a = readw_relaxed(index_of + ++ smu[(i + 1) * num + k]); ++ b = si[2 * (i - 1) + 3 - k]; ++ c = readw_relaxed(index_of + b); ++ tmp = a + c; ++ tmp %= cw_len; ++ dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^ ++ dmu[i + 1]; ++ } ++ } ++ } ++ ++ return; ++} ++ ++static int pmecc_err_location(struct mtd_info *mtd) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ unsigned long end_time; ++ const int cap = host->pmecc_corr_cap; ++ const int num = 2 * cap + 1; ++ int sector_size = host->pmecc_sector_size; ++ int err_nbr = 0; /* number of error */ ++ int roots_nbr; /* number of roots */ ++ int i; ++ uint32_t val; ++ int16_t *smu = host->pmecc_smu; ++ ++ pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE); ++ ++ for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) { ++ pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i, ++ smu[(cap + 1) * num + i]); ++ err_nbr++; ++ } ++ ++ val = (err_nbr - 1) << 16; ++ if (sector_size == 1024) ++ val |= 1; ++ ++ pmerrloc_writel(host->pmerrloc_base, ELCFG, val); ++ pmerrloc_writel(host->pmerrloc_base, ELEN, ++ sector_size * 8 + host->pmecc_degree * cap); ++ ++ end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); ++ while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR) ++ & PMERRLOC_CALC_DONE)) { ++ if (unlikely(time_after(jiffies, end_time))) { ++ dev_err(host->dev, "PMECC: Timeout to calculate error location.\n"); ++ return -1; ++ } ++ cpu_relax(); ++ } ++ ++ roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR) ++ & PMERRLOC_ERR_NUM_MASK) >> 8; ++ /* Number of roots == degree of smu hence <= cap */ ++ if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1) ++ return err_nbr - 1; ++ ++ /* Number of roots does not match the degree of smu ++ * unable to correct error */ ++ return -1; ++} ++ ++static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, ++ int sector_num, int extra_bytes, int err_nbr) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ int i = 0; ++ int byte_pos, bit_pos, sector_size, pos; ++ uint32_t tmp; ++ uint8_t err_byte; ++ ++ sector_size = host->pmecc_sector_size; ++ ++ while (err_nbr) { ++ tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1; ++ byte_pos = tmp / 8; ++ bit_pos = tmp % 8; ++ ++ if (byte_pos >= (sector_size + extra_bytes)) ++ BUG(); /* should never happen */ ++ ++ if (byte_pos < sector_size) { ++ err_byte = *(buf + byte_pos); ++ *(buf + byte_pos) ^= (1 << bit_pos); ++ ++ pos = sector_num * host->pmecc_sector_size + byte_pos; ++ dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", ++ pos, bit_pos, err_byte, *(buf + byte_pos)); ++ } else { ++ /* Bit flip in OOB area */ ++ tmp = sector_num * host->pmecc_bytes_per_sector ++ + (byte_pos - sector_size); ++ err_byte = ecc[tmp]; ++ ecc[tmp] ^= (1 << bit_pos); ++ ++ pos = tmp + nand_chip->ecc.layout->eccpos[0]; ++ dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", ++ pos, bit_pos, err_byte, ecc[tmp]); ++ } ++ ++ i++; ++ err_nbr--; ++ } ++ ++ return; ++} ++ ++static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, ++ u8 *ecc) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ int i, err_nbr, eccbytes; ++ uint8_t *buf_pos; ++ ++ eccbytes = nand_chip->ecc.bytes; ++ for (i = 0; i < eccbytes; i++) ++ if (ecc[i] != 0xff) ++ goto normal_check; ++ /* Erased page, return OK */ ++ return 0; ++ ++normal_check: ++ for (i = 0; i < host->pmecc_sector_number; i++) { ++ err_nbr = 0; ++ if (pmecc_stat & 0x1) { ++ buf_pos = buf + i * host->pmecc_sector_size; ++ ++ pmecc_gen_syndrome(mtd, i); ++ pmecc_substitute(mtd); ++ pmecc_get_sigma(mtd); ++ ++ err_nbr = pmecc_err_location(mtd); ++ if (err_nbr == -1) { ++ dev_err(host->dev, "PMECC: Too many errors\n"); ++ mtd->ecc_stats.failed++; ++ return -EIO; ++ } else { ++ pmecc_correct_data(mtd, buf_pos, ecc, i, ++ host->pmecc_bytes_per_sector, err_nbr); ++ mtd->ecc_stats.corrected += err_nbr; ++ } ++ } ++ pmecc_stat >>= 1; ++ } ++ ++ return 0; ++} ++ ++static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, ++ struct nand_chip *chip, uint8_t *buf, int oob_required, int page) ++{ ++ struct atmel_nand_host *host = chip->priv; ++ int eccsize = chip->ecc.size; ++ uint8_t *oob = chip->oob_poi; ++ uint32_t *eccpos = chip->ecc.layout->eccpos; ++ uint32_t stat; ++ unsigned long end_time; ++ ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); ++ pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) ++ & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE); ++ ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); ++ ++ chip->read_buf(mtd, buf, eccsize); ++ chip->read_buf(mtd, oob, mtd->oobsize); ++ ++ end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); ++ while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { ++ if (unlikely(time_after(jiffies, end_time))) { ++ dev_err(host->dev, "PMECC: Timeout to get error status.\n"); ++ return -EIO; ++ } ++ cpu_relax(); ++ } ++ ++ stat = pmecc_readl_relaxed(host->ecc, ISR); ++ if (stat != 0) ++ if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0) ++ return -EIO; ++ ++ return 0; ++} ++ ++static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, ++ struct nand_chip *chip, const uint8_t *buf, int oob_required) ++{ ++ struct atmel_nand_host *host = chip->priv; ++ uint32_t *eccpos = chip->ecc.layout->eccpos; ++ int i, j; ++ unsigned long end_time; ++ ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); ++ ++ pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) | ++ PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE); ++ ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); ++ ++ chip->write_buf(mtd, (u8 *)buf, mtd->writesize); ++ ++ end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); ++ while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { ++ if (unlikely(time_after(jiffies, end_time))) { ++ dev_err(host->dev, "PMECC: Timeout to get ECC value.\n"); ++ return -EIO; ++ } ++ cpu_relax(); ++ } ++ ++ for (i = 0; i < host->pmecc_sector_number; i++) { ++ for (j = 0; j < host->pmecc_bytes_per_sector; j++) { ++ int pos; ++ ++ pos = i * host->pmecc_bytes_per_sector + j; ++ chip->oob_poi[eccpos[pos]] = ++ pmecc_readb_ecc_relaxed(host->ecc, i, j); ++ } ++ } ++ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ return 0; ++} ++ ++static void atmel_pmecc_core_init(struct mtd_info *mtd) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct atmel_nand_host *host = nand_chip->priv; ++ uint32_t val = 0; ++ struct nand_ecclayout *ecc_layout; ++ ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); ++ ++ switch (host->pmecc_corr_cap) { ++ case 2: ++ val = PMECC_CFG_BCH_ERR2; ++ break; ++ case 4: ++ val = PMECC_CFG_BCH_ERR4; ++ break; ++ case 8: ++ val = PMECC_CFG_BCH_ERR8; ++ break; ++ case 12: ++ val = PMECC_CFG_BCH_ERR12; ++ break; ++ case 24: ++ val = PMECC_CFG_BCH_ERR24; ++ break; ++ } ++ ++ if (host->pmecc_sector_size == 512) ++ val |= PMECC_CFG_SECTOR512; ++ else if (host->pmecc_sector_size == 1024) ++ val |= PMECC_CFG_SECTOR1024; ++ ++ switch (host->pmecc_sector_number) { ++ case 1: ++ val |= PMECC_CFG_PAGE_1SECTOR; ++ break; ++ case 2: ++ val |= PMECC_CFG_PAGE_2SECTORS; ++ break; ++ case 4: ++ val |= PMECC_CFG_PAGE_4SECTORS; ++ break; ++ case 8: ++ val |= PMECC_CFG_PAGE_8SECTORS; ++ break; ++ } ++ ++ val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE ++ | PMECC_CFG_AUTO_DISABLE); ++ pmecc_writel(host->ecc, CFG, val); ++ ++ ecc_layout = nand_chip->ecc.layout; ++ pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1); ++ pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]); ++ pmecc_writel(host->ecc, EADDR, ++ ecc_layout->eccpos[ecc_layout->eccbytes - 1]); ++ /* See datasheet about PMECC Clock Control Register */ ++ pmecc_writel(host->ecc, CLK, 2); ++ pmecc_writel(host->ecc, IDR, 0xff); ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); ++} ++ ++static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, ++ struct atmel_nand_host *host) ++{ ++ struct mtd_info *mtd = &host->mtd; ++ struct nand_chip *nand_chip = &host->nand_chip; ++ struct resource *regs, *regs_pmerr, *regs_rom; ++ int cap, sector_size, err_no; ++ ++ cap = host->pmecc_corr_cap; ++ sector_size = host->pmecc_sector_size; ++ dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n", ++ cap, sector_size); ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!regs) { ++ dev_warn(host->dev, ++ "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n"); ++ nand_chip->ecc.mode = NAND_ECC_SOFT; ++ return 0; ++ } ++ ++ host->ecc = ioremap(regs->start, resource_size(regs)); ++ if (host->ecc == NULL) { ++ dev_err(host->dev, "ioremap failed\n"); ++ err_no = -EIO; ++ goto err_pmecc_ioremap; ++ } ++ ++ regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); ++ if (regs_pmerr && regs_rom) { ++ host->pmerrloc_base = ioremap(regs_pmerr->start, ++ resource_size(regs_pmerr)); ++ host->pmecc_rom_base = ioremap(regs_rom->start, ++ resource_size(regs_rom)); ++ } ++ ++ if (!host->pmerrloc_base || !host->pmecc_rom_base) { ++ dev_err(host->dev, ++ "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n"); ++ err_no = -EIO; ++ goto err_pmloc_ioremap; ++ } ++ ++ /* ECC is calculated for the whole page (1 step) */ ++ nand_chip->ecc.size = mtd->writesize; ++ ++ /* set ECC page size and oob layout */ ++ switch (mtd->writesize) { ++ case 2048: ++ host->pmecc_degree = PMECC_GF_DIMENSION_13; ++ host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; ++ host->pmecc_sector_number = mtd->writesize / sector_size; ++ host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes( ++ cap, sector_size); ++ host->pmecc_alpha_to = pmecc_get_alpha_to(host); ++ host->pmecc_index_of = host->pmecc_rom_base + ++ host->pmecc_lookup_table_offset; ++ ++ nand_chip->ecc.steps = 1; ++ nand_chip->ecc.strength = cap; ++ nand_chip->ecc.bytes = host->pmecc_bytes_per_sector * ++ host->pmecc_sector_number; ++ if (nand_chip->ecc.bytes > mtd->oobsize - 2) { ++ dev_err(host->dev, "No room for ECC bytes\n"); ++ err_no = -EINVAL; ++ goto err_no_ecc_room; ++ } ++ pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, ++ mtd->oobsize, ++ nand_chip->ecc.bytes); ++ nand_chip->ecc.layout = &atmel_pmecc_oobinfo; ++ break; ++ case 512: ++ case 1024: ++ case 4096: ++ /* TODO */ ++ dev_warn(host->dev, ++ "Unsupported page size for PMECC, use Software ECC\n"); ++ default: ++ /* page size not handled by HW ECC */ ++ /* switching back to soft ECC */ ++ nand_chip->ecc.mode = NAND_ECC_SOFT; ++ return 0; ++ } ++ ++ /* Allocate data for PMECC computation */ ++ err_no = pmecc_data_alloc(host); ++ if (err_no) { ++ dev_err(host->dev, ++ "Cannot allocate memory for PMECC computation!\n"); ++ goto err_pmecc_data_alloc; ++ } ++ ++ nand_chip->ecc.read_page = atmel_nand_pmecc_read_page; ++ nand_chip->ecc.write_page = atmel_nand_pmecc_write_page; ++ ++ atmel_pmecc_core_init(mtd); ++ ++ return 0; ++ ++err_pmecc_data_alloc: ++err_no_ecc_room: ++err_pmloc_ioremap: ++ iounmap(host->ecc); ++ if (host->pmerrloc_base) ++ iounmap(host->pmerrloc_base); ++ if (host->pmecc_rom_base) ++ iounmap(host->pmecc_rom_base); ++err_pmecc_ioremap: ++ return err_no; ++} ++ ++/* + * Calculate HW ECC + * + * function called after a write +@@ -743,7 +1465,11 @@ static int __init atmel_nand_probe(struct platform_device *pdev) + } + + if (nand_chip->ecc.mode == NAND_ECC_HW) { +- res = atmel_hw_nand_init_params(pdev, host); ++ if (host->has_pmecc) ++ res = atmel_pmecc_nand_init_params(pdev, host); ++ else ++ res = atmel_hw_nand_init_params(pdev, host); ++ + if (res != 0) + goto err_hw_ecc; + } +@@ -762,8 +1488,16 @@ static int __init atmel_nand_probe(struct platform_device *pdev) + return res; + + err_scan_tail: ++ if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) { ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); ++ pmecc_data_free(host); ++ } + if (host->ecc) + iounmap(host->ecc); ++ if (host->pmerrloc_base) ++ iounmap(host->pmerrloc_base); ++ if (host->pmecc_rom_base) ++ iounmap(host->pmecc_rom_base); + err_hw_ecc: + err_scan_ident: + err_no_card: +@@ -789,8 +1523,19 @@ static int __exit atmel_nand_remove(struct platform_device *pdev) + + atmel_nand_disable(host); + ++ if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) { ++ pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); ++ pmerrloc_writel(host->pmerrloc_base, ELDIS, ++ PMERRLOC_DISABLE); ++ pmecc_data_free(host); ++ } ++ + if (host->ecc) + iounmap(host->ecc); ++ if (host->pmecc_rom_base) ++ iounmap(host->pmecc_rom_base); ++ if (host->pmerrloc_base) ++ iounmap(host->pmerrloc_base); + + if (host->dma_chan) + dma_release_channel(host->dma_chan); +diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h +index 578c776..8a1e9a6 100644 +--- a/drivers/mtd/nand/atmel_nand_ecc.h ++++ b/drivers/mtd/nand/atmel_nand_ecc.h +@@ -3,7 +3,7 @@ + * Based on AT91SAM9260 datasheet revision B. + * + * Copyright (C) 2007 Andrew Victor +- * Copyright (C) 2007 Atmel Corporation. ++ * Copyright (C) 2007 - 2012 Atmel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the +@@ -36,4 +36,116 @@ + #define ATMEL_ECC_NPR 0x10 /* NParity register */ + #define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */ + ++/* PMECC Register Definitions */ ++#define ATMEL_PMECC_CFG 0x000 /* Configuration Register */ ++#define PMECC_CFG_BCH_ERR2 (0 << 0) ++#define PMECC_CFG_BCH_ERR4 (1 << 0) ++#define PMECC_CFG_BCH_ERR8 (2 << 0) ++#define PMECC_CFG_BCH_ERR12 (3 << 0) ++#define PMECC_CFG_BCH_ERR24 (4 << 0) ++ ++#define PMECC_CFG_SECTOR512 (0 << 4) ++#define PMECC_CFG_SECTOR1024 (1 << 4) ++ ++#define PMECC_CFG_PAGE_1SECTOR (0 << 8) ++#define PMECC_CFG_PAGE_2SECTORS (1 << 8) ++#define PMECC_CFG_PAGE_4SECTORS (2 << 8) ++#define PMECC_CFG_PAGE_8SECTORS (3 << 8) ++ ++#define PMECC_CFG_READ_OP (0 << 12) ++#define PMECC_CFG_WRITE_OP (1 << 12) ++ ++#define PMECC_CFG_SPARE_ENABLE (1 << 16) ++#define PMECC_CFG_SPARE_DISABLE (0 << 16) ++ ++#define PMECC_CFG_AUTO_ENABLE (1 << 20) ++#define PMECC_CFG_AUTO_DISABLE (0 << 20) ++ ++#define ATMEL_PMECC_SAREA 0x004 /* Spare area size */ ++#define ATMEL_PMECC_SADDR 0x008 /* PMECC starting address */ ++#define ATMEL_PMECC_EADDR 0x00c /* PMECC ending address */ ++#define ATMEL_PMECC_CLK 0x010 /* PMECC clock control */ ++#define PMECC_CLK_133MHZ (2 << 0) ++ ++#define ATMEL_PMECC_CTRL 0x014 /* PMECC control register */ ++#define PMECC_CTRL_RST (1 << 0) ++#define PMECC_CTRL_DATA (1 << 1) ++#define PMECC_CTRL_USER (1 << 2) ++#define PMECC_CTRL_ENABLE (1 << 4) ++#define PMECC_CTRL_DISABLE (1 << 5) ++ ++#define ATMEL_PMECC_SR 0x018 /* PMECC status register */ ++#define PMECC_SR_BUSY (1 << 0) ++#define PMECC_SR_ENABLE (1 << 4) ++ ++#define ATMEL_PMECC_IER 0x01c /* PMECC interrupt enable */ ++#define PMECC_IER_ENABLE (1 << 0) ++#define ATMEL_PMECC_IDR 0x020 /* PMECC interrupt disable */ ++#define PMECC_IER_DISABLE (1 << 0) ++#define ATMEL_PMECC_IMR 0x024 /* PMECC interrupt mask */ ++#define PMECC_IER_MASK (1 << 0) ++#define ATMEL_PMECC_ISR 0x028 /* PMECC interrupt status */ ++#define ATMEL_PMECC_ECCx 0x040 /* PMECC ECC x */ ++#define ATMEL_PMECC_REMx 0x240 /* PMECC REM x */ ++ ++/* PMERRLOC Register Definitions */ ++#define ATMEL_PMERRLOC_ELCFG 0x000 /* Error location config */ ++#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0) ++#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0) ++#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16) ++ ++#define ATMEL_PMERRLOC_ELPRIM 0x004 /* Error location primitive */ ++#define ATMEL_PMERRLOC_ELEN 0x008 /* Error location enable */ ++#define ATMEL_PMERRLOC_ELDIS 0x00c /* Error location disable */ ++#define PMERRLOC_DISABLE (1 << 0) ++ ++#define ATMEL_PMERRLOC_ELSR 0x010 /* Error location status */ ++#define PMERRLOC_ELSR_BUSY (1 << 0) ++#define ATMEL_PMERRLOC_ELIER 0x014 /* Error location int enable */ ++#define ATMEL_PMERRLOC_ELIDR 0x018 /* Error location int disable */ ++#define ATMEL_PMERRLOC_ELIMR 0x01c /* Error location int mask */ ++#define ATMEL_PMERRLOC_ELISR 0x020 /* Error location int status */ ++#define PMERRLOC_ERR_NUM_MASK (0x1f << 8) ++#define PMERRLOC_CALC_DONE (1 << 0) ++#define ATMEL_PMERRLOC_SIGMAx 0x028 /* Error location SIGMA x */ ++#define ATMEL_PMERRLOC_ELx 0x08c /* Error location x */ ++ ++/* Register access macros for PMECC */ ++#define pmecc_readl_relaxed(addr, reg) \ ++ readl_relaxed((addr) + ATMEL_PMECC_##reg) ++ ++#define pmecc_writel(addr, reg, value) \ ++ writel((value), (addr) + ATMEL_PMECC_##reg) ++ ++#define pmecc_readb_ecc_relaxed(addr, sector, n) \ ++ readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n)) ++ ++#define pmecc_readl_rem_relaxed(addr, sector, n) \ ++ readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4)) ++ ++#define pmerrloc_readl_relaxed(addr, reg) \ ++ readl_relaxed((addr) + ATMEL_PMERRLOC_##reg) ++ ++#define pmerrloc_writel(addr, reg, value) \ ++ writel((value), (addr) + ATMEL_PMERRLOC_##reg) ++ ++#define pmerrloc_writel_sigma_relaxed(addr, n, value) \ ++ writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4)) ++ ++#define pmerrloc_readl_sigma_relaxed(addr, n) \ ++ readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4)) ++ ++#define pmerrloc_readl_el_relaxed(addr, n) \ ++ readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4)) ++ ++/* Galois field dimension */ ++#define PMECC_GF_DIMENSION_13 13 ++#define PMECC_GF_DIMENSION_14 14 ++ ++#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000 ++#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000 ++ ++/* Time out value for reading PMECC status register */ ++#define PMECC_MAX_TIMEOUT_MS 100 ++ + #endif +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0076-MTD-nand-add-return-value-for-write_page-write_page_.patch b/patches.at91/0076-MTD-nand-add-return-value-for-write_page-write_page_.patch new file mode 100644 index 000000000000..af5354607adb --- /dev/null +++ b/patches.at91/0076-MTD-nand-add-return-value-for-write_page-write_page_.patch @@ -0,0 +1,153 @@ +From c00279166e428d885fd658d0be8d2419acc87d18 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Mon, 25 Jun 2012 15:15:54 +0800 +Subject: MTD: nand: add return value for write_page()/write_page_raw() + functions in structure of nand_ecc_ctrl. + +There is an implemention of hardware ECC write page function which may return an +error indication. +For instance, using Atmel HW PMECC to write one page into a nand flash, the hardware +engine will compute the BCH ecc code for this page. so we need read a the +status register to theck whether the ecc code is generated. +But we cannot assume the status register always can be ready, for example, +incorrect hardware configuration or hardware issue, in such case we need +write_page() to return a error code. + +Since the definition of 'write_page' function in struct nand_ecc_ctrl is 'void'. +So this patch will: + 1. add return 'int' value for 'write_page' function. + 2. to be consitent, add return 'int' value for 'write_page_raw' fuctions too. + 3. add code to test the return value, and if negative, indicate an + error happend when write page with ECC. + 4. fix the compile warning in all impacted nand flash driver. + +Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. + +Signed-off-by: Josh Wu +--- + drivers/mtd/nand/nand_base.c | 27 +++++++++++++++++++-------- + include/linux/mtd/nand.h | 4 ++-- + 2 files changed, 21 insertions(+), 10 deletions(-) + +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -1922,11 +1922,13 @@ out: + * + * Not for syndrome calculating ECC controllers, which use a special oob layout. + */ +-static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, ++static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) + { + chip->write_buf(mtd, buf, mtd->writesize); + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ return 0; + } + + /** +@@ -1937,7 +1939,7 @@ static void nand_write_page_raw(struct m + * + * We need a special oob layout and handling even when ECC isn't checked. + */ +-static void nand_write_page_raw_syndrome(struct mtd_info *mtd, ++static int nand_write_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) + { +@@ -1967,6 +1969,8 @@ static void nand_write_page_raw_syndrome + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->write_buf(mtd, oob, size); ++ ++ return 0; + } + /** + * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function +@@ -1974,7 +1978,7 @@ static void nand_write_page_raw_syndrome + * @chip: nand chip info structure + * @buf: data buffer + */ +-static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, ++static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) + { + int i, eccsize = chip->ecc.size; +@@ -1991,7 +1995,7 @@ static void nand_write_page_swecc(struct + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + +- chip->ecc.write_page_raw(mtd, chip, buf); ++ return chip->ecc.write_page_raw(mtd, chip, buf); + } + + /** +@@ -2000,7 +2004,7 @@ static void nand_write_page_swecc(struct + * @chip: nand chip info structure + * @buf: data buffer + */ +-static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, ++static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) + { + int i, eccsize = chip->ecc.size; +@@ -2020,6 +2024,8 @@ static void nand_write_page_hwecc(struct + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ return 0; + } + + /** +@@ -2031,7 +2037,7 @@ static void nand_write_page_hwecc(struct + * The hw generator calculates the error syndrome automatically. Therefore we + * need a special oob layout and handling. + */ +-static void nand_write_page_syndrome(struct mtd_info *mtd, ++static int nand_write_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) + { + int i, eccsize = chip->ecc.size; +@@ -2064,6 +2070,8 @@ static void nand_write_page_syndrome(str + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->write_buf(mtd, oob, i); ++ ++ return 0; + } + + /** +@@ -2083,9 +2091,12 @@ static int nand_write_page(struct mtd_in + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + + if (unlikely(raw)) +- chip->ecc.write_page_raw(mtd, chip, buf); ++ status = chip->ecc.write_page_raw(mtd, chip, buf); + else +- chip->ecc.write_page(mtd, chip, buf); ++ status = chip->ecc.write_page(mtd, chip, buf); ++ ++ if (status < 0) ++ return status; + + /* + * Cached progamming disabled for now. Not sure if it's worth the +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -361,13 +361,13 @@ struct nand_ecc_ctrl { + uint8_t *calc_ecc); + int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page); +- void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, ++ int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf); + int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page); + int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, + uint32_t offs, uint32_t len, uint8_t *buf); +- void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, ++ int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf); + int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, + int page); diff --git a/patches.at91/0077-MTD-atmel_nand-revet-the-oob_required-parameter-in-e.patch b/patches.at91/0077-MTD-atmel_nand-revet-the-oob_required-parameter-in-e.patch new file mode 100644 index 000000000000..bdccc954ab88 --- /dev/null +++ b/patches.at91/0077-MTD-atmel_nand-revet-the-oob_required-parameter-in-e.patch @@ -0,0 +1,38 @@ +From 7d92178b306bf2b8020da2a5c53077885e6239f9 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Fri, 21 Sep 2012 15:49:29 +0200 +Subject: MTD: atmel_nand: revet the oob_required parameter in + ecc.read/write_page + +Only for v3.4 compatibility. Do not propagate upstream + +Signed-off-by: Nicolas Ferre +--- + drivers/mtd/nand/atmel_nand.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index 42b64fb..ec0745e 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -759,7 +759,7 @@ normal_check: + } + + static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, +- struct nand_chip *chip, uint8_t *buf, int oob_required, int page) ++ struct nand_chip *chip, uint8_t *buf, int page) + { + struct atmel_nand_host *host = chip->priv; + int eccsize = chip->ecc.size; +@@ -797,7 +797,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, + } + + static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, +- struct nand_chip *chip, const uint8_t *buf, int oob_required) ++ struct nand_chip *chip, const uint8_t *buf) + { + struct atmel_nand_host *host = chip->priv; + uint32_t *eccpos = chip->ecc.layout->eccpos; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0078-MTD-atmel_nand-add-9x5-to-list-of-SoC-with-DMA.patch b/patches.at91/0078-MTD-atmel_nand-add-9x5-to-list-of-SoC-with-DMA.patch new file mode 100644 index 000000000000..052f8ee81486 --- /dev/null +++ b/patches.at91/0078-MTD-atmel_nand-add-9x5-to-list-of-SoC-with-DMA.patch @@ -0,0 +1,28 @@ +From ddee6570ee156ed3d758fbfb0931054d77da29c5 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 24 Sep 2012 14:57:08 +0200 +Subject: MTD: atmel_nand: add 9x5 to list of SoC with DMA + +Temporary: may have to be replaced by a device-tree property. + +Signed-off-by: Nicolas Ferre +--- + drivers/mtd/nand/atmel_nand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index ec0745e..a5c184e 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -127,7 +127,7 @@ static struct nand_ecclayout atmel_pmecc_oobinfo; + + static int cpu_has_dma(void) + { +- return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); ++ return cpu_is_at91sam9rl() || cpu_is_at91sam9g45() || cpu_is_at91sam9x5(); + } + + /* +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0079-MTD-atmel_nand-POI-fall-back-is-not-an-issue-change-.patch b/patches.at91/0079-MTD-atmel_nand-POI-fall-back-is-not-an-issue-change-.patch new file mode 100644 index 000000000000..cbecb401cca4 --- /dev/null +++ b/patches.at91/0079-MTD-atmel_nand-POI-fall-back-is-not-an-issue-change-.patch @@ -0,0 +1,26 @@ +From 3efc10bd73879d566ad573e6ce4419fb79d9eda0 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 24 Sep 2012 15:07:06 +0200 +Subject: MTD: atmel_nand: POI fall back is not an issue: change log + +Signed-off-by: Nicolas Ferre +--- + drivers/mtd/nand/atmel_nand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index a5c184e..17ef011 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -281,7 +281,7 @@ err_dma: + dma_unmap_single(dma_dev->dev, phys_addr, len, dir); + err_buf: + if (err != 0) +- dev_warn(host->dev, "Fall back to CPU I/O\n"); ++ dev_dbg(host->dev, "Fall back to CPU I/O\n"); + return err; + } + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0080-MTD-atmel_nand-add-9n12-to-list-of-SoC-with-DMA.patch b/patches.at91/0080-MTD-atmel_nand-add-9n12-to-list-of-SoC-with-DMA.patch new file mode 100644 index 000000000000..0b9ce93686f3 --- /dev/null +++ b/patches.at91/0080-MTD-atmel_nand-add-9n12-to-list-of-SoC-with-DMA.patch @@ -0,0 +1,29 @@ +From 6d16ae9b0f776651f60af120bb799d77504a2703 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 8 Oct 2012 16:55:29 +0200 +Subject: MTD: atmel_nand: add 9n12 to list of SoC with DMA + +Temporary: may have to be replaced by a device-tree property. + +Signed-off-by: Nicolas Ferre +--- + drivers/mtd/nand/atmel_nand.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c +index 17ef011..b1158b4 100644 +--- a/drivers/mtd/nand/atmel_nand.c ++++ b/drivers/mtd/nand/atmel_nand.c +@@ -127,7 +127,8 @@ static struct nand_ecclayout atmel_pmecc_oobinfo; + + static int cpu_has_dma(void) + { +- return cpu_is_at91sam9rl() || cpu_is_at91sam9g45() || cpu_is_at91sam9x5(); ++ return cpu_is_at91sam9rl() || cpu_is_at91sam9g45() ++ || cpu_is_at91sam9x5() || cpu_is_at91sam9n12(); + } + + /* +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0081-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch b/patches.at91/0081-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch new file mode 100644 index 000000000000..e0fbdeb181a8 --- /dev/null +++ b/patches.at91/0081-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch @@ -0,0 +1,392 @@ +From 205e3ae2e153f8cd611e980d02c5ca629e726f06 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Wed, 17 Nov 2010 12:28:13 +0100 +Subject: input: atmel_tsadcc: add support for ARCH_AT91SAM9X5 + +XXX: split header creation in a new patch (or don't do it) + +Signed-off-by: Josh Wu +--- + drivers/input/touchscreen/atmel_tsadcc.c | 150 ++++++++++++---------------- + drivers/input/touchscreen/atmel_tsadcc.h | 162 +++++++++++++++++++++++++++++++ + 2 files changed, 222 insertions(+), 90 deletions(-) + create mode 100644 drivers/input/touchscreen/atmel_tsadcc.h + +diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c +index 201b2d2..a0e8d52 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.c ++++ b/drivers/input/touchscreen/atmel_tsadcc.c +@@ -25,74 +25,9 @@ + #include + #include + +-/* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */ +- +-#define ATMEL_TSADCC_CR 0x00 /* Control register */ +-#define ATMEL_TSADCC_SWRST (1 << 0) /* Software Reset*/ +-#define ATMEL_TSADCC_START (1 << 1) /* Start conversion */ +- +-#define ATMEL_TSADCC_MR 0x04 /* Mode register */ +-#define ATMEL_TSADCC_TSAMOD (3 << 0) /* ADC mode */ +-#define ATMEL_TSADCC_TSAMOD_ADC_ONLY_MODE (0x0) /* ADC Mode */ +-#define ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE (0x1) /* Touch Screen Only Mode */ +-#define ATMEL_TSADCC_LOWRES (1 << 4) /* Resolution selection */ +-#define ATMEL_TSADCC_SLEEP (1 << 5) /* Sleep mode */ +-#define ATMEL_TSADCC_PENDET (1 << 6) /* Pen Detect selection */ +-#define ATMEL_TSADCC_PRES (1 << 7) /* Pressure Measurement Selection */ +-#define ATMEL_TSADCC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ +-#define ATMEL_TSADCC_EPRESCAL (0xff << 8) /* Prescalar Rate Selection (Extended) */ +-#define ATMEL_TSADCC_STARTUP (0x7f << 16) /* Start Up time */ +-#define ATMEL_TSADCC_SHTIM (0xf << 24) /* Sample & Hold time */ +-#define ATMEL_TSADCC_PENDBC (0xf << 28) /* Pen Detect debouncing time */ +- +-#define ATMEL_TSADCC_TRGR 0x08 /* Trigger register */ +-#define ATMEL_TSADCC_TRGMOD (7 << 0) /* Trigger mode */ +-#define ATMEL_TSADCC_TRGMOD_NONE (0 << 0) +-#define ATMEL_TSADCC_TRGMOD_EXT_RISING (1 << 0) +-#define ATMEL_TSADCC_TRGMOD_EXT_FALLING (2 << 0) +-#define ATMEL_TSADCC_TRGMOD_EXT_ANY (3 << 0) +-#define ATMEL_TSADCC_TRGMOD_PENDET (4 << 0) +-#define ATMEL_TSADCC_TRGMOD_PERIOD (5 << 0) +-#define ATMEL_TSADCC_TRGMOD_CONTINUOUS (6 << 0) +-#define ATMEL_TSADCC_TRGPER (0xffff << 16) /* Trigger period */ +- +-#define ATMEL_TSADCC_TSR 0x0C /* Touch Screen register */ +-#define ATMEL_TSADCC_TSFREQ (0xf << 0) /* TS Frequency in Interleaved mode */ +-#define ATMEL_TSADCC_TSSHTIM (0xf << 24) /* Sample & Hold time */ +- +-#define ATMEL_TSADCC_CHER 0x10 /* Channel Enable register */ +-#define ATMEL_TSADCC_CHDR 0x14 /* Channel Disable register */ +-#define ATMEL_TSADCC_CHSR 0x18 /* Channel Status register */ +-#define ATMEL_TSADCC_CH(n) (1 << (n)) /* Channel number */ +- +-#define ATMEL_TSADCC_SR 0x1C /* Status register */ +-#define ATMEL_TSADCC_EOC(n) (1 << ((n)+0)) /* End of conversion for channel N */ +-#define ATMEL_TSADCC_OVRE(n) (1 << ((n)+8)) /* Overrun error for channel N */ +-#define ATMEL_TSADCC_DRDY (1 << 16) /* Data Ready */ +-#define ATMEL_TSADCC_GOVRE (1 << 17) /* General Overrun Error */ +-#define ATMEL_TSADCC_ENDRX (1 << 18) /* End of RX Buffer */ +-#define ATMEL_TSADCC_RXBUFF (1 << 19) /* TX Buffer full */ +-#define ATMEL_TSADCC_PENCNT (1 << 20) /* Pen contact */ +-#define ATMEL_TSADCC_NOCNT (1 << 21) /* No contact */ +- +-#define ATMEL_TSADCC_LCDR 0x20 /* Last Converted Data register */ +-#define ATMEL_TSADCC_DATA (0x3ff << 0) /* Channel data */ +- +-#define ATMEL_TSADCC_IER 0x24 /* Interrupt Enable register */ +-#define ATMEL_TSADCC_IDR 0x28 /* Interrupt Disable register */ +-#define ATMEL_TSADCC_IMR 0x2C /* Interrupt Mask register */ +-#define ATMEL_TSADCC_CDR0 0x30 /* Channel Data 0 */ +-#define ATMEL_TSADCC_CDR1 0x34 /* Channel Data 1 */ +-#define ATMEL_TSADCC_CDR2 0x38 /* Channel Data 2 */ +-#define ATMEL_TSADCC_CDR3 0x3C /* Channel Data 3 */ +-#define ATMEL_TSADCC_CDR4 0x40 /* Channel Data 4 */ +-#define ATMEL_TSADCC_CDR5 0x44 /* Channel Data 5 */ +- +-#define ATMEL_TSADCC_XPOS 0x50 +-#define ATMEL_TSADCC_Z1DAT 0x54 +-#define ATMEL_TSADCC_Z2DAT 0x58 +- +-#define PRESCALER_VAL(x) ((x) >> 8) ++#include "atmel_tsadcc.h" ++ ++#define cpu_has_9x5_adc() (cpu_is_at91sam9x5()) + + #define ADC_DEFAULT_CLOCK 100000 + +@@ -124,12 +59,17 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + + if (status & ATMEL_TSADCC_NOCNT) { + /* Contact lost */ +- reg = atmel_tsadcc_read(ATMEL_TSADCC_MR) | ATMEL_TSADCC_PENDBC; +- +- atmel_tsadcc_write(ATMEL_TSADCC_MR, reg); ++ if (cpu_has_9x5_adc()) { ++ /* 9X5 using TSMR to set PENDBC time */ ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR) | ATMEL_TSADCC_PENDBC; ++ atmel_tsadcc_write(ATMEL_TSADCC_TSMR, reg); ++ } else { ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_MR) | ATMEL_TSADCC_PENDBC; ++ atmel_tsadcc_write(ATMEL_TSADCC_MR, reg); ++ } + atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE); + atmel_tsadcc_write(ATMEL_TSADCC_IDR, +- ATMEL_TSADCC_EOC(3) | ATMEL_TSADCC_NOCNT); ++ ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT); + atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT); + + input_report_key(input_dev, BTN_TOUCH, 0); +@@ -138,23 +78,31 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + + } else if (status & ATMEL_TSADCC_PENCNT) { + /* Pen detected */ +- reg = atmel_tsadcc_read(ATMEL_TSADCC_MR); +- reg &= ~ATMEL_TSADCC_PENDBC; ++ if (cpu_has_9x5_adc()) { ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR); ++ reg &= ~ATMEL_TSADCC_PENDBC; ++ atmel_tsadcc_write(ATMEL_TSADCC_TSMR, reg); ++ } else { ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_MR); ++ reg &= ~ATMEL_TSADCC_PENDBC; ++ atmel_tsadcc_write(ATMEL_TSADCC_MR, reg); ++ } + + atmel_tsadcc_write(ATMEL_TSADCC_IDR, ATMEL_TSADCC_PENCNT); +- atmel_tsadcc_write(ATMEL_TSADCC_MR, reg); + atmel_tsadcc_write(ATMEL_TSADCC_IER, +- ATMEL_TSADCC_EOC(3) | ATMEL_TSADCC_NOCNT); ++ ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT); + atmel_tsadcc_write(ATMEL_TSADCC_TRGR, + ATMEL_TSADCC_TRGMOD_PERIOD | (0x0FFF << 16)); + +- } else if (status & ATMEL_TSADCC_EOC(3)) { ++ } else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) { + /* Conversion finished */ + + if (ts_dev->bufferedmeasure) { + /* Last measurement is always discarded, since it can + * be erroneous. + * Always report previous measurement */ ++ dev_dbg(&input_dev->dev, "x = %d, y = %d\n", ++ ts_dev->prev_absx, ts_dev->prev_absy); + input_report_abs(input_dev, ABS_X, ts_dev->prev_absx); + input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy); + input_report_key(input_dev, BTN_TOUCH, 1); +@@ -163,11 +111,16 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + ts_dev->bufferedmeasure = 1; + + /* Now make new measurement */ +- ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_CDR3) << 10; +- ts_dev->prev_absx /= atmel_tsadcc_read(ATMEL_TSADCC_CDR2); +- +- ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_CDR1) << 10; +- ts_dev->prev_absy /= atmel_tsadcc_read(ATMEL_TSADCC_CDR0); ++ if (cpu_has_9x5_adc()) { ++ ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR) & 0xffff; ++ ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR) & 0xffff; ++ } else { ++ ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_CDR3) << 10; ++ ts_dev->prev_absx /= atmel_tsadcc_read(ATMEL_TSADCC_CDR2); ++ ++ ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_CDR1) << 10; ++ ts_dev->prev_absy /= atmel_tsadcc_read(ATMEL_TSADCC_CDR0); ++ } + } + + return IRQ_HANDLED; +@@ -284,18 +237,35 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + + dev_info(&pdev->dev, "Prescaler is set at: %d\n", prsc); + +- reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE | +- ((0x00 << 5) & ATMEL_TSADCC_SLEEP) | /* Normal Mode */ +- ((0x01 << 6) & ATMEL_TSADCC_PENDET) | /* Enable Pen Detect */ +- (prsc << 8) | +- ((0x26 << 16) & ATMEL_TSADCC_STARTUP) | +- ((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC); ++ if (cpu_has_9x5_adc()) { ++ reg = ((0x01 << 5) & ATMEL_TSADCC_SLEEP) | /* Sleep Mode */ ++ (prsc << 8) | ++ ((0x8 << 16) & ATMEL_TSADCC_STARTUP) | ++ ((pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TRACKTIM); ++ } else { ++ reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE | ++ ((0x00 << 5) & ATMEL_TSADCC_SLEEP) | /* Normal Mode */ ++ ((0x01 << 6) & ATMEL_TSADCC_PENDET) | /* Enable Pen Detect */ ++ (prsc << 8) | ++ ((0x26 << 16) & ATMEL_TSADCC_STARTUP) | ++ ((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC); ++ } + + atmel_tsadcc_write(ATMEL_TSADCC_CR, ATMEL_TSADCC_SWRST); + atmel_tsadcc_write(ATMEL_TSADCC_MR, reg); + atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE); +- atmel_tsadcc_write(ATMEL_TSADCC_TSR, +- (pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM); ++ ++ if (cpu_has_9x5_adc()) { ++ atmel_tsadcc_write(ATMEL_TSADCC_TSMR, ++ ATMEL_TSADCC_TSMODE_4WIRE_NO_PRESS | ++ ATMEL_TSADCC_NOTSDMA | ++ ATMEL_TSADCC_PENDET_ENA | ++ (pdata->pendet_debounce << 28) | ++ (0x0 << 8)); ++ } else { ++ atmel_tsadcc_write(ATMEL_TSADCC_TSR, ++ (pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM); ++ } + + atmel_tsadcc_read(ATMEL_TSADCC_SR); + atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT); +diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h +new file mode 100644 +index 0000000..5918c20 +--- /dev/null ++++ b/drivers/input/touchscreen/atmel_tsadcc.h +@@ -0,0 +1,162 @@ ++/* ++ * Header file for AT91/AT32 ADC + touchscreen Controller ++ * ++ * Data structure and register user interface ++ * ++ * Copyright (C) 2010 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ATMEL_TSADCC_H__ ++#define __ATMEL_TSADCC_H__ ++ ++/* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */ ++#define ATMEL_TSADCC_CR 0x00 /* Control register */ ++#define ATMEL_TSADCC_SWRST (1 << 0) /* Software Reset*/ ++#define ATMEL_TSADCC_START (1 << 1) /* Start conversion */ ++ ++#define ATMEL_TSADCC_MR 0x04 /* Mode register */ ++#define ATMEL_TSADCC_TSAMOD (3 << 0) /* ADC mode */ ++#define ATMEL_TSADCC_TSAMOD_ADC_ONLY_MODE (0x0) /* ADC Mode */ ++#define ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE (0x1) /* Touch Screen Only Mode */ ++#define ATMEL_TSADCC_LOWRES (1 << 4) /* Resolution selection */ ++#define ATMEL_TSADCC_SLEEP (1 << 5) /* Sleep mode */ ++#define ATMEL_TSADCC_PENDET (1 << 6) /* Pen Detect selection */ ++#define ATMEL_TSADCC_PRES (1 << 7) /* Pressure Measurement Selection */ ++#define ATMEL_TSADCC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ ++#define ATMEL_TSADCC_EPRESCAL (0xff << 8) /* Prescalar Rate Selection (Extended) */ ++#define ATMEL_TSADCC_STARTUP (0x7f << 16) /* Start Up time */ ++#define ATMEL_TSADCC_SHTIM (0xf << 24) /* Sample & Hold time */ ++#define ATMEL_TSADCC_PENDBC (0xf << 28) /* Pen Detect debouncing time */ ++ ++#define ATMEL_TSADCC_TRGR 0x08 /* Trigger register */ ++#define ATMEL_TSADCC_TRGMOD (7 << 0) /* Trigger mode */ ++#define ATMEL_TSADCC_TRGMOD_NONE (0 << 0) ++#define ATMEL_TSADCC_TRGMOD_EXT_RISING (1 << 0) ++#define ATMEL_TSADCC_TRGMOD_EXT_FALLING (2 << 0) ++#define ATMEL_TSADCC_TRGMOD_EXT_ANY (3 << 0) ++#define ATMEL_TSADCC_TRGMOD_PENDET (4 << 0) ++#define ATMEL_TSADCC_TRGMOD_PERIOD (5 << 0) ++#define ATMEL_TSADCC_TRGMOD_CONTINUOUS (6 << 0) ++#define ATMEL_TSADCC_TRGPER (0xffff << 16) /* Trigger period */ ++ ++#define ATMEL_TSADCC_TSR 0x0C /* Touch Screen register */ ++#define ATMEL_TSADCC_TSFREQ (0xf << 0) /* TS Frequency in Interleaved mode */ ++#define ATMEL_TSADCC_TSSHTIM (0xf << 24) /* Sample & Hold time */ ++ ++#define ATMEL_TSADCC_CHER 0x10 /* Channel Enable register */ ++#define ATMEL_TSADCC_CHDR 0x14 /* Channel Disable register */ ++#define ATMEL_TSADCC_CHSR 0x18 /* Channel Status register */ ++#define ATMEL_TSADCC_CH(n) (1 << (n)) /* Channel number */ ++ ++#define ATMEL_TSADCC_SR 0x1C /* Status register */ ++#define ATMEL_TSADCC_EOC(n) (1 << ((n)+0)) /* End of conversion for channel N */ ++#define ATMEL_TSADCC_OVRE(n) (1 << ((n)+8)) /* Overrun error for channel N */ ++#define ATMEL_TSADCC_DRDY (1 << 16) /* Data Ready */ ++#define ATMEL_TSADCC_GOVRE (1 << 17) /* General Overrun Error */ ++#define ATMEL_TSADCC_ENDRX (1 << 18) /* End of RX Buffer */ ++#define ATMEL_TSADCC_RXBUFF (1 << 19) /* TX Buffer full */ ++#define ATMEL_TSADCC_PENCNT (1 << 20) /* Pen contact */ ++#define ATMEL_TSADCC_NOCNT (1 << 21) /* No contact */ ++ ++#define ATMEL_TSADCC_LCDR 0x20 /* Last Converted Data register */ ++#define ATMEL_TSADCC_DATA (0x3ff << 0) /* Channel data */ ++ ++#define ATMEL_TSADCC_IER 0x24 /* Interrupt Enable register */ ++#define ATMEL_TSADCC_IDR 0x28 /* Interrupt Disable register */ ++#define ATMEL_TSADCC_IMR 0x2C /* Interrupt Mask register */ ++#define ATMEL_TSADCC_CDR0 0x30 /* Channel Data 0 */ ++#define ATMEL_TSADCC_CDR1 0x34 /* Channel Data 1 */ ++#define ATMEL_TSADCC_CDR2 0x38 /* Channel Data 2 */ ++#define ATMEL_TSADCC_CDR3 0x3C /* Channel Data 3 */ ++#define ATMEL_TSADCC_CDR4 0x40 /* Channel Data 4 */ ++#define ATMEL_TSADCC_CDR5 0x44 /* Channel Data 5 */ ++ ++#define ATMEL_TSADCC_XPOS 0x50 ++#define ATMEL_TSADCC_Z1DAT 0x54 ++#define ATMEL_TSADCC_Z2DAT 0x58 ++ ++#define ATMEL_TSADCC_CONVERSION_END (ATMEL_TSADCC_EOC(3)) ++ ++/* Register definitions based on AT91SAM9X5 preliminary draft datasheet */ ++#define ATMEL_TSADCC_TRACKTIM (0x0f << 24) /* Tracking Time */ ++ ++#define ATMEL_TSADCC_ISR 0x30 /* Interrupt Status register */ ++#define ATMEL_TSADCC_XRDY (1 << 20) /* Measure XPOS Ready */ ++#define ATMEL_TSADCC_YRDY (1 << 21) /* Measure YPOS Ready */ ++#define ATMEL_TSADCC_PRDY (1 << 22) /* Measure Pressure Ready */ ++#define ATMEL_TSADCC_COMPE (1 << 26) /* Comparison Event */ ++#define ATMEL_TSADCC_PEN (1 << 29) /* Pen Contact */ ++#define ATMEL_TSADCC_NOPEN (1 << 30) /* No Pen Contact */ ++#define ATMEL_TSADCC_PENDET_STATUS (1 << 31) /* Pen Detect Status (not interrupt source) */ ++ ++#define ATMEL_TSADCC_TSMR 0xb0 ++#define ATMEL_TSADCC_TSMODE (3 << 0) /* Touch Screen Mode */ ++#define ATMEL_TSADCC_TSMODE_NO (0 << 0) /* No Touch Screen */ ++#define ATMEL_TSADCC_TSMODE_4WIRE_NO_PRESS (1 << 0) /* 4-wire Touch Screen without pressure measurement */ ++#define ATMEL_TSADCC_TSMODE_4WIRE_PRESS (2 << 0) /* 4-wire Touch Screen with pressure measurement */ ++#define ATMEL_TSADCC_TSMODE_5WIRE (3 << 0) /* 5-wire Touch Screen */ ++#define ATMEL_TSADCC_TSAV (3 << 4) /* Touch Screen Average */ ++#define ATMEL_TSADCC_TSAV_1 (0 << 4) /* No filtering. Only one conversion ADC per measure */ ++#define ATMEL_TSADCC_TSAV_2 (1 << 4) /* Averages 2 ADC conversions */ ++#define ATMEL_TSADCC_TSAV_4 (2 << 4) /* Averages 4 ADC conversions */ ++#define ATMEL_TSADCC_TSAV_8 (3 << 4) /* Averages 8 ADC conversions */ ++#define ATMEL_TSADCC_TSSCTIM (0x0f << 16) /* Touch Screen switches closure time */ ++ ++#define ATMEL_TSADCC_NOTSDMA (1 << 22) /* No Touchscreen DMA */ ++#define ATMEL_TSADCC_PENDET_DIS (0 << 24) /* Pen contact detection disable */ ++#define ATMEL_TSADCC_PENDET_ENA (1 << 24) /* Pen contact detection enable */ ++ ++#define ATMEL_TSADCC_XPOSR 0xb4 ++#define ATMEL_TSADCC_XSCALE (0x3ff << 16) /* Scale of X Position */ ++ ++#define ATMEL_TSADCC_YPOSR 0xb8 ++#define ATMEL_TSADCC_YPOS (0x3ff << 0) /* Y Position */ ++#define ATMEL_TSADCC_YSCALE (0x3ff << 16) /* Scale of Y Position */ ++ ++/* 9x5 ADC registers which conflict with previous definition */ ++#ifdef CONFIG_ARCH_AT91SAM9X5 ++#undef ATMEL_TSADCC_TRGR ++#undef ATMEL_TSADCC_SR ++#define ATMEL_TSADCC_SR ATMEL_TSADCC_ISR ++#define ATMEL_TSADCC_TRGR 0xc0 ++ ++/* For code compatiable, redefine with 9x5 value */ ++#undef ATMEL_TSADCC_STARTUP ++#define ATMEL_TSADCC_STARTUP (0x0f << 16) /* Startup Time */ ++#undef ATMEL_TSADCC_DRDY ++#define ATMEL_TSADCC_DRDY (1 << 24) /* Data Ready */ ++#undef ATMEL_TSADCC_GOVRE ++#define ATMEL_TSADCC_GOVRE (1 << 25) /* General Overrun */ ++#undef ATMEL_TSADCC_TSFREQ ++#define ATMEL_TSADCC_TSFREQ (0x0f << 8) /* Touch Screen Frequency */ ++#undef ATMEL_TSADCC_PENDET ++#define ATMEL_TSADCC_PENDET (1 << 24) /* Pen Contact Detection Enable */ ++#undef ATMEL_TSADCC_XPOS ++#define ATMEL_TSADCC_XPOS (0x3ff << 0) /* X Position */ ++ ++#undef ATMEL_TSADCC_NOCNT ++#define ATMEL_TSADCC_NOCNT ATMEL_TSADCC_NOPEN ++#undef ATMEL_TSADCC_PENCNT ++#define ATMEL_TSADCC_PENCNT ATMEL_TSADCC_PEN ++#undef ATMEL_TSADCC_CONVERSION_END ++#define ATMEL_TSADCC_CONVERSION_END (ATMEL_TSADCC_XRDY | ATMEL_TSADCC_YRDY | ATMEL_TSADCC_PRDY) ++ ++#endif ++ ++/* Retrieve prescaler value */ ++#define PRESCALER_VAL(x) ((x) >> 8) ++ ++#endif /* __ATMEL_TSADCC_H__ */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0082-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch b/patches.at91/0082-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch new file mode 100644 index 000000000000..c9e593440224 --- /dev/null +++ b/patches.at91/0082-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch @@ -0,0 +1,104 @@ +From f924876dcc5572639dbb81e2e148cc84066f9571 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Wed, 17 Nov 2010 13:12:11 +0100 +Subject: input: atmel_tsadcc: add touch screen pressure measurement + +Signed-off-by: Josh Wu +--- + drivers/input/touchscreen/atmel_tsadcc.c | 26 +++++++++++++++++++++++--- + drivers/input/touchscreen/atmel_tsadcc.h | 4 ++++ + 2 files changed, 27 insertions(+), 3 deletions(-) + +diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c +index a0e8d52..b6a1630 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.c ++++ b/drivers/input/touchscreen/atmel_tsadcc.c +@@ -38,6 +38,7 @@ struct atmel_tsadcc { + int irq; + unsigned int prev_absx; + unsigned int prev_absy; ++ unsigned int prev_absz; + unsigned char bufferedmeasure; + }; + +@@ -53,6 +54,9 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + + unsigned int status; + unsigned int reg; ++ unsigned int z1, z2; ++ unsigned int Rxp = 1; ++ unsigned int factor = 1000; + + status = atmel_tsadcc_read(ATMEL_TSADCC_SR); + status &= atmel_tsadcc_read(ATMEL_TSADCC_IMR); +@@ -101,11 +105,15 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + /* Last measurement is always discarded, since it can + * be erroneous. + * Always report previous measurement */ +- dev_dbg(&input_dev->dev, "x = %d, y = %d\n", +- ts_dev->prev_absx, ts_dev->prev_absy); ++ dev_dbg(&input_dev->dev, ++ "x = %d, y = %d, pressure = %d\n", ++ ts_dev->prev_absx, ts_dev->prev_absy, ++ ts_dev->prev_absz); + input_report_abs(input_dev, ABS_X, ts_dev->prev_absx); + input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy); + input_report_key(input_dev, BTN_TOUCH, 1); ++ if (cpu_has_9x5_adc()) ++ input_report_abs(input_dev, ABS_PRESSURE, ts_dev->prev_absz); + input_sync(input_dev); + } else + ts_dev->bufferedmeasure = 1; +@@ -114,6 +122,17 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + if (cpu_has_9x5_adc()) { + ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR) & 0xffff; + ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR) & 0xffff; ++ ++ /* calculate the pressure */ ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_PRESSR); ++ z1 = reg & ATMEL_TSADCC_PRESSR_Z1; ++ z2 = (reg & ATMEL_TSADCC_PRESSR_Z2) >> 16; ++ ++ if (z1 != 0) ++ ts_dev->prev_absz = Rxp * (ts_dev->prev_absx * factor / 1024) * (z2 * factor / z1 - factor) / factor; ++ else ++ ts_dev->prev_absz = 0; ++ + } else { + ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_CDR3) << 10; + ts_dev->prev_absx /= atmel_tsadcc_read(ATMEL_TSADCC_CDR2); +@@ -209,6 +228,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + __set_bit(EV_ABS, input_dev->evbit); + input_set_abs_params(input_dev, ABS_X, 0, 0x3FF, 0, 0); + input_set_abs_params(input_dev, ABS_Y, 0, 0x3FF, 0, 0); ++ input_set_abs_params(input_dev, ABS_PRESSURE, 0, 0xffffff, 0, 0); + + input_set_capability(input_dev, EV_KEY, BTN_TOUCH); + +@@ -257,7 +277,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + + if (cpu_has_9x5_adc()) { + atmel_tsadcc_write(ATMEL_TSADCC_TSMR, +- ATMEL_TSADCC_TSMODE_4WIRE_NO_PRESS | ++ ATMEL_TSADCC_TSMODE_4WIRE_PRESS | + ATMEL_TSADCC_NOTSDMA | + ATMEL_TSADCC_PENDET_ENA | + (pdata->pendet_debounce << 28) | +diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h +index 5918c20..231497e 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.h ++++ b/drivers/input/touchscreen/atmel_tsadcc.h +@@ -126,6 +126,10 @@ + #define ATMEL_TSADCC_YPOS (0x3ff << 0) /* Y Position */ + #define ATMEL_TSADCC_YSCALE (0x3ff << 16) /* Scale of Y Position */ + ++#define ATMEL_TSADCC_PRESSR 0xbc /* Touchscreen Pressure Register */ ++#define ATMEL_TSADCC_PRESSR_Z1 (0x3ff << 0) /* Data of Z1 Measurement */ ++#define ATMEL_TSADCC_PRESSR_Z2 (0x3ff << 16) /* Data of Z2 Measurement */ ++ + /* 9x5 ADC registers which conflict with previous definition */ + #ifdef CONFIG_ARCH_AT91SAM9X5 + #undef ATMEL_TSADCC_TRGR +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0083-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch b/patches.at91/0083-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch new file mode 100644 index 000000000000..f368baf433b5 --- /dev/null +++ b/patches.at91/0083-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch @@ -0,0 +1,77 @@ +From c331326e3dcab10a8930f9f685bec700ec0d604a Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Tue, 5 Apr 2011 17:30:03 +0200 +Subject: input: atmel_tsadcc: enable touchscreen averaging and add fast wake + up + +Enable the touchscreen average to improve the resulting events. For this +to work the trigger period needs to be reduced. + +This puts a field into at91_tsadcc_data to allow platforms to specify +the number of conversions to average over. + +XXX: should the trigger period passed by the platform, too, as this +depends on the number of conversions? +XXX: seperate fast wake up into a seperate patch? What does it? +XXX: don't use bare constants + +Signed-off-by: Ludovic Desroches +--- + drivers/input/touchscreen/atmel_tsadcc.c | 14 ++++++++------ + drivers/input/touchscreen/atmel_tsadcc.h | 1 + + 2 files changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c +index b6a1630..48faecb 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.c ++++ b/drivers/input/touchscreen/atmel_tsadcc.c +@@ -96,7 +96,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + atmel_tsadcc_write(ATMEL_TSADCC_IER, + ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT); + atmel_tsadcc_write(ATMEL_TSADCC_TRGR, +- ATMEL_TSADCC_TRGMOD_PERIOD | (0x0FFF << 16)); ++ ATMEL_TSADCC_TRGMOD_PERIOD | (0x00D0 << 16)); + + } else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) { + /* Conversion finished */ +@@ -259,6 +259,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + + if (cpu_has_9x5_adc()) { + reg = ((0x01 << 5) & ATMEL_TSADCC_SLEEP) | /* Sleep Mode */ ++ ((0x01 << 6) & ATMEL_TSADCC_FWUP) | /* Fast Wake Up */ + (prsc << 8) | + ((0x8 << 16) & ATMEL_TSADCC_STARTUP) | + ((pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TRACKTIM); +@@ -277,11 +278,12 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + + if (cpu_has_9x5_adc()) { + atmel_tsadcc_write(ATMEL_TSADCC_TSMR, +- ATMEL_TSADCC_TSMODE_4WIRE_PRESS | +- ATMEL_TSADCC_NOTSDMA | +- ATMEL_TSADCC_PENDET_ENA | +- (pdata->pendet_debounce << 28) | +- (0x0 << 8)); ++ ATMEL_TSADCC_TSMODE_4WIRE_PRESS | ++ (pdata->filtering_average << 4) | /* Touchscreen average */ ++ ATMEL_TSADCC_NOTSDMA | ++ ATMEL_TSADCC_PENDET_ENA | ++ (pdata->pendet_debounce << 28) | ++ (0x3 << 8)); /* Touchscreen freq */ + } else { + atmel_tsadcc_write(ATMEL_TSADCC_TSR, + (pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM); +diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h +index 231497e..572770a 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.h ++++ b/drivers/input/touchscreen/atmel_tsadcc.h +@@ -34,6 +34,7 @@ + #define ATMEL_TSADCC_LOWRES (1 << 4) /* Resolution selection */ + #define ATMEL_TSADCC_SLEEP (1 << 5) /* Sleep mode */ + #define ATMEL_TSADCC_PENDET (1 << 6) /* Pen Detect selection */ ++#define ATMEL_TSADCC_FWUP (1 << 6) /* Fast Wake Up selection (5series) */ + #define ATMEL_TSADCC_PRES (1 << 7) /* Pressure Measurement Selection */ + #define ATMEL_TSADCC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ + #define ATMEL_TSADCC_EPRESCAL (0xff << 8) /* Prescalar Rate Selection (Extended) */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0084-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch b/patches.at91/0084-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch new file mode 100644 index 000000000000..82ce0dbcb7ee --- /dev/null +++ b/patches.at91/0084-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch @@ -0,0 +1,92 @@ +From bb2bbaa1312891063aed730f0fd3eeddf77f95cb Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Fri, 6 May 2011 17:54:45 +0200 +Subject: input: atmel_tsadcc: add ACR register and change trigger period value + +Add ACR register which allows to configure internal ADC resistor, that should +prevent from adding resistor on display module. Furthermore increase +trigger period which seems to be related with resistor value. A Too small +value causes continuous irq. + +Signed-off-by: Ludovic Desroches +--- + drivers/input/touchscreen/atmel_tsadcc.c | 30 +++++++++++++++++++++++++++++- + drivers/input/touchscreen/atmel_tsadcc.h | 3 +++ + 2 files changed, 32 insertions(+), 1 deletion(-) + +diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c +index 48faecb..20154ba 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.c ++++ b/drivers/input/touchscreen/atmel_tsadcc.c +@@ -47,6 +47,17 @@ static void __iomem *tsc_base; + #define atmel_tsadcc_read(reg) __raw_readl(tsc_base + (reg)) + #define atmel_tsadcc_write(reg, val) __raw_writel((val), tsc_base + (reg)) + ++static void atmel_tsadcc_dump_conf(struct platform_device *pdev) ++{ ++ dev_info(&pdev->dev, "--- configuration ---\n"); ++ dev_info(&pdev->dev, "Mode Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_MR)); ++ dev_info(&pdev->dev, "Trigger Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_TRGR)); ++ dev_info(&pdev->dev, "Touchscreen Mode Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_TSMR)); ++ dev_info(&pdev->dev, "Analog Control Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_ACR)); ++ dev_info(&pdev->dev, "ADC Channel Status Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_CHSR)); ++ dev_info(&pdev->dev, "---------------------\n"); ++} ++ + static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + { + struct atmel_tsadcc *ts_dev = (struct atmel_tsadcc *)dev; +@@ -95,8 +106,14 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + atmel_tsadcc_write(ATMEL_TSADCC_IDR, ATMEL_TSADCC_PENCNT); + atmel_tsadcc_write(ATMEL_TSADCC_IER, + ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT); ++ /* this value is related to the resistor bits value of ++ * ACR register and R64. If internal resistor value is ++ * increased then this value has to be increased. This ++ * behavior seems to happen only with averaging on 8 ++ * values ++ */ + atmel_tsadcc_write(ATMEL_TSADCC_TRGR, +- ATMEL_TSADCC_TRGMOD_PERIOD | (0x00D0 << 16)); ++ ATMEL_TSADCC_TRGMOD_PERIOD | (0x0FF << 16)); + + } else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) { + /* Conversion finished */ +@@ -289,9 +306,20 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + (pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM); + } + ++ /* Change adc internal resistor value for better pen detection, ++ * default value is 100 kOhm. ++ * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm ++ * option only available on ES2 and higher ++ */ ++ if (cpu_has_9x5_adc()) { ++ atmel_tsadcc_write(ATMEL_TSADCC_ACR, pdata->pendet_sensitivity); ++ } ++ + atmel_tsadcc_read(ATMEL_TSADCC_SR); + atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT); + ++ /* atmel_tsadcc_dump_conf(pdev); */ ++ + /* All went ok, so register to the input system */ + err = input_register_device(input_dev); + if (err) +diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h +index 572770a..fe74506 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.h ++++ b/drivers/input/touchscreen/atmel_tsadcc.h +@@ -103,6 +103,9 @@ + #define ATMEL_TSADCC_NOPEN (1 << 30) /* No Pen Contact */ + #define ATMEL_TSADCC_PENDET_STATUS (1 << 31) /* Pen Detect Status (not interrupt source) */ + ++#define ATMEL_TSADCC_ACR 0x94 /* Analog Control Register */ ++#define ATMEL_TSADCC_PENDET_SENSITIVITY (0x3 << 0) /* ADC internal resistor */ ++ + #define ATMEL_TSADCC_TSMR 0xb0 + #define ATMEL_TSADCC_TSMODE (3 << 0) /* Touch Screen Mode */ + #define ATMEL_TSADCC_TSMODE_NO (0 << 0) /* No Touch Screen */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0085-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch b/patches.at91/0085-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch new file mode 100644 index 000000000000..a42080f6c462 --- /dev/null +++ b/patches.at91/0085-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch @@ -0,0 +1,168 @@ +From dd05003395a5ae175e64b5ae8d78f6867d5d7398 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 16 Jun 2011 19:24:04 +0200 +Subject: AT91/input: atmel_tsadcc: rework irq infrastructure and parameters + +Signed-off-by: Nicolas Ferre +--- + drivers/input/touchscreen/atmel_tsadcc.c | 70 ++++++++++++++++++-------------- + 1 file changed, 40 insertions(+), 30 deletions(-) + +diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c +index 20154ba..397d17a 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.c ++++ b/drivers/input/touchscreen/atmel_tsadcc.c +@@ -30,6 +30,7 @@ + #define cpu_has_9x5_adc() (cpu_is_at91sam9x5()) + + #define ADC_DEFAULT_CLOCK 100000 ++#define ZTHRESHOLD 3200 + + struct atmel_tsadcc { + struct input_dev *input; +@@ -39,7 +40,6 @@ struct atmel_tsadcc { + unsigned int prev_absx; + unsigned int prev_absy; + unsigned int prev_absz; +- unsigned char bufferedmeasure; + }; + + static void __iomem *tsc_base; +@@ -62,6 +62,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + { + struct atmel_tsadcc *ts_dev = (struct atmel_tsadcc *)dev; + struct input_dev *input_dev = ts_dev->input; ++ struct at91_tsadcc_data *pdata = input_dev->dev.parent->platform_data; + + unsigned int status; + unsigned int reg; +@@ -76,7 +77,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + /* Contact lost */ + if (cpu_has_9x5_adc()) { + /* 9X5 using TSMR to set PENDBC time */ +- reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR) | ATMEL_TSADCC_PENDBC; ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR) | ((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC); + atmel_tsadcc_write(ATMEL_TSADCC_TSMR, reg); + } else { + reg = atmel_tsadcc_read(ATMEL_TSADCC_MR) | ATMEL_TSADCC_PENDBC; +@@ -88,7 +89,6 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT); + + input_report_key(input_dev, BTN_TOUCH, 0); +- ts_dev->bufferedmeasure = 0; + input_sync(input_dev); + + } else if (status & ATMEL_TSADCC_PENCNT) { +@@ -118,27 +118,20 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + } else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) { + /* Conversion finished */ + +- if (ts_dev->bufferedmeasure) { +- /* Last measurement is always discarded, since it can +- * be erroneous. +- * Always report previous measurement */ +- dev_dbg(&input_dev->dev, +- "x = %d, y = %d, pressure = %d\n", +- ts_dev->prev_absx, ts_dev->prev_absy, +- ts_dev->prev_absz); +- input_report_abs(input_dev, ABS_X, ts_dev->prev_absx); +- input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy); +- input_report_key(input_dev, BTN_TOUCH, 1); +- if (cpu_has_9x5_adc()) +- input_report_abs(input_dev, ABS_PRESSURE, ts_dev->prev_absz); +- input_sync(input_dev); +- } else +- ts_dev->bufferedmeasure = 1; +- +- /* Now make new measurement */ ++ /* make new measurement */ + if (cpu_has_9x5_adc()) { +- ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR) & 0xffff; +- ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR) & 0xffff; ++ unsigned int xscale, yscale; ++ ++ /* calculate position */ ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR); ++ ts_dev->prev_absx = (reg & ATMEL_TSADCC_XPOS) << 10; ++ xscale = (reg & ATMEL_TSADCC_XSCALE) >> 16; ++ ts_dev->prev_absx /= xscale ? xscale: 1; ++ ++ reg = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR); ++ ts_dev->prev_absy = (reg & ATMEL_TSADCC_YPOS) << 10; ++ yscale = (reg & ATMEL_TSADCC_YSCALE) >> 16; ++ ts_dev->prev_absy /= yscale ? yscale: 1 << 10; + + /* calculate the pressure */ + reg = atmel_tsadcc_read(ATMEL_TSADCC_PRESSR); +@@ -157,6 +150,23 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_CDR1) << 10; + ts_dev->prev_absy /= atmel_tsadcc_read(ATMEL_TSADCC_CDR0); + } ++ ++ /* report measurement to input layer */ ++ if (ts_dev->prev_absz < ZTHRESHOLD) { ++ dev_dbg(&input_dev->dev, ++ "x = %d, y = %d, pressure = %d\n", ++ ts_dev->prev_absx, ts_dev->prev_absy, ++ ts_dev->prev_absz); ++ input_report_abs(input_dev, ABS_X, ts_dev->prev_absx); ++ input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy); ++ if (cpu_has_9x5_adc()) ++ input_report_abs(input_dev, ABS_PRESSURE, ts_dev->prev_absz); ++ input_report_key(input_dev, BTN_TOUCH, 1); ++ input_sync(input_dev); ++ } else { ++ dev_dbg(&input_dev->dev, ++ "pressure too low: not reporting\n"); ++ } + } + + return IRQ_HANDLED; +@@ -233,7 +243,6 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + } + + ts_dev->input = input_dev; +- ts_dev->bufferedmeasure = 0; + + snprintf(ts_dev->phys, sizeof(ts_dev->phys), + "%s/input0", dev_name(&pdev->dev)); +@@ -275,10 +284,10 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + dev_info(&pdev->dev, "Prescaler is set at: %d\n", prsc); + + if (cpu_has_9x5_adc()) { +- reg = ((0x01 << 5) & ATMEL_TSADCC_SLEEP) | /* Sleep Mode */ +- ((0x01 << 6) & ATMEL_TSADCC_FWUP) | /* Fast Wake Up */ ++ reg = ((0x00 << 5) & ATMEL_TSADCC_SLEEP) | /* no Sleep Mode */ ++ ((0x00 << 6) & ATMEL_TSADCC_FWUP) | /* no Fast Wake Up needed */ + (prsc << 8) | +- ((0x8 << 16) & ATMEL_TSADCC_STARTUP) | ++ ((0x4 << 16) & ATMEL_TSADCC_STARTUP) | + ((pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TRACKTIM); + } else { + reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE | +@@ -296,10 +305,10 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + if (cpu_has_9x5_adc()) { + atmel_tsadcc_write(ATMEL_TSADCC_TSMR, + ATMEL_TSADCC_TSMODE_4WIRE_PRESS | +- (pdata->filtering_average << 4) | /* Touchscreen average */ ++ ((pdata->filtering_average << 4) & ATMEL_TSADCC_TSAV) | /* Touchscreen average */ + ATMEL_TSADCC_NOTSDMA | + ATMEL_TSADCC_PENDET_ENA | +- (pdata->pendet_debounce << 28) | ++ ((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC) | + (0x3 << 8)); /* Touchscreen freq */ + } else { + atmel_tsadcc_write(ATMEL_TSADCC_TSR, +@@ -312,7 +321,8 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + * option only available on ES2 and higher + */ + if (cpu_has_9x5_adc()) { +- atmel_tsadcc_write(ATMEL_TSADCC_ACR, pdata->pendet_sensitivity); ++ if (pdata->pendet_sensitivity <= ATMEL_TSADCC_PENDET_SENSITIVITY) ++ atmel_tsadcc_write(ATMEL_TSADCC_ACR, pdata->pendet_sensitivity); + } + + atmel_tsadcc_read(ATMEL_TSADCC_SR); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0086-input-at91-add-tsadcc_data-for-9x5.patch b/patches.at91/0086-input-at91-add-tsadcc_data-for-9x5.patch new file mode 100644 index 000000000000..3b361bce87d4 --- /dev/null +++ b/patches.at91/0086-input-at91-add-tsadcc_data-for-9x5.patch @@ -0,0 +1,27 @@ +From 6fa3817bddf46d9e1fc43a6a217826ec84ededa4 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Thu, 7 Jun 2012 14:19:11 +0800 +Subject: input: at91: add tsadcc_data for 9x5 + +Signed-off-by: Josh Wu +--- + arch/arm/mach-at91/include/mach/board.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h +index 369afc2..726e5f3 100644 +--- a/arch/arm/mach-at91/include/mach/board.h ++++ b/arch/arm/mach-at91/include/mach/board.h +@@ -175,7 +175,9 @@ extern void __init at91_add_device_isi(struct isi_platform_data *data, + /* Touchscreen Controller */ + struct at91_tsadcc_data { + unsigned int adc_clock; ++ u8 filtering_average; + u8 pendet_debounce; ++ u8 pendet_sensitivity; + u8 ts_sample_hold_time; + }; + extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0087-input-at91-add-dt-support-for-atmel-touch-screen-adc.patch b/patches.at91/0087-input-at91-add-dt-support-for-atmel-touch-screen-adc.patch new file mode 100644 index 000000000000..1a432fc80602 --- /dev/null +++ b/patches.at91/0087-input-at91-add-dt-support-for-atmel-touch-screen-adc.patch @@ -0,0 +1,157 @@ +From 9dec1a67c24abf90346706d2fb3172c14d0fbcdf Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Wed, 13 Jun 2012 17:28:40 +0800 +Subject: input: at91: add dt support for atmel touch screen adc controller. + +Signed-off-by: Josh Wu +--- + drivers/input/touchscreen/atmel_tsadcc.c | 86 ++++++++++++++++++++++++++++++-- + 1 file changed, 82 insertions(+), 4 deletions(-) + +diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c +index 397d17a..021f87e 100644 +--- a/drivers/input/touchscreen/atmel_tsadcc.c ++++ b/drivers/input/touchscreen/atmel_tsadcc.c +@@ -40,6 +40,8 @@ struct atmel_tsadcc { + unsigned int prev_absx; + unsigned int prev_absy; + unsigned int prev_absz; ++ ++ struct at91_tsadcc_data board; + }; + + static void __iomem *tsc_base; +@@ -62,7 +64,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + { + struct atmel_tsadcc *ts_dev = (struct atmel_tsadcc *)dev; + struct input_dev *input_dev = ts_dev->input; +- struct at91_tsadcc_data *pdata = input_dev->dev.parent->platform_data; ++ struct at91_tsadcc_data *pdata = &ts_dev->board; + + unsigned int status; + unsigned int reg; +@@ -172,6 +174,63 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev) + return IRQ_HANDLED; + } + ++#if defined(CONFIG_OF) ++static int __devinit atmel_of_init_tsadcc(struct device_node *np, ++ struct at91_tsadcc_data *pdata, ++ struct platform_device *pdev) ++{ ++ u32 val; ++ ++ if (of_property_read_u32(np, "atmel,tsadcc_clock", &val) == 0) ++ pdata->adc_clock = val; ++ ++ if (of_property_read_u32(np, "atmel,filtering_average", &val) == 0) { ++ if (val > 0x03) { ++ dev_err(&pdev->dev, "invalid touch average setting, 0x%02x\n", ++ val); ++ return -EINVAL; ++ } ++ pdata->filtering_average = (u8)val; ++ } ++ ++ if (of_property_read_u32(np, "atmel,pendet_debounce", &val) == 0) { ++ if (val > 0x0f) { ++ dev_err(&pdev->dev, "invalid pen detect debounce, 0x%02x\n", ++ val); ++ return -EINVAL; ++ } ++ pdata->pendet_debounce = (u8)val; ++ } ++ ++ if (of_property_read_u32(np, "atmel,pendet_sensitivity", &val) == 0) { ++ if (val > 0x03) { ++ dev_err(&pdev->dev, "invalid pen detective sensitivity setting, 0x%02x\n", ++ val); ++ return -EINVAL; ++ } ++ pdata->pendet_sensitivity = (u8)val; ++ } ++ ++ if (of_property_read_u32(np, "atmel,ts_sample_hold_time", &val) == 0) { ++ if (val > 0x0f) { ++ dev_err(&pdev->dev, "invalid ts sample hold time, 0x%02x\n", ++ val); ++ return -EINVAL; ++ } ++ pdata->ts_sample_hold_time = (u8)val; ++ } ++ ++ return 0; ++} ++#else ++static int __devinit atmel_of_init_tsadcc(struct device_node *np, ++ struct at91_tsadcc_data *pdata, ++ struct platform_device *pdev) ++{ ++ return -EINVAL; ++} ++#endif ++ + /* + * The functions for inserting/removing us as a module. + */ +@@ -181,7 +240,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + struct atmel_tsadcc *ts_dev; + struct input_dev *input_dev; + struct resource *res; +- struct at91_tsadcc_data *pdata = pdev->dev.platform_data; ++ struct at91_tsadcc_data *pdata; + int err = 0; + unsigned int prsc; + unsigned int reg; +@@ -199,6 +258,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + return -ENOMEM; + } + platform_set_drvdata(pdev, ts_dev); ++ pdata = &ts_dev->board; + + input_dev = input_allocate_device(); + if (!input_dev) { +@@ -264,8 +324,16 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev) + prsc = clk_get_rate(ts_dev->clk); + dev_info(&pdev->dev, "Master clock is set at: %d Hz\n", prsc); + +- if (!pdata) +- goto err_fail; ++ if (pdev->dev.of_node) { ++ err = atmel_of_init_tsadcc(pdev->dev.of_node, pdata, pdev); ++ if (err) ++ goto err_fail; ++ } else { ++ if (!pdev->dev.platform_data) ++ goto err_fail; ++ else ++ memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); ++ } + + if (!pdata->adc_clock) + pdata->adc_clock = ADC_DEFAULT_CLOCK; +@@ -374,11 +442,21 @@ static int __devexit atmel_tsadcc_remove(struct platform_device *pdev) + return 0; + } + ++#if defined(CONFIG_OF) ++static const struct of_device_id atmel_tsaddcc_dt_ids[] = { ++ { .compatible = "atmel,at91sam9x5-tsadcc"}, ++ { /* sentinel */ } ++} ++ ++MODULE_DEVICE_TABLE(of, atmel_tsaddcc_dt_ids); ++#endif ++ + static struct platform_driver atmel_tsadcc_driver = { + .probe = atmel_tsadcc_probe, + .remove = __devexit_p(atmel_tsadcc_remove), + .driver = { + .name = "atmel_tsadcc", ++ .of_match_table = of_match_ptr(atmel_tsaddcc_dt_ids), + }, + }; + module_platform_driver(atmel_tsadcc_driver); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0088-net-macb-Add-support-for-Gigabit-Ethernet-mode.patch b/patches.at91/0088-net-macb-Add-support-for-Gigabit-Ethernet-mode.patch new file mode 100644 index 000000000000..df89e312b3d3 --- /dev/null +++ b/patches.at91/0088-net-macb-Add-support-for-Gigabit-Ethernet-mode.patch @@ -0,0 +1,85 @@ +From 5c2ed1407b5a897a7bd9c9ba0bb6dbc550c71d64 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 6 Sep 2012 14:55:37 +0200 +Subject: net/macb: Add support for Gigabit Ethernet mode + +Add Gigabit Ethernet mode to GEM cadence IP and enable RGMII connection. + +Signed-off-by: Patrice Vilchez +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 15 ++++++++++++--- + drivers/net/ethernet/cadence/macb.h | 4 ++++ + 2 files changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index 6100b85..e9b909a 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -152,13 +152,17 @@ static void macb_handle_link_change(struct net_device *dev) + + reg = macb_readl(bp, NCFGR); + reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); ++ if (macb_is_gem(bp)) ++ reg &= ~GEM_BIT(GBE); + + if (phydev->duplex) + reg |= MACB_BIT(FD); + if (phydev->speed == SPEED_100) + reg |= MACB_BIT(SPD); ++ if (phydev->speed == SPEED_1000) ++ reg |= GEM_BIT(GBE); + +- macb_writel(bp, NCFGR, reg); ++ macb_or_gem_writel(bp, NCFGR, reg); + + bp->speed = phydev->speed; + bp->duplex = phydev->duplex; +@@ -216,7 +220,10 @@ static int macb_mii_probe(struct net_device *dev) + } + + /* mask with MAC supported features */ +- phydev->supported &= PHY_BASIC_FEATURES; ++ if (macb_is_gem(bp)) ++ phydev->supported &= PHY_GBIT_FEATURES; ++ else ++ phydev->supported &= PHY_BASIC_FEATURES; + + phydev->advertising = phydev->supported; + +@@ -1383,7 +1390,9 @@ static int __init macb_probe(struct platform_device *pdev) + bp->phy_interface = err; + } + +- if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) ++ if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) ++ macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII)); ++ else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) + #if defined(CONFIG_ARCH_AT91) + macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | + MACB_BIT(CLKEN))); +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index 335e288..f69ceef 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -145,6 +145,8 @@ + #define MACB_IRXFCS_SIZE 1 + + /* GEM specific NCFGR bitfields. */ ++#define GEM_GBE_OFFSET 10 ++#define GEM_GBE_SIZE 1 + #define GEM_CLK_OFFSET 18 + #define GEM_CLK_SIZE 3 + #define GEM_DBW_OFFSET 21 +@@ -246,6 +248,8 @@ + /* Bitfields in USRIO (AT91) */ + #define MACB_RMII_OFFSET 0 + #define MACB_RMII_SIZE 1 ++#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ ++#define GEM_RGMII_SIZE 1 + #define MACB_CLKEN_OFFSET 1 + #define MACB_CLKEN_SIZE 1 + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0089-net-macb-memory-barriers-cleanup.patch b/patches.at91/0089-net-macb-memory-barriers-cleanup.patch new file mode 100644 index 000000000000..7950edb7c417 --- /dev/null +++ b/patches.at91/0089-net-macb-memory-barriers-cleanup.patch @@ -0,0 +1,96 @@ +From fe758f5a6775fb6b71fdf086c07e5247cafd53f3 Mon Sep 17 00:00:00 2001 +From: Havard Skinnemoen +Date: Fri, 28 May 2010 17:13:33 +0200 +Subject: net/macb: memory barriers cleanup + +Remove a couple of unneeded barriers and document the remaining ones. + +Signed-off-by: Havard Skinnemoen +[nicolas.ferre@atmel.com: split patch in topics] +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++++---- + 1 file changed, 14 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index e9b909a..a4dcd11 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -372,7 +372,9 @@ static void macb_tx(struct macb *bp) + + BUG_ON(skb == NULL); + ++ /* Make hw descriptor updates visible to CPU */ + rmb(); ++ + bufstat = bp->tx_ring[tail].ctrl; + + if (!(bufstat & MACB_BIT(TX_USED))) +@@ -415,7 +417,10 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + if (frag == last_frag) + break; + } ++ ++ /* Make descriptor updates visible to hardware */ + wmb(); ++ + return 1; + } + +@@ -436,12 +441,14 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + frag_len); + offset += RX_BUFFER_SIZE; + bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); +- wmb(); + + if (frag == last_frag) + break; + } + ++ /* Make descriptor updates visible to hardware */ ++ wmb(); ++ + skb->protocol = eth_type_trans(skb, bp->dev); + + bp->stats.rx_packets++; +@@ -461,6 +468,8 @@ static void discard_partial_frame(struct macb *bp, unsigned int begin, + + for (frag = begin; frag != end; frag = NEXT_RX(frag)) + bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); ++ ++ /* Make descriptor updates visible to hardware */ + wmb(); + + /* +@@ -479,7 +488,9 @@ static int macb_rx(struct macb *bp, int budget) + for (; budget > 0; tail = NEXT_RX(tail)) { + u32 addr, ctrl; + ++ /* Make hw descriptor updates visible to CPU */ + rmb(); ++ + addr = bp->rx_ring[tail].addr; + ctrl = bp->rx_ring[tail].ctrl; + +@@ -674,6 +685,8 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + + bp->tx_ring[entry].addr = mapping; + bp->tx_ring[entry].ctrl = ctrl; ++ ++ /* Make newly initialized descriptor visible to hardware */ + wmb(); + + entry = NEXT_TX(entry); +@@ -782,9 +795,6 @@ static void macb_init_rings(struct macb *bp) + + static void macb_reset_hw(struct macb *bp) + { +- /* Make sure we have the write buffer for ourselves */ +- wmb(); +- + /* + * Disable RX and TX (XXX: Should we halt the transmission + * more gracefully?) +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0090-net-macb-change-debugging-messages.patch b/patches.at91/0090-net-macb-change-debugging-messages.patch new file mode 100644 index 000000000000..014d00ddc601 --- /dev/null +++ b/patches.at91/0090-net-macb-change-debugging-messages.patch @@ -0,0 +1,112 @@ +From 7dd52f7f7728c264880ed982dcc5cebeb2ee76c0 Mon Sep 17 00:00:00 2001 +From: Havard Skinnemoen +Date: Fri, 28 May 2010 17:45:43 +0200 +Subject: net/macb: change debugging messages + +Convert some noisy netdev_dbg() statements to netdev_vdbg(). Defining +DEBUG will no longer fill up the logs; VERBOSE_DEBUG still does. +Add one more verbose debug for ISR status. + +Signed-off-by: Havard Skinnemoen +[nicolas.ferre@atmel.com: split patch in topics, add ISR status] +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index a4dcd11..ce1f558 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -313,7 +313,7 @@ static void macb_tx(struct macb *bp) + status = macb_readl(bp, TSR); + macb_writel(bp, TSR, status); + +- netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status); ++ netdev_vdbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status); + + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { + int i; +@@ -380,7 +380,7 @@ static void macb_tx(struct macb *bp) + if (!(bufstat & MACB_BIT(TX_USED))) + break; + +- netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n", ++ netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", + tail, skb->data); + dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, + DMA_TO_DEVICE); +@@ -406,7 +406,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + + len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); + +- netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", ++ netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", + first_frag, last_frag, len); + + skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET); +@@ -453,7 +453,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + + bp->stats.rx_packets++; + bp->stats.rx_bytes += len; +- netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n", ++ netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", + skb->len, skb->csum); + netif_receive_skb(skb); + +@@ -535,7 +535,7 @@ static int macb_poll(struct napi_struct *napi, int budget) + + work_done = 0; + +- netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n", ++ netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", + (unsigned long)status, budget); + + work_done = macb_rx(bp, budget); +@@ -574,6 +574,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) + break; + } + ++ netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status); ++ + if (status & MACB_RX_INT_FLAGS) { + /* + * There's no point taking any more interrupts +@@ -585,7 +587,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) + macb_writel(bp, IDR, MACB_RX_INT_FLAGS); + + if (napi_schedule_prep(&bp->napi)) { +- netdev_dbg(bp->dev, "scheduling RX softirq\n"); ++ netdev_vdbg(bp->dev, "scheduling RX softirq\n"); + __napi_schedule(&bp->napi); + } + } +@@ -647,8 +649,8 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + u32 ctrl; + unsigned long flags; + +-#ifdef DEBUG +- netdev_dbg(bp->dev, ++#if defined(DEBUG) && defined(VERBOSE_DEBUG) ++ netdev_vdbg(bp->dev, + "start_xmit: len %u head %p data %p tail %p end %p\n", + skb->len, skb->head, skb->data, + skb_tail_pointer(skb), skb_end_pointer(skb)); +@@ -670,12 +672,12 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + } + + entry = bp->tx_head; +- netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry); ++ netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry); + mapping = dma_map_single(&bp->pdev->dev, skb->data, + len, DMA_TO_DEVICE); + bp->tx_skb[entry].skb = skb; + bp->tx_skb[entry].mapping = mapping; +- netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", ++ netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", + skb->data, (unsigned long)mapping); + + ctrl = MACB_BF(TX_FRMLEN, len); +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0091-net-macb-remove-macb_get_drvinfo.patch b/patches.at91/0091-net-macb-remove-macb_get_drvinfo.patch new file mode 100644 index 000000000000..c9e7cdb252c1 --- /dev/null +++ b/patches.at91/0091-net-macb-remove-macb_get_drvinfo.patch @@ -0,0 +1,41 @@ +From 93c3f8300d6da2e5a670ac681548509d4aa3b020 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 6 Sep 2012 15:23:47 +0200 +Subject: net/macb: remove macb_get_drvinfo() + +This function has little meaning so remove it altogether and +let ethtool core fill in the fields automatically. + +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 11 ----------- + 1 file changed, 11 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index ce1f558..dc34ff1 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -1223,20 +1223,9 @@ static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) + return phy_ethtool_sset(phydev, cmd); + } + +-static void macb_get_drvinfo(struct net_device *dev, +- struct ethtool_drvinfo *info) +-{ +- struct macb *bp = netdev_priv(dev); +- +- strcpy(info->driver, bp->pdev->dev.driver->name); +- strcpy(info->version, "$Revision: 1.14 $"); +- strcpy(info->bus_info, dev_name(&bp->pdev->dev)); +-} +- + static const struct ethtool_ops macb_ethtool_ops = { + .get_settings = macb_get_settings, + .set_settings = macb_set_settings, +- .get_drvinfo = macb_get_drvinfo, + .get_link = ethtool_op_get_link, + }; + +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0092-net-macb-tx-status-is-more-than-8-bits-now.patch b/patches.at91/0092-net-macb-tx-status-is-more-than-8-bits-now.patch new file mode 100644 index 000000000000..9c0d4ce58f49 --- /dev/null +++ b/patches.at91/0092-net-macb-tx-status-is-more-than-8-bits-now.patch @@ -0,0 +1,28 @@ +From 69eb5ddf7b65fe255a87b7613360c17fc8db2bbc Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 3 Sep 2012 17:52:09 +0200 +Subject: net/macb: tx status is more than 8 bits now + +On some revision of GEM, TSR status register has more information. + +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index dc34ff1..4e05a29 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -313,7 +313,7 @@ static void macb_tx(struct macb *bp) + status = macb_readl(bp, TSR); + macb_writel(bp, TSR, status); + +- netdev_vdbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status); ++ netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status); + + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { + int i; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0093-net-macb-clean-up-ring-buffer-logic.patch b/patches.at91/0093-net-macb-clean-up-ring-buffer-logic.patch new file mode 100644 index 000000000000..4e781ee0d844 --- /dev/null +++ b/patches.at91/0093-net-macb-clean-up-ring-buffer-logic.patch @@ -0,0 +1,409 @@ +From 5c7c8fe88a651f0e3313e644a952d40f83ce8dee Mon Sep 17 00:00:00 2001 +From: Havard Skinnemoen +Date: Mon, 21 Jun 2010 18:56:29 +0200 +Subject: net/macb: clean up ring buffer logic + +Instead of masking head and tail every time we increment them, just let them +wrap through UINT_MAX and mask them when subscripting. Add simple accessor +functions to do the subscripting properly to minimize the chances of messing +this up. + +This makes the code slightly smaller, and hopefully faster as well. Also, +doing the ring buffer management this way will simplify things a lot when +making the ring sizes configurable in the future. + +Signed-off-by: Havard Skinnemoen +[nicolas.ferre@atmel.com: split patch in topics, adapt to newer kernel] +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 168 +++++++++++++++++++++++------------- + drivers/net/ethernet/cadence/macb.h | 22 +++-- + 2 files changed, 122 insertions(+), 68 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index 4e05a29..2554354 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -31,24 +31,13 @@ + + #define RX_BUFFER_SIZE 128 + #define RX_RING_SIZE 512 +-#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE) ++#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) + + /* Make the IP header word-aligned (the ethernet header is 14 bytes) */ + #define RX_OFFSET 2 + + #define TX_RING_SIZE 128 +-#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1) +-#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE) +- +-#define TX_RING_GAP(bp) \ +- (TX_RING_SIZE - (bp)->tx_pending) +-#define TX_BUFFS_AVAIL(bp) \ +- (((bp)->tx_tail <= (bp)->tx_head) ? \ +- (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \ +- (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp)) +-#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1)) +- +-#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1)) ++#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) + + /* minimum number of free TX descriptors before waking up TX process */ + #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) +@@ -56,6 +45,51 @@ + #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) + ++/* Ring buffer accessors */ ++static unsigned int macb_tx_ring_wrap(unsigned int index) ++{ ++ return index & (TX_RING_SIZE - 1); ++} ++ ++static unsigned int macb_tx_ring_avail(struct macb *bp) ++{ ++ return TX_RING_SIZE - (bp->tx_head - bp->tx_tail); ++} ++ ++static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index) ++{ ++ return &bp->tx_ring[macb_tx_ring_wrap(index)]; ++} ++ ++static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index) ++{ ++ return &bp->tx_skb[macb_tx_ring_wrap(index)]; ++} ++ ++static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index) ++{ ++ dma_addr_t offset; ++ ++ offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); ++ ++ return bp->tx_ring_dma + offset; ++} ++ ++static unsigned int macb_rx_ring_wrap(unsigned int index) ++{ ++ return index & (RX_RING_SIZE - 1); ++} ++ ++static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) ++{ ++ return &bp->rx_ring[macb_rx_ring_wrap(index)]; ++} ++ ++static void *macb_rx_buffer(struct macb *bp, unsigned int index) ++{ ++ return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index); ++} ++ + static void __macb_set_hwaddr(struct macb *bp) + { + u32 bottom; +@@ -335,17 +369,18 @@ static void macb_tx(struct macb *bp) + bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); + + /* free transmit buffer in upper layer*/ +- for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { +- struct ring_info *rp = &bp->tx_skb[tail]; +- struct sk_buff *skb = rp->skb; +- +- BUG_ON(skb == NULL); ++ for (tail = bp->tx_tail; tail != head; tail++) { ++ struct macb_tx_skb *tx_skb; ++ struct sk_buff *skb; + + rmb(); + +- dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, +- DMA_TO_DEVICE); +- rp->skb = NULL; ++ tx_skb = macb_tx_skb(bp, tail); ++ skb = tx_skb->skb; ++ ++ dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, ++ skb->len, DMA_TO_DEVICE); ++ tx_skb->skb = NULL; + dev_kfree_skb_irq(skb); + } + +@@ -365,34 +400,38 @@ static void macb_tx(struct macb *bp) + return; + + head = bp->tx_head; +- for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { +- struct ring_info *rp = &bp->tx_skb[tail]; +- struct sk_buff *skb = rp->skb; +- u32 bufstat; ++ for (tail = bp->tx_tail; tail != head; tail++) { ++ struct macb_tx_skb *tx_skb; ++ struct sk_buff *skb; ++ struct macb_dma_desc *desc; ++ u32 ctrl; + +- BUG_ON(skb == NULL); ++ desc = macb_tx_desc(bp, tail); + + /* Make hw descriptor updates visible to CPU */ + rmb(); + +- bufstat = bp->tx_ring[tail].ctrl; ++ ctrl = desc->ctrl; + +- if (!(bufstat & MACB_BIT(TX_USED))) ++ if (!(ctrl & MACB_BIT(TX_USED))) + break; + ++ tx_skb = macb_tx_skb(bp, tail); ++ skb = tx_skb->skb; ++ + netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", +- tail, skb->data); +- dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, ++ macb_tx_ring_wrap(tail), skb->data); ++ dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, + DMA_TO_DEVICE); + bp->stats.tx_packets++; + bp->stats.tx_bytes += skb->len; +- rp->skb = NULL; ++ tx_skb->skb = NULL; + dev_kfree_skb_irq(skb); + } + + bp->tx_tail = tail; +- if (netif_queue_stopped(bp->dev) && +- TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH) ++ if (netif_queue_stopped(bp->dev) ++ && macb_tx_ring_avail(bp) > MACB_TX_WAKEUP_THRESH) + netif_wake_queue(bp->dev); + } + +@@ -403,17 +442,21 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + unsigned int frag; + unsigned int offset = 0; + struct sk_buff *skb; ++ struct macb_dma_desc *desc; + +- len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); ++ desc = macb_rx_desc(bp, last_frag); ++ len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); + + netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", +- first_frag, last_frag, len); ++ macb_rx_ring_wrap(first_frag), ++ macb_rx_ring_wrap(last_frag), len); + + skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET); + if (!skb) { + bp->stats.rx_dropped++; +- for (frag = first_frag; ; frag = NEXT_RX(frag)) { +- bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); ++ for (frag = first_frag; ; frag++) { ++ desc = macb_rx_desc(bp, frag); ++ desc->addr &= ~MACB_BIT(RX_USED); + if (frag == last_frag) + break; + } +@@ -428,7 +471,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + skb_checksum_none_assert(skb); + skb_put(skb, len); + +- for (frag = first_frag; ; frag = NEXT_RX(frag)) { ++ for (frag = first_frag; ; frag++) { + unsigned int frag_len = RX_BUFFER_SIZE; + + if (offset + frag_len > len) { +@@ -436,11 +479,10 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + frag_len = len - offset; + } + skb_copy_to_linear_data_offset(skb, offset, +- (bp->rx_buffers + +- (RX_BUFFER_SIZE * frag)), +- frag_len); ++ macb_rx_buffer(bp, frag), frag_len); + offset += RX_BUFFER_SIZE; +- bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); ++ desc = macb_rx_desc(bp, frag); ++ desc->addr &= ~MACB_BIT(RX_USED); + + if (frag == last_frag) + break; +@@ -466,8 +508,10 @@ static void discard_partial_frame(struct macb *bp, unsigned int begin, + { + unsigned int frag; + +- for (frag = begin; frag != end; frag = NEXT_RX(frag)) +- bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); ++ for (frag = begin; frag != end; frag++) { ++ struct macb_dma_desc *desc = macb_rx_desc(bp, frag); ++ desc->addr &= ~MACB_BIT(RX_USED); ++ } + + /* Make descriptor updates visible to hardware */ + wmb(); +@@ -482,17 +526,18 @@ static void discard_partial_frame(struct macb *bp, unsigned int begin, + static int macb_rx(struct macb *bp, int budget) + { + int received = 0; +- unsigned int tail = bp->rx_tail; ++ unsigned int tail; + int first_frag = -1; + +- for (; budget > 0; tail = NEXT_RX(tail)) { ++ for (tail = bp->rx_tail; budget > 0; tail++) { ++ struct macb_dma_desc *desc = macb_rx_desc(bp, tail); + u32 addr, ctrl; + + /* Make hw descriptor updates visible to CPU */ + rmb(); + +- addr = bp->rx_ring[tail].addr; +- ctrl = bp->rx_ring[tail].ctrl; ++ addr = desc->addr; ++ ctrl = desc->ctrl; + + if (!(addr & MACB_BIT(RX_USED))) + break; +@@ -646,6 +691,8 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + struct macb *bp = netdev_priv(dev); + dma_addr_t mapping; + unsigned int len, entry; ++ struct macb_dma_desc *desc; ++ struct macb_tx_skb *tx_skb; + u32 ctrl; + unsigned long flags; + +@@ -662,7 +709,7 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + spin_lock_irqsave(&bp->lock, flags); + + /* This is a hard error, log it. */ +- if (TX_BUFFS_AVAIL(bp) < 1) { ++ if (macb_tx_ring_avail(bp) < 1) { + netif_stop_queue(dev); + spin_unlock_irqrestore(&bp->lock, flags); + netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n"); +@@ -671,12 +718,15 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + return NETDEV_TX_BUSY; + } + +- entry = bp->tx_head; ++ entry = macb_tx_ring_wrap(bp->tx_head); ++ bp->tx_head++; + netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry); + mapping = dma_map_single(&bp->pdev->dev, skb->data, + len, DMA_TO_DEVICE); +- bp->tx_skb[entry].skb = skb; +- bp->tx_skb[entry].mapping = mapping; ++ ++ tx_skb = &bp->tx_skb[entry]; ++ tx_skb->skb = skb; ++ tx_skb->mapping = mapping; + netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", + skb->data, (unsigned long)mapping); + +@@ -685,20 +735,18 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + if (entry == (TX_RING_SIZE - 1)) + ctrl |= MACB_BIT(TX_WRAP); + +- bp->tx_ring[entry].addr = mapping; +- bp->tx_ring[entry].ctrl = ctrl; ++ desc = &bp->tx_ring[entry]; ++ desc->addr = mapping; ++ desc->ctrl = ctrl; + + /* Make newly initialized descriptor visible to hardware */ + wmb(); + +- entry = NEXT_TX(entry); +- bp->tx_head = entry; +- + skb_tx_timestamp(skb); + + macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); + +- if (TX_BUFFS_AVAIL(bp) < 1) ++ if (macb_tx_ring_avail(bp) < 1) + netif_stop_queue(dev); + + spin_unlock_irqrestore(&bp->lock, flags); +@@ -734,7 +782,7 @@ static int macb_alloc_consistent(struct macb *bp) + { + int size; + +- size = TX_RING_SIZE * sizeof(struct ring_info); ++ size = TX_RING_SIZE * sizeof(struct macb_tx_skb); + bp->tx_skb = kmalloc(size, GFP_KERNEL); + if (!bp->tx_skb) + goto out_err; +@@ -1407,8 +1455,6 @@ static int __init macb_probe(struct platform_device *pdev) + macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); + #endif + +- bp->tx_pending = DEF_TX_RING_PENDING; +- + err = register_netdev(dev); + if (err) { + dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index f69ceef..8a4ee2f 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -356,7 +356,12 @@ + __v; \ + }) + +-struct dma_desc { ++/** ++ * struct macb_dma_desc - Hardware DMA descriptor ++ * @addr: DMA address of data buffer ++ * @ctrl: Control and status bits ++ */ ++struct macb_dma_desc { + u32 addr; + u32 ctrl; + }; +@@ -421,7 +426,12 @@ struct dma_desc { + #define MACB_TX_USED_OFFSET 31 + #define MACB_TX_USED_SIZE 1 + +-struct ring_info { ++/** ++ * struct macb_tx_skb - data about an skb which is being transmitted ++ * @skb: skb currently being transmitted ++ * @mapping: DMA address of the skb's data buffer ++ */ ++struct macb_tx_skb { + struct sk_buff *skb; + dma_addr_t mapping; + }; +@@ -506,12 +516,12 @@ struct macb { + void __iomem *regs; + + unsigned int rx_tail; +- struct dma_desc *rx_ring; ++ struct macb_dma_desc *rx_ring; + void *rx_buffers; + + unsigned int tx_head, tx_tail; +- struct dma_desc *tx_ring; +- struct ring_info *tx_skb; ++ struct macb_dma_desc *tx_ring; ++ struct macb_tx_skb *tx_skb; + + spinlock_t lock; + struct platform_device *pdev; +@@ -529,8 +539,6 @@ struct macb { + dma_addr_t tx_ring_dma; + dma_addr_t rx_buffers_dma; + +- unsigned int rx_pending, tx_pending; +- + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + unsigned int link; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0094-net-macb-ethtool-interface-add-register-dump-feature.patch b/patches.at91/0094-net-macb-ethtool-interface-add-register-dump-feature.patch new file mode 100644 index 000000000000..0b4bc9cbb76a --- /dev/null +++ b/patches.at91/0094-net-macb-ethtool-interface-add-register-dump-feature.patch @@ -0,0 +1,88 @@ +From 07007d3c709662f4cc5e186cb8dd0596e8b0d769 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 3 Sep 2012 17:56:18 +0200 +Subject: net/macb: ethtool interface: add register dump feature + +Add macb_get_regs() ethtool function and its helper function: +macb_get_regs_len(). +The version field is deduced from the IP revision which gives the +"MACB or GEM" information. An additional version field is reserved. + +Signed-off-by: Nicolas Ferre +Reviewed-by: Ben Hutchings +--- + drivers/net/ethernet/cadence/macb.c | 40 +++++++++++++++++++++++++++++++++++++ + drivers/net/ethernet/cadence/macb.h | 3 +++ + 2 files changed, 43 insertions(+) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index 2554354..6486a56 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -1271,9 +1271,49 @@ static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) + return phy_ethtool_sset(phydev, cmd); + } + ++static int macb_get_regs_len(struct net_device *netdev) ++{ ++ return MACB_GREGS_NBR * sizeof(u32); ++} ++ ++static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, ++ void *p) ++{ ++ struct macb *bp = netdev_priv(dev); ++ unsigned int tail, head; ++ u32 *regs_buff = p; ++ ++ regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) ++ | MACB_GREGS_VERSION; ++ ++ tail = macb_tx_ring_wrap(bp->tx_tail); ++ head = macb_tx_ring_wrap(bp->tx_head); ++ ++ regs_buff[0] = macb_readl(bp, NCR); ++ regs_buff[1] = macb_or_gem_readl(bp, NCFGR); ++ regs_buff[2] = macb_readl(bp, NSR); ++ regs_buff[3] = macb_readl(bp, TSR); ++ regs_buff[4] = macb_readl(bp, RBQP); ++ regs_buff[5] = macb_readl(bp, TBQP); ++ regs_buff[6] = macb_readl(bp, RSR); ++ regs_buff[7] = macb_readl(bp, IMR); ++ ++ regs_buff[8] = tail; ++ regs_buff[9] = head; ++ regs_buff[10] = macb_tx_dma(bp, tail); ++ regs_buff[11] = macb_tx_dma(bp, head); ++ ++ if (macb_is_gem(bp)) { ++ regs_buff[12] = gem_readl(bp, USRIO); ++ regs_buff[13] = gem_readl(bp, DMACFG); ++ } ++} ++ + static const struct ethtool_ops macb_ethtool_ops = { + .get_settings = macb_get_settings, + .set_settings = macb_set_settings, ++ .get_regs_len = macb_get_regs_len, ++ .get_regs = macb_get_regs, + .get_link = ethtool_op_get_link, + }; + +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index 8a4ee2f..5be5900 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -10,6 +10,9 @@ + #ifndef _MACB_H + #define _MACB_H + ++#define MACB_GREGS_NBR 16 ++#define MACB_GREGS_VERSION 1 ++ + /* MACB register offsets */ + #define MACB_NCR 0x0000 + #define MACB_NCFGR 0x0004 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0095-net-macb-better-manage-tx-errors.patch b/patches.at91/0095-net-macb-better-manage-tx-errors.patch new file mode 100644 index 000000000000..1be968b607b3 --- /dev/null +++ b/patches.at91/0095-net-macb-better-manage-tx-errors.patch @@ -0,0 +1,257 @@ +From 950c22b78992b706fd8f446efbabb695e2fa2ac1 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 22 Jun 2010 18:38:26 +0200 +Subject: net/macb: better manage tx errors + +Handle all TX errors, not only underruns. TX error management is +deferred to a dedicated workqueue. +Reinitialize the TX ring after treating all remaining frames, and +restart the controller when everything has been cleaned up properly. +Napi is not stopped during this task as the driver only handles +napi for RX for now. +With this sequence, we do not need a special check during the xmit +method as the packets will be caught by TX disable during workqueue +execution. + +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 166 ++++++++++++++++++++++++------------ + drivers/net/ethernet/cadence/macb.h | 1 + + 2 files changed, 113 insertions(+), 54 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index 6486a56..cd24ce6 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -44,6 +44,16 @@ + + #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) ++#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ ++ | MACB_BIT(ISR_RLE) \ ++ | MACB_BIT(TXERR)) ++#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) ++ ++/* ++ * Graceful stop timeouts in us. We should allow up to ++ * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) ++ */ ++#define MACB_HALT_TIMEOUT 1230 + + /* Ring buffer accessors */ + static unsigned int macb_tx_ring_wrap(unsigned int index) +@@ -338,66 +348,113 @@ static void macb_update_stats(struct macb *bp) + *p += __raw_readl(reg); + } + +-static void macb_tx(struct macb *bp) ++static int macb_halt_tx(struct macb *bp) + { +- unsigned int tail; +- unsigned int head; +- u32 status; ++ unsigned long halt_time, timeout; ++ u32 status; + +- status = macb_readl(bp, TSR); +- macb_writel(bp, TSR, status); ++ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); + +- netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status); ++ timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); ++ do { ++ halt_time = jiffies; ++ status = macb_readl(bp, TSR); ++ if (!(status & MACB_BIT(TGO))) ++ return 0; + +- if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { +- int i; +- netdev_err(bp->dev, "TX %s, resetting buffers\n", +- status & MACB_BIT(UND) ? +- "underrun" : "retry limit exceeded"); ++ usleep_range(10, 250); ++ } while (time_before(halt_time, timeout)); + +- /* Transfer ongoing, disable transmitter, to avoid confusion */ +- if (status & MACB_BIT(TGO)) +- macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE)); ++ return -ETIMEDOUT; ++} + +- head = bp->tx_head; ++static void macb_tx_error_task(struct work_struct *work) ++{ ++ struct macb *bp = container_of(work, struct macb, tx_error_task); ++ struct macb_tx_skb *tx_skb; ++ struct sk_buff *skb; ++ unsigned int tail; + +- /*Mark all the buffer as used to avoid sending a lost buffer*/ +- for (i = 0; i < TX_RING_SIZE; i++) +- bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); ++ netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n", ++ bp->tx_tail, bp->tx_head); + +- /* Add wrap bit */ +- bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); ++ /* Make sure nobody is trying to queue up new packets */ ++ netif_stop_queue(bp->dev); + +- /* free transmit buffer in upper layer*/ +- for (tail = bp->tx_tail; tail != head; tail++) { +- struct macb_tx_skb *tx_skb; +- struct sk_buff *skb; ++ /* ++ * Stop transmission now ++ * (in case we have just queued new packets) ++ */ ++ if (macb_halt_tx(bp)) ++ /* Just complain for now, reinitializing TX path can be good */ ++ netdev_err(bp->dev, "BUG: halt tx timed out\n"); + +- rmb(); ++ /* No need for the lock here as nobody will interrupt us anymore */ + +- tx_skb = macb_tx_skb(bp, tail); +- skb = tx_skb->skb; ++ /* ++ * Treat frames in TX queue including the ones that caused the error. ++ * Free transmit buffers in upper layer. ++ */ ++ for (tail = bp->tx_tail; tail != bp->tx_head; tail++) { ++ struct macb_dma_desc *desc; ++ u32 ctrl; + +- dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, +- skb->len, DMA_TO_DEVICE); +- tx_skb->skb = NULL; +- dev_kfree_skb_irq(skb); +- } ++ desc = macb_tx_desc(bp, tail); ++ ctrl = desc->ctrl; ++ tx_skb = macb_tx_skb(bp, tail); ++ skb = tx_skb->skb; + +- bp->tx_head = bp->tx_tail = 0; ++ if (ctrl & MACB_BIT(TX_USED)) { ++ netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", ++ macb_tx_ring_wrap(tail), skb->data); ++ bp->stats.tx_packets++; ++ bp->stats.tx_bytes += skb->len; ++ } else { ++ /* ++ * "Buffers exhausted mid-frame" errors may only happen ++ * if the driver is buggy, so complain loudly about those. ++ * Statistics are updated by hardware. ++ */ ++ if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) ++ netdev_err(bp->dev, ++ "BUG: TX buffers exhausted mid-frame\n"); + +- /* Enable the transmitter again */ +- if (status & MACB_BIT(TGO)) +- macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); ++ desc->ctrl = ctrl | MACB_BIT(TX_USED); ++ } ++ ++ dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, ++ DMA_TO_DEVICE); ++ tx_skb->skb = NULL; ++ dev_kfree_skb(skb); + } + +- if (!(status & MACB_BIT(COMP))) +- /* +- * This may happen when a buffer becomes complete +- * between reading the ISR and scanning the +- * descriptors. Nothing to worry about. +- */ +- return; ++ /* Make descriptor updates visible to hardware */ ++ wmb(); ++ ++ /* Reinitialize the TX desc queue */ ++ macb_writel(bp, TBQP, bp->tx_ring_dma); ++ /* Make TX ring reflect state of hardware */ ++ bp->tx_head = bp->tx_tail = 0; ++ ++ /* Now we are ready to start transmission again */ ++ netif_wake_queue(bp->dev); ++ ++ /* Housework before enabling TX IRQ */ ++ macb_writel(bp, TSR, macb_readl(bp, TSR)); ++ macb_writel(bp, IER, MACB_TX_INT_FLAGS); ++} ++ ++static void macb_tx_interrupt(struct macb *bp) ++{ ++ unsigned int tail; ++ unsigned int head; ++ u32 status; ++ ++ status = macb_readl(bp, TSR); ++ macb_writel(bp, TSR, status); ++ ++ netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", ++ (unsigned long)status); + + head = bp->tx_head; + for (tail = bp->tx_tail; tail != head; tail++) { +@@ -637,9 +694,14 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) + } + } + +- if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | +- MACB_BIT(ISR_RLE))) +- macb_tx(bp); ++ if (unlikely(status & (MACB_TX_ERR_FLAGS))) { ++ macb_writel(bp, IDR, MACB_TX_INT_FLAGS); ++ schedule_work(&bp->tx_error_task); ++ break; ++ } ++ ++ if (status & MACB_BIT(TCOMP)) ++ macb_tx_interrupt(bp); + + /* + * Link change detection isn't possible with RMII, so we'll +@@ -969,13 +1031,8 @@ static void macb_init_hw(struct macb *bp) + macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); + + /* Enable interrupts */ +- macb_writel(bp, IER, (MACB_BIT(RCOMP) +- | MACB_BIT(RXUBR) +- | MACB_BIT(ISR_TUND) +- | MACB_BIT(ISR_RLE) +- | MACB_BIT(TXERR) +- | MACB_BIT(TCOMP) +- | MACB_BIT(ISR_ROVR) ++ macb_writel(bp, IER, (MACB_RX_INT_FLAGS ++ | MACB_TX_INT_FLAGS + | MACB_BIT(HRESP))); + + } +@@ -1423,6 +1480,7 @@ static int __init macb_probe(struct platform_device *pdev) + bp->dev = dev; + + spin_lock_init(&bp->lock); ++ INIT_WORK(&bp->tx_error_task, macb_tx_error_task); + + bp->pclk = clk_get(&pdev->dev, "pclk"); + if (IS_ERR(bp->pclk)) { +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index 5be5900..bfab8ef 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -532,6 +532,7 @@ struct macb { + struct clk *hclk; + struct net_device *dev; + struct napi_struct napi; ++ struct work_struct tx_error_task; + struct net_device_stats stats; + union { + struct macb_stats macb; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0096-net-macb-Offset-first-RX-buffer-by-two-bytes.patch b/patches.at91/0096-net-macb-Offset-first-RX-buffer-by-two-bytes.patch new file mode 100644 index 000000000000..8037759a4005 --- /dev/null +++ b/patches.at91/0096-net-macb-Offset-first-RX-buffer-by-two-bytes.patch @@ -0,0 +1,94 @@ +From ebff9d35a64e87d3a6c6d05421b7be4ceedbb589 Mon Sep 17 00:00:00 2001 +From: Havard Skinnemoen +Date: Tue, 24 Mar 2009 10:45:18 +0100 +Subject: net/macb: Offset first RX buffer by two bytes + +Make the ethernet frame payload word-aligned, possibly making the +memcpy into the skb a bit faster. This will be even more important +after we eliminate the copy altogether. + +Also eliminate the redundant RX_OFFSET constant -- it has the same +definition and purpose as NET_IP_ALIGN. + +Signed-off-by: Havard Skinnemoen +[nicolas.ferre@atmel.com: adapt to newer kernel] +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 23 ++++++++++++++++------- + 1 file changed, 16 insertions(+), 7 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index cd24ce6..88a1d20 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -33,9 +33,6 @@ + #define RX_RING_SIZE 512 + #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) + +-/* Make the IP header word-aligned (the ethernet header is 14 bytes) */ +-#define RX_OFFSET 2 +- + #define TX_RING_SIZE 128 + #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) + +@@ -497,7 +494,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + { + unsigned int len; + unsigned int frag; +- unsigned int offset = 0; ++ unsigned int offset; + struct sk_buff *skb; + struct macb_dma_desc *desc; + +@@ -508,7 +505,16 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + macb_rx_ring_wrap(first_frag), + macb_rx_ring_wrap(last_frag), len); + +- skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET); ++ /* ++ * The ethernet header starts NET_IP_ALIGN bytes into the ++ * first buffer. Since the header is 14 bytes, this makes the ++ * payload word-aligned. ++ * ++ * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy ++ * the two padding bytes into the skb so that we avoid hitting ++ * the slowpath in memcpy(), and pull them off afterwards. ++ */ ++ skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); + if (!skb) { + bp->stats.rx_dropped++; + for (frag = first_frag; ; frag++) { +@@ -524,7 +530,8 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + return 1; + } + +- skb_reserve(skb, RX_OFFSET); ++ offset = 0; ++ len += NET_IP_ALIGN; + skb_checksum_none_assert(skb); + skb_put(skb, len); + +@@ -548,10 +555,11 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + /* Make descriptor updates visible to hardware */ + wmb(); + ++ __skb_pull(skb, NET_IP_ALIGN); + skb->protocol = eth_type_trans(skb, bp->dev); + + bp->stats.rx_packets++; +- bp->stats.rx_bytes += len; ++ bp->stats.rx_bytes += skb->len; + netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", + skb->len, skb->csum); + netif_receive_skb(skb); +@@ -1011,6 +1019,7 @@ static void macb_init_hw(struct macb *bp) + __macb_set_hwaddr(bp); + + config = macb_mdc_clk_div(bp); ++ config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ + config |= MACB_BIT(PAE); /* PAuse Enable */ + config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ + config |= MACB_BIT(BIG); /* Receive oversized frames */ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0097-net-macb-GEM-DMA-configuration-register-update.patch b/patches.at91/0097-net-macb-GEM-DMA-configuration-register-update.patch new file mode 100644 index 000000000000..2cfd5c29859c --- /dev/null +++ b/patches.at91/0097-net-macb-GEM-DMA-configuration-register-update.patch @@ -0,0 +1,71 @@ +From 5d30336b8a420e0a8b24572d3fbc7458477e2a2e Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Wed, 19 Sep 2012 15:14:34 +0200 +Subject: net/macb: GEM DMA configuration register update + +Add information to the DMA Configuration Register to +maximize system performance: +- rx/tx packet buffer full memory size +- allow possibility to use INCR16 if supported + +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 10 ++++++++-- + drivers/net/ethernet/cadence/macb.h | 11 +++++++++++ + 2 files changed, 19 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index 88a1d20..56bab3c 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -997,8 +997,12 @@ static u32 macb_dbw(struct macb *bp) + } + + /* +- * Configure the receive DMA engine to use the correct receive buffer size. +- * This is a configurable parameter for GEM. ++ * Configure the receive DMA engine ++ * - use the correct receive buffer size ++ * - set the possibility to use INCR16 bursts ++ * (if not supported by FIFO, it will fallback to default) ++ * - set both rx/tx packet buffers to full memory size ++ * These are configurable parameters for GEM. + */ + static void macb_configure_dma(struct macb *bp) + { +@@ -1007,6 +1011,8 @@ static void macb_configure_dma(struct macb *bp) + if (macb_is_gem(bp)) { + dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); + dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); ++ dmacfg |= GEM_BF(FBLDO, 16); ++ dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); + gem_writel(bp, DMACFG, dmacfg); + } + } +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index bfab8ef..256559d 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -161,8 +161,19 @@ + #define GEM_DBW128 2 + + /* Bitfields in DMACFG. */ ++#define GEM_FBLDO_OFFSET 0 ++#define GEM_FBLDO_SIZE 5 ++#define GEM_RXBMS_OFFSET 8 ++#define GEM_RXBMS_SIZE 2 ++#define GEM_TXPBMS_OFFSET 10 ++#define GEM_TXPBMS_SIZE 1 ++#define GEM_TXCOEN_OFFSET 11 ++#define GEM_TXCOEN_SIZE 1 + #define GEM_RXBS_OFFSET 16 + #define GEM_RXBS_SIZE 8 ++#define GEM_DDRP_OFFSET 24 ++#define GEM_DDRP_SIZE 1 ++ + + /* Bitfields in NSR */ + #define MACB_NSR_LINK_OFFSET 0 +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0098-net-macb-Use-non-coherent-memory-for-rx-buffers.patch b/patches.at91/0098-net-macb-Use-non-coherent-memory-for-rx-buffers.patch new file mode 100644 index 000000000000..19fb2b0a74ab --- /dev/null +++ b/patches.at91/0098-net-macb-Use-non-coherent-memory-for-rx-buffers.patch @@ -0,0 +1,378 @@ +From d753b91290e2caf097dcb0d216710fcce4208327 Mon Sep 17 00:00:00 2001 +From: Havard Skinnemoen +Date: Tue, 24 Mar 2009 10:45:19 +0100 +Subject: net/macb: Use non-coherent memory for rx buffers + +Allocate regular pages to use as backing for the RX ring and use the +DMA API to sync the caches. This should give a bit better performance +since it allows the CPU to do burst transfers from memory. It is also +a necessary step on the way to reduce the amount of copying done by +the driver. + +Signed-off-by: Havard Skinnemoen +[nicolas.ferre@atmel.com: adapt to newer kernel] +Signed-off-by: Nicolas Ferre +--- + drivers/net/ethernet/cadence/macb.c | 206 +++++++++++++++++++++++------------- + drivers/net/ethernet/cadence/macb.h | 20 +++- + 2 files changed, 148 insertions(+), 78 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index 56bab3c..e3168bf 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -10,6 +10,7 @@ + + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include ++#include + #include + #include + #include +@@ -32,6 +33,8 @@ + #define RX_BUFFER_SIZE 128 + #define RX_RING_SIZE 512 + #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) ++#define RX_BUFFERS_PER_PAGE (PAGE_SIZE / RX_BUFFER_SIZE) ++#define RX_RING_PAGES (RX_RING_SIZE / RX_BUFFERS_PER_PAGE) + + #define TX_RING_SIZE 128 + #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) +@@ -92,9 +95,16 @@ static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) + return &bp->rx_ring[macb_rx_ring_wrap(index)]; + } + +-static void *macb_rx_buffer(struct macb *bp, unsigned int index) ++static struct macb_rx_page *macb_rx_page(struct macb *bp, unsigned int index) + { +- return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index); ++ unsigned int entry = macb_rx_ring_wrap(index); ++ ++ return &bp->rx_page[entry / RX_BUFFERS_PER_PAGE]; ++} ++ ++static unsigned int macb_rx_page_offset(struct macb *bp, unsigned int index) ++{ ++ return (index % RX_BUFFERS_PER_PAGE) * RX_BUFFER_SIZE; + } + + static void __macb_set_hwaddr(struct macb *bp) +@@ -492,11 +502,15 @@ static void macb_tx_interrupt(struct macb *bp) + static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + unsigned int last_frag) + { +- unsigned int len; +- unsigned int frag; +- unsigned int offset; +- struct sk_buff *skb; +- struct macb_dma_desc *desc; ++ unsigned int len; ++ unsigned int frag; ++ unsigned int skb_offset; ++ unsigned int pg_offset; ++ struct macb_rx_page *rx_page; ++ dma_addr_t phys; ++ void *buf; ++ struct sk_buff *skb; ++ struct macb_dma_desc *desc; + + desc = macb_rx_desc(bp, last_frag); + len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); +@@ -530,7 +544,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + return 1; + } + +- offset = 0; ++ skb_offset = 0; + len += NET_IP_ALIGN; + skb_checksum_none_assert(skb); + skb_put(skb, len); +@@ -538,13 +552,28 @@ static int macb_rx_frame(struct macb *bp, unsigned int first_frag, + for (frag = first_frag; ; frag++) { + unsigned int frag_len = RX_BUFFER_SIZE; + +- if (offset + frag_len > len) { ++ if (skb_offset + frag_len > len) { + BUG_ON(frag != last_frag); +- frag_len = len - offset; ++ frag_len = len - skb_offset; + } +- skb_copy_to_linear_data_offset(skb, offset, +- macb_rx_buffer(bp, frag), frag_len); +- offset += RX_BUFFER_SIZE; ++ ++ rx_page = macb_rx_page(bp, frag); ++ pg_offset = macb_rx_page_offset(bp, frag); ++ phys = rx_page->phys; ++ ++ dma_sync_single_range_for_cpu(&bp->pdev->dev, phys, ++ pg_offset, frag_len, DMA_FROM_DEVICE); ++ ++ buf = kmap_atomic(rx_page->page); ++ skb_copy_to_linear_data_offset(skb, skb_offset, ++ buf + pg_offset, frag_len); ++ kunmap_atomic(buf); ++ ++ skb_offset += frag_len; ++ ++ dma_sync_single_range_for_device(&bp->pdev->dev, phys, ++ pg_offset, frag_len, DMA_FROM_DEVICE); ++ + desc = macb_rx_desc(bp, frag); + desc->addr &= ~MACB_BIT(RX_USED); + +@@ -824,86 +853,90 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) + return NETDEV_TX_OK; + } + +-static void macb_free_consistent(struct macb *bp) ++static void macb_free_rings(struct macb *bp) + { +- if (bp->tx_skb) { +- kfree(bp->tx_skb); +- bp->tx_skb = NULL; +- } +- if (bp->rx_ring) { +- dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, +- bp->rx_ring, bp->rx_ring_dma); +- bp->rx_ring = NULL; +- } +- if (bp->tx_ring) { +- dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, +- bp->tx_ring, bp->tx_ring_dma); +- bp->tx_ring = NULL; +- } +- if (bp->rx_buffers) { +- dma_free_coherent(&bp->pdev->dev, +- RX_RING_SIZE * RX_BUFFER_SIZE, +- bp->rx_buffers, bp->rx_buffers_dma); +- bp->rx_buffers = NULL; ++ int i; ++ ++ for (i = 0; i < RX_RING_PAGES; i++) { ++ struct macb_rx_page *rx_page = &bp->rx_page[i]; ++ ++ if (!rx_page->page) ++ continue; ++ ++ dma_unmap_page(&bp->pdev->dev, rx_page->phys, ++ PAGE_SIZE, DMA_FROM_DEVICE); ++ put_page(rx_page->page); ++ rx_page->page = NULL; + } ++ ++ kfree(bp->tx_skb); ++ kfree(bp->rx_page); ++ dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, bp->tx_ring, ++ bp->tx_ring_dma); ++ dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, bp->rx_ring, ++ bp->rx_ring_dma); + } + +-static int macb_alloc_consistent(struct macb *bp) ++static int macb_init_rings(struct macb *bp) + { +- int size; ++ struct page *page; ++ dma_addr_t phys; ++ unsigned int page_idx; ++ unsigned int ring_idx; ++ unsigned int i; + +- size = TX_RING_SIZE * sizeof(struct macb_tx_skb); +- bp->tx_skb = kmalloc(size, GFP_KERNEL); +- if (!bp->tx_skb) +- goto out_err; +- +- size = RX_RING_BYTES; +- bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, ++ bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, RX_RING_BYTES, + &bp->rx_ring_dma, GFP_KERNEL); + if (!bp->rx_ring) +- goto out_err; ++ goto err_alloc_rx_ring; ++ + netdev_dbg(bp->dev, + "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", +- size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); ++ RX_RING_BYTES, (unsigned long)bp->rx_ring_dma, bp->rx_ring); + +- size = TX_RING_BYTES; +- bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, ++ bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, TX_RING_BYTES, + &bp->tx_ring_dma, GFP_KERNEL); + if (!bp->tx_ring) +- goto out_err; +- netdev_dbg(bp->dev, +- "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", +- size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); +- +- size = RX_RING_SIZE * RX_BUFFER_SIZE; +- bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, +- &bp->rx_buffers_dma, GFP_KERNEL); +- if (!bp->rx_buffers) +- goto out_err; ++ goto err_alloc_tx_ring; ++ + netdev_dbg(bp->dev, +- "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", +- size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); ++ "Allocated TX ring of %d bytes at 0x%08lx (mapped %p)\n", ++ TX_RING_BYTES, (unsigned long)bp->tx_ring_dma, bp->tx_ring); + +- return 0; ++ bp->rx_page = kcalloc(RX_RING_PAGES, sizeof(struct macb_rx_page), ++ GFP_KERNEL); ++ if (!bp->rx_page) ++ goto err_alloc_rx_page; + +-out_err: +- macb_free_consistent(bp); +- return -ENOMEM; +-} ++ bp->tx_skb = kcalloc(TX_RING_SIZE, sizeof(struct macb_tx_skb), ++ GFP_KERNEL); ++ if (!bp->tx_skb) ++ goto err_alloc_tx_skb; + +-static void macb_init_rings(struct macb *bp) +-{ +- int i; +- dma_addr_t addr; ++ for (page_idx = 0, ring_idx = 0; page_idx < RX_RING_PAGES; page_idx++) { ++ page = alloc_page(GFP_KERNEL); ++ if (!page) ++ goto err_alloc_page; ++ ++ phys = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(&bp->pdev->dev, phys)) ++ goto err_map_page; ++ ++ bp->rx_page[page_idx].page = page; ++ bp->rx_page[page_idx].phys = phys; + +- addr = bp->rx_buffers_dma; +- for (i = 0; i < RX_RING_SIZE; i++) { +- bp->rx_ring[i].addr = addr; +- bp->rx_ring[i].ctrl = 0; +- addr += RX_BUFFER_SIZE; ++ for (i = 0; i < RX_BUFFERS_PER_PAGE; i++, ring_idx++) { ++ bp->rx_ring[ring_idx].addr = phys; ++ bp->rx_ring[ring_idx].ctrl = 0; ++ phys += RX_BUFFER_SIZE; ++ } + } + bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); + ++ netdev_dbg(bp->dev, "Allocated %u RX buffers (%lu pages)\n", ++ RX_RING_SIZE, RX_RING_PAGES); ++ + for (i = 0; i < TX_RING_SIZE; i++) { + bp->tx_ring[i].addr = 0; + bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); +@@ -911,6 +944,28 @@ static void macb_init_rings(struct macb *bp) + bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); + + bp->rx_tail = bp->tx_head = bp->tx_tail = 0; ++ ++ return 0; ++ ++err_map_page: ++ __free_page(page); ++err_alloc_page: ++ while (page_idx--) { ++ dma_unmap_page(&bp->pdev->dev, bp->rx_page[page_idx].phys, ++ PAGE_SIZE, DMA_FROM_DEVICE); ++ __free_page(bp->rx_page[page_idx].page); ++ } ++ kfree(bp->tx_skb); ++err_alloc_tx_skb: ++ kfree(bp->rx_page); ++err_alloc_rx_page: ++ dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, bp->tx_ring, ++ bp->tx_ring_dma); ++err_alloc_tx_ring: ++ dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, bp->rx_ring, ++ bp->rx_ring_dma); ++err_alloc_rx_ring: ++ return -ENOMEM; + } + + static void macb_reset_hw(struct macb *bp) +@@ -1185,16 +1240,15 @@ static int macb_open(struct net_device *dev) + if (!is_valid_ether_addr(dev->dev_addr)) + return -EADDRNOTAVAIL; + +- err = macb_alloc_consistent(bp); ++ err = macb_init_rings(bp); + if (err) { +- netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", ++ netdev_err(dev, "Unable to allocate DMA rings (error %d)\n", + err); + return err; + } + + napi_enable(&bp->napi); + +- macb_init_rings(bp); + macb_init_hw(bp); + + /* schedule a link state check */ +@@ -1221,7 +1275,7 @@ static int macb_close(struct net_device *dev) + netif_carrier_off(dev); + spin_unlock_irqrestore(&bp->lock, flags); + +- macb_free_consistent(bp); ++ macb_free_rings(bp); + + return 0; + } +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index 256559d..01aecea 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -441,6 +441,23 @@ struct macb_dma_desc { + #define MACB_TX_USED_SIZE 1 + + /** ++ * struct macb_rx_page - data associated with a page used as RX buffers ++ * @page: Physical page used as storage for the buffers ++ * @phys: DMA address of the page ++ * ++ * Each page is used to provide %MACB_RX_BUFFERS_PER_PAGE RX buffers. ++ * The page gets an initial reference when it is inserted into the ++ * ring, and an additional reference each time it is passed up the ++ * stack as a fragment. When all the buffers have been used, we drop ++ * the initial reference and allocate a new page. Any additional ++ * references are dropped when the higher layers free the skb. ++ */ ++struct macb_rx_page { ++ struct page *page; ++ dma_addr_t phys; ++}; ++ ++/** + * struct macb_tx_skb - data about an skb which is being transmitted + * @skb: skb currently being transmitted + * @mapping: DMA address of the skb's data buffer +@@ -531,7 +548,7 @@ struct macb { + + unsigned int rx_tail; + struct macb_dma_desc *rx_ring; +- void *rx_buffers; ++ struct macb_rx_page *rx_page; + + unsigned int tx_head, tx_tail; + struct macb_dma_desc *tx_ring; +@@ -552,7 +569,6 @@ struct macb { + + dma_addr_t rx_ring_dma; + dma_addr_t tx_ring_dma; +- dma_addr_t rx_buffers_dma; + + struct mii_bus *mii_bus; + struct phy_device *phy_dev; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0099-phy-micrel-Use-proper-phy-in-gmac.patch b/patches.at91/0099-phy-micrel-Use-proper-phy-in-gmac.patch new file mode 100644 index 000000000000..2c1d4bb38c47 --- /dev/null +++ b/patches.at91/0099-phy-micrel-Use-proper-phy-in-gmac.patch @@ -0,0 +1,49 @@ +From 0a488fbfdd0525849b8a67cc8158523643aaba7e Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 26 Jun 2012 11:07:32 +0200 +Subject: phy/micrel: Use proper phy in gmac + +Signed-off-by: Nicolas Ferre +--- + drivers/net/phy/micrel.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c +index 590f902..cc7f75b 100644 +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -191,6 +191,7 @@ static int __init ksphy_init(void) + { + int ret; + ++#if 0 + ret = phy_driver_register(&ks8001_driver); + if (ret) + goto err1; +@@ -208,9 +209,15 @@ static int __init ksphy_init(void) + ret = phy_driver_register(&ks8051_driver); + if (ret) + goto err5; ++#endif ++ ++ ret = phy_driver_register(&ksz9021_driver); ++ if (ret) ++ goto err1; + + return 0; + ++#if 0 + err5: + phy_driver_unregister(&ks8041_driver); + err4: +@@ -219,6 +226,7 @@ err3: + phy_driver_unregister(&ksz9021_driver); + err2: + phy_driver_unregister(&ks8001_driver); ++#endif + err1: + return ret; + } +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0100-phy-micrel-we-need-to-register-ks8051-phy-for-emac.patch b/patches.at91/0100-phy-micrel-we-need-to-register-ks8051-phy-for-emac.patch new file mode 100644 index 000000000000..32d46d482232 --- /dev/null +++ b/patches.at91/0100-phy-micrel-we-need-to-register-ks8051-phy-for-emac.patch @@ -0,0 +1,39 @@ +From db4349884ad9dd53c6a3e866aefd00a78532907f Mon Sep 17 00:00:00 2001 +From: Ludovic Desroches +Date: Tue, 10 Jul 2012 12:03:54 +0200 +Subject: phy/micrel: we need to register ks8051 phy for emac + +Signed-off-by: Ludovic Desroches +--- + drivers/net/phy/micrel.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c +index cc7f75b..2d80e01 100644 +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -206,10 +206,10 @@ static int __init ksphy_init(void) + ret = phy_driver_register(&ks8041_driver); + if (ret) + goto err4; ++#endif + ret = phy_driver_register(&ks8051_driver); + if (ret) +- goto err5; +-#endif ++ goto err2; + + ret = phy_driver_register(&ksz9021_driver); + if (ret) +@@ -227,6 +227,8 @@ err3: + err2: + phy_driver_unregister(&ks8001_driver); + #endif ++err2: ++ phy_driver_unregister(&ks8051_driver); + err1: + return ret; + } +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0101-usb-gadget-at91_udc-move-the-dereference-below-the-N.patch b/patches.at91/0101-usb-gadget-at91_udc-move-the-dereference-below-the-N.patch new file mode 100644 index 000000000000..b28e71bae404 --- /dev/null +++ b/patches.at91/0101-usb-gadget-at91_udc-move-the-dereference-below-the-N.patch @@ -0,0 +1,40 @@ +From ae50ff05ab833b25bb7d581dd0beaeec1ab830da Mon Sep 17 00:00:00 2001 +From: Wei Yongjun +Date: Fri, 7 Sep 2012 14:54:25 +0800 +Subject: usb: gadget: at91_udc: move the dereference below the NULL test + +The dereference should be moved below the NULL test. + +spatch with a semantic match is used to found this. +(http://coccinelle.lip6.fr/) + +Signed-off-by: Wei Yongjun +Signed-off-by: Felipe Balbi +--- + drivers/usb/gadget/at91_udc.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c +index 9d7bcd9..d6249f0 100644 +--- a/drivers/usb/gadget/at91_udc.c ++++ b/drivers/usb/gadget/at91_udc.c +@@ -469,7 +469,7 @@ static int at91_ep_enable(struct usb_ep *_ep, + const struct usb_endpoint_descriptor *desc) + { + struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); +- struct at91_udc *udc = ep->udc; ++ struct at91_udc *udc; + u16 maxpacket; + u32 tmp; + unsigned long flags; +@@ -484,6 +484,7 @@ static int at91_ep_enable(struct usb_ep *_ep, + return -EINVAL; + } + ++ udc = ep->udc; + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { + DBG("bogus device state\n"); + return -ESHUTDOWN; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0103-USB-ohci-at91-fix-PIO-handling-in-relation-with-numb.patch b/patches.at91/0103-USB-ohci-at91-fix-PIO-handling-in-relation-with-numb.patch new file mode 100644 index 000000000000..4f7467a03a8c --- /dev/null +++ b/patches.at91/0103-USB-ohci-at91-fix-PIO-handling-in-relation-with-numb.patch @@ -0,0 +1,41 @@ +From 42e76043636c925fe4de3223092e587d12a1be2a Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Wed, 29 Aug 2012 11:49:18 +0200 +Subject: USB: ohci-at91: fix PIO handling in relation with number of ports + +If the number of ports present on the SoC/board is not the maximum +and that the platform data is not filled with all data, there is +an easy way to mess the PIO setup for this interface. +This quick fix addresses mis-configuration in USB host platform data +that is common in at91 boards since commit 0ee6d1e (USB: ohci-at91: +change maximum number of ports) that did not modified the associatd +board files. + +Reported-by: Klaus Falkner +Signed-off-by: Nicolas Ferre +Cc: Stable [3.4+] +Acked-by: Alan Stern +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/ohci-at91.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/usb/host/ohci-at91.c ++++ b/drivers/usb/host/ohci-at91.c +@@ -647,6 +647,16 @@ static int __devexit ohci_hcd_at91_drv_r + + if (pdata) { + at91_for_each_port(i) { ++ /* ++ * do not configure PIO if not in relation with ++ * real USB port on board ++ */ ++ if (i >= pdata->ports) { ++ pdata->vbus_pin[i] = -EINVAL; ++ pdata->overcurrent_pin[i] = -EINVAL; ++ break; ++ } ++ + if (!gpio_is_valid(pdata->vbus_pin[i])) + continue; + ohci_at91_usb_set_power(pdata, i, 0); diff --git a/patches.at91/0104-usb-gadget-at91_udc-Propagate-devicetree-to-gadget-d.patch b/patches.at91/0104-usb-gadget-at91_udc-Propagate-devicetree-to-gadget-d.patch new file mode 100644 index 000000000000..014d66dc902d --- /dev/null +++ b/patches.at91/0104-usb-gadget-at91_udc-Propagate-devicetree-to-gadget-d.patch @@ -0,0 +1,28 @@ +From 3be7e4694db4d894b3bbb2252d033a58a8805cf0 Mon Sep 17 00:00:00 2001 +From: Alexandre Pereira da Silva +Date: Tue, 26 Jun 2012 11:27:12 -0300 +Subject: usb: gadget: at91_udc: Propagate devicetree to gadget drivers + +Fill dev.of_node of gadget drivers, so they can use devicetree + +Signed-off-by: Alexandre Pereira da Silva +Signed-off-by: Felipe Balbi +--- + drivers/usb/gadget/at91_udc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c +index ffb46bc..ddeaadb 100644 +--- a/drivers/usb/gadget/at91_udc.c ++++ b/drivers/usb/gadget/at91_udc.c +@@ -1650,6 +1650,7 @@ static int at91_start(struct usb_gadget_driver *driver, + + udc->driver = driver; + udc->gadget.dev.driver = &driver->driver; ++ udc->gadget.dev.of_node = udc->pdev->dev.of_node; + dev_set_drvdata(&udc->gadget.dev, &driver->driver); + udc->enabled = 1; + udc->selfpowered = 1; +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0105-USB-ohci-at91.c-remove-err-usage.patch b/patches.at91/0105-USB-ohci-at91.c-remove-err-usage.patch new file mode 100644 index 000000000000..c90aef45d3d8 --- /dev/null +++ b/patches.at91/0105-USB-ohci-at91.c-remove-err-usage.patch @@ -0,0 +1,34 @@ +From 3b08384658865b98f31a74f07550ac0a562887e8 Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Fri, 27 Apr 2012 11:24:39 -0700 +Subject: USB: ohci-at91.c: remove err() usage + +err() was a very old USB-specific macro that I thought had +gone away. This patch removes it from being used in the +driver and uses dev_err() instead. + +CC: Alan Stern +CC: Grant Likely +CC: Rob Herring +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/ohci-at91.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c +index 5dfea46..aaa8d2b 100644 +--- a/drivers/usb/host/ohci-at91.c ++++ b/drivers/usb/host/ohci-at91.c +@@ -243,7 +243,8 @@ ohci_at91_start (struct usb_hcd *hcd) + int ret; + + if ((ret = ohci_run(ohci)) < 0) { +- err("can't start %s", hcd->self.bus_name); ++ dev_err(hcd->self.controller, "can't start %s\n", ++ hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0107-media-video-atmel-isi-add-dumb-set_parm.patch b/patches.at91/0107-media-video-atmel-isi-add-dumb-set_parm.patch new file mode 100644 index 000000000000..d61092555b68 --- /dev/null +++ b/patches.at91/0107-media-video-atmel-isi-add-dumb-set_parm.patch @@ -0,0 +1,42 @@ +From 705b4b4645cf6f31bc1e267e193388a82b7f2df3 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Fri, 10 Jun 2011 17:21:28 +0200 +Subject: media/video: atmel-isi: add dumb set_parm() + +Add dumb set_parm() & get_parm() function to struct soc_camera_host_ops. +Needed for ffmpeg to be able to capture frames from ISI driver. + +Signed-off-by: Nicolas Ferre +--- + drivers/media/video/atmel-isi.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/media/video/atmel-isi.c b/drivers/media/video/atmel-isi.c +index ec3f6a0..7a44df4 100644 +--- a/drivers/media/video/atmel-isi.c ++++ b/drivers/media/video/atmel-isi.c +@@ -893,6 +893,12 @@ static int isi_camera_set_bus_param(struct soc_camera_device *icd) + return 0; + } + ++ ++static int isi_camera_set_parm(struct soc_camera_device *icd, struct v4l2_streamparm *parm) ++{ ++ return 0; ++} ++ + static struct soc_camera_host_ops isi_soc_camera_host_ops = { + .owner = THIS_MODULE, + .add = isi_camera_add_device, +@@ -904,6 +910,8 @@ static struct soc_camera_host_ops isi_soc_camera_host_ops = { + .poll = isi_camera_poll, + .querycap = isi_camera_querycap, + .set_bus_param = isi_camera_set_bus_param, ++ .set_parm = isi_camera_set_parm, ++ .get_parm = isi_camera_set_parm, + }; + + /* -----------------------------------------------------------------------*/ +-- +1.8.0.197.g5a90748 + diff --git a/patches.at91/0108-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch b/patches.at91/0108-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch new file mode 100644 index 000000000000..4e4c77bc85b9 --- /dev/null +++ b/patches.at91/0108-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch @@ -0,0 +1,1810 @@ +From 5c29a55f144400febf2dfcdc327253b813113c07 Mon Sep 17 00:00:00 2001 +From: Josh Wu +Date: Mon, 1 Nov 2010 16:38:41 +0800 +Subject: video/atmel_lcdfb: add support for AT91SAM9x5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Josh Wu +Signed-off-by: Dan Liang +Signed-off-by: Nicolas Ferre +[ukleinek: forward-port to 2.6.39-rcish] +Signed-off-by: Uwe Kleine-König + +Conflicts: + + drivers/video/atmel_lcdfb.c +--- + arch/arm/mach-at91/include/mach/atmel_hlcdfb.h | 865 +++++++++++++++++++++++++ + drivers/video/atmel_lcdfb.c | 668 ++++++++++++++----- + include/video/atmel_lcdc.h | 15 + + 3 files changed, 1389 insertions(+), 159 deletions(-) + create mode 100644 arch/arm/mach-at91/include/mach/atmel_hlcdfb.h + +diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h b/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h +new file mode 100644 +index 0000000..a57b79b +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h +@@ -0,0 +1,865 @@ ++/* ++ * Header file for AT91 High end LCD Controller ++ * ++ * Data structure and register user interface ++ * ++ * Copyright (C) 2010 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ATMEL_HLCD_H__ ++#define __ATMEL_HLCD_H__ ++ ++/* Lcdc hardware registers */ ++#define ATMEL_LCDC_LCDCFG0 0x0000 ++#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) ++#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) ++#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) ++#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) ++#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) ++#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) ++#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) ++#define LCDC_LCDCFG0_CLKDIV_OFFSET 16 ++#define LCDC_LCDCFG0_CLKDIV (0xff << LCDC_LCDCFG0_CLKDIV_OFFSET) ++ ++#define ATMEL_LCDC_LCDCFG1 0x0004 ++#define LCDC_LCDCFG1_HSPW_OFFSET 0 ++#define LCDC_LCDCFG1_HSPW (0x3f << LCDC_LCDCFG1_HSPW_OFFSET) ++#define LCDC_LCDCFG1_VSPW_OFFSET 16 ++#define LCDC_LCDCFG1_VSPW (0x3f << LCDC_LCDCFG1_VSPW_OFFSET) ++ ++#define ATMEL_LCDC_LCDCFG2 0x0008 ++#define LCDC_LCDCFG2_VFPW_OFFSET 0 ++#define LCDC_LCDCFG2_VFPW (0x3f << LCDC_LCDCFG2_VFPW_OFFSET) ++#define LCDC_LCDCFG2_VBPW_OFFSET 16 ++#define LCDC_LCDCFG2_VBPW (0x3f << LCDC_LCDCFG2_VBPW_OFFSET) ++ ++#define ATMEL_LCDC_LCDCFG3 0x000C ++#define LCDC_LCDCFG3_HFPW_OFFSET 0 ++#define LCDC_LCDCFG3_HFPW (0xff << LCDC_LCDCFG3_HFPW_OFFSET) ++#define LCDC_LCDCFG3_HBPW_OFFSET 16 ++#define LCDC_LCDCFG3_HBPW (0xff << LCDC_LCDCFG3_HBPW_OFFSET) ++ ++#define ATMEL_LCDC_LCDCFG4 0x0010 ++#define LCDC_LCDCFG4_PPL_OFFSET 0 ++#define LCDC_LCDCFG4_PPL (0x7ff << LCDC_LCDCFG4_PPL_OFFSET) ++#define LCDC_LCDCFG4_RPF_OFFSET 16 ++#define LCDC_LCDCFG4_RPF (0x7ff << LCDC_LCDCFG4_RPF_OFFSET) ++ ++#define ATMEL_LCDC_LCDCFG5 0x0014 ++#define LCDC_LCDCFG5_HSPOL (0x1 << 0) ++#define LCDC_LCDCFG5_VSPOL (0x1 << 1) ++#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) ++#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) ++#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) ++#define LCDC_LCDCFG5_SERIAL (0x1 << 5) ++#define LCDC_LCDCFG5_DITHER (0x1 << 6) ++#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) ++#define LCDC_LCDCFG5_MODE_OFFSET 8 ++#define LCDC_LCDCFG5_MODE (0x3 << LCDC_LCDCFG5_MODE_OFFSET) ++#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) ++#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) ++#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) ++#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) ++#define LCDC_LCDCFG5_VSPSU (0x1 << 12) ++#define LCDC_LCDCFG5_VSPHO (0x1 << 13) ++#define LCDC_LCDCFG5_GUARDTIME_OFFSET 16 ++#define LCDC_LCDCFG5_GUARDTIME (0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET) ++ ++#define ATMEL_LCDC_LCDCFG6 0x0018 ++#define LCDC_LCDCFG6_PWMPS_OFFSET 0 ++#define LCDC_LCDCFG6_PWMPS (0x7 << LCDC_LCDCFG6_PWMPS_OFFSET) ++#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) ++#define LCDC_LCDCFG6_PWMCVAL_OFFSET 8 ++#define LCDC_LCDCFG6_PWMCVAL (0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET) ++ ++#define ATMEL_LCDC_LCDEN 0x0020 ++#define LCDC_LCDEN_CLKEN (0x1 << 0) ++#define LCDC_LCDEN_SYNCEN (0x1 << 1) ++#define LCDC_LCDEN_DISPEN (0x1 << 2) ++#define LCDC_LCDEN_PWMEN (0x1 << 3) ++ ++#define ATMEL_LCDC_LCDDIS 0x0024 ++#define LCDC_LCDDIS_CLKDIS (0x1 << 0) ++#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) ++#define LCDC_LCDDIS_DISPDIS (0x1 << 2) ++#define LCDC_LCDDIS_PWMDIS (0x1 << 3) ++#define LCDC_LCDDIS_CLKRST (0x1 << 8) ++#define LCDC_LCDDIS_SYNCRST (0x1 << 9) ++#define LCDC_LCDDIS_DISPRST (0x1 << 10) ++#define LCDC_LCDDIS_PWMRST (0x1 << 11) ++ ++#define ATMEL_LCDC_LCDSR 0x0028 ++#define LCDC_LCDSR_CLKSTS (0x1 << 0) ++#define LCDC_LCDSR_LCDSTS (0x1 << 1) ++#define LCDC_LCDSR_DISPSTS (0x1 << 2) ++#define LCDC_LCDSR_PWMSTS (0x1 << 3) ++#define LCDC_LCDSR_SIPSTS (0x1 << 4) ++ ++#define ATMEL_LCDC_LCDIER 0x002C ++#define LCDC_LCDIER_SOFIE (0x1 << 0) ++#define LCDC_LCDIER_DISIE (0x1 << 1) ++#define LCDC_LCDIER_DISPIE (0x1 << 2) ++#define LCDC_LCDIER_FIFOERRIE (0x1 << 4) ++#define LCDC_LCDIER_BASEIE (0x1 << 8) ++#define LCDC_LCDIER_OVR1IE (0x1 << 9) ++#define LCDC_LCDIER_HEOIE (0x1 << 11) ++#define LCDC_LCDIER_HCRIE (0x1 << 12) ++ ++#define ATMEL_LCDC_LCDIDR 0x0030 ++#define LCDC_LCDIDR_SOFID (0x1 << 0) ++#define LCDC_LCDIDR_DISID (0x1 << 1) ++#define LCDC_LCDIDR_DISPID (0x1 << 2) ++#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) ++#define LCDC_LCDIDR_BASEID (0x1 << 8) ++#define LCDC_LCDIDR_OVR1ID (0x1 << 9) ++#define LCDC_LCDIDR_HEOID (0x1 << 11) ++#define LCDC_LCDIDR_HCRID (0x1 << 12) ++ ++#define ATMEL_LCDC_LCDIMR 0x0034 ++#define LCDC_LCDIMR_SOFIM (0x1 << 0) ++#define LCDC_LCDIMR_DISIM (0x1 << 1) ++#define LCDC_LCDIMR_DISPIM (0x1 << 2) ++#define LCDC_LCDIMR_FIFOERRIM (0x1 << 4) ++#define LCDC_LCDIMR_BASEIM (0x1 << 8) ++#define LCDC_LCDIMR_OVR1IM (0x1 << 9) ++#define LCDC_LCDIMR_HEOIM (0x1 << 11) ++#define LCDC_LCDIMR_HCRIM (0x1 << 12) ++ ++#define ATMEL_LCDC_LCDISR 0x0038 ++#define LCDC_LCDISR_SOF (0x1 << 0) ++#define LCDC_LCDISR_DIS (0x1 << 1) ++#define LCDC_LCDISR_DISP (0x1 << 2) ++#define LCDC_LCDISR_FIFOERR (0x1 << 4) ++#define LCDC_LCDISR_BASE (0x1 << 8) ++#define LCDC_LCDISR_OVR1 (0x1 << 9) ++#define LCDC_LCDISR_HEO (0x1 << 11) ++#define LCDC_LCDISR_HCR (0x1 << 12) ++ ++#define ATMEL_LCDC_BASECHER 0x0040 ++#define LCDC_BASECHER_CHEN (0x1 << 0) ++#define LCDC_BASECHER_UPDATEEN (0x1 << 1) ++#define LCDC_BASECHER_A2QEN (0x1 << 2) ++ ++#define ATMEL_LCDC_BASECHDR 0x0044 ++#define LCDC_BASECHDR_CHDIS (0x1 << 0) ++#define LCDC_BASECHDR_CHRST (0x1 << 8) ++ ++#define ATMEL_LCDC_BASECHSR 0x0048 ++#define LCDC_BASECHSR_CHSR (0x1 << 0) ++#define LCDC_BASECHSR_UPDATESR (0x1 << 1) ++#define LCDC_BASECHSR_A2QSR (0x1 << 2) ++ ++#define ATMEL_LCDC_BASEIER 0x004C ++#define LCDC_BASEIER_DMA (0x1 << 2) ++#define LCDC_BASEIER_DSCR (0x1 << 3) ++#define LCDC_BASEIER_ADD (0x1 << 4) ++#define LCDC_BASEIER_DONE (0x1 << 5) ++#define LCDC_BASEIER_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_BASEIDR 0x0050 ++#define LCDC_BASEIDR_DMA (0x1 << 2) ++#define LCDC_BASEIDR_DSCR (0x1 << 3) ++#define LCDC_BASEIDR_ADD (0x1 << 4) ++#define LCDC_BASEIDR_DONE (0x1 << 5) ++#define LCDC_BASEIDR_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_BASEIMR 0x0054 ++#define LCDC_BASEIMR_DMA (0x1 << 2) ++#define LCDC_BASEIMR_DSCR (0x1 << 3) ++#define LCDC_BASEIMR_ADD (0x1 << 4) ++#define LCDC_BASEIMR_DONE (0x1 << 5) ++#define LCDC_BASEIMR_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_BASEISR 0x0058 ++#define LCDC_BASEISR_DMA (0x1 << 2) ++#define LCDC_BASEISR_DSCR (0x1 << 3) ++#define LCDC_BASEISR_ADD (0x1 << 4) ++#define LCDC_BASEISR_DONE (0x1 << 5) ++#define LCDC_BASEISR_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_BASEHEAD 0x005C ++ ++#define ATMEL_LCDC_BASEADDR 0x0060 ++ ++#define ATMEL_LCDC_BASECTRL 0x0064 ++#define LCDC_BASECTRL_DFETCH (0x1 << 0) ++#define LCDC_BASECTRL_LFETCH (0x1 << 1) ++#define LCDC_BASECTRL_DMAIEN (0x1 << 2) ++#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) ++#define LCDC_BASECTRL_ADDIEN (0x1 << 4) ++#define LCDC_BASECTRL_DONEIEN (0x1 << 5) ++ ++#define ATMEL_LCDC_BASENEXT 0x0068 ++ ++#define ATMEL_LCDC_BASECFG0 0x006C ++#define LCDC_BASECFG0_BLEN_OFFSET 4 ++#define LCDC_BASECFG0_BLEN (0x3 << LCDC_BASECFG0_BLEN_OFFSET) ++#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) ++#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) ++#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) ++#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) ++#define LCDC_BASECFG0_DLBO (0x1 << 8) ++ ++#define ATMEL_LCDC_BASECFG1 0x0070 ++#define LCDC_BASECFG1_CLUTEN (0x1 << 0) ++#define LCDC_BASECFG1_RGBMODE_OFFSET 4 ++#define LCDC_BASECFG1_RGBMODE (0xf << LCDC_BASECFG1_RGBMODE_OFFSET) ++#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) ++#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) ++#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) ++#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) ++#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) ++#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) ++#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) ++#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) ++#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) ++#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) ++#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) ++#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) ++#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) ++#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) ++#define LCDC_BASECFG1_CLUTMODE_OFFSET 8 ++#define LCDC_BASECFG1_CLUTMODE (0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET) ++#define LCDC_BASECFG1_CLUTMODE_1BPP (0x0 << 8) ++#define LCDC_BASECFG1_CLUTMODE_2BPP (0x1 << 8) ++#define LCDC_BASECFG1_CLUTMODE_4BPP (0x2 << 8) ++#define LCDC_BASECFG1_CLUTMODE_8BPP (0x3 << 8) ++ ++#define ATMEL_LCDC_BASECFG2 0x0074 ++ ++#define ATMEL_LCDC_BASECFG3 0x0078 ++#define LCDC_BASECFG3_BDEF_OFFSET 0 ++#define LCDC_BASECFG3_BDEF (0xff << LCDC_BASECFG3_BDEF_OFFSET) ++#define LCDC_BASECFG3_GDEF_OFFSET 8 ++#define LCDC_BASECFG3_GDEF (0xff << LCDC_BASECFG3_GDEF_OFFSET) ++#define LCDC_BASECFG3_RDEF_OFFSET 16 ++#define LCDC_BASECFG3_RDEF (0xff << LCDC_BASECFG3_RDEF_OFFSET) ++ ++#define ATMEL_LCDC_BASECFG4 0x007C ++#define LCDC_BASECFG4_DMA (0x1 << 8) ++#define LCDC_BASECFG4_REP (0x1 << 9) ++ ++#define ATMEL_LCDC_OVRCHER1 0x0100 ++#define LCDC_OVRCHER1_CHEN (0x1 << 0) ++#define LCDC_OVRCHER1_UPDATEEN (0x1 << 1) ++#define LCDC_OVRCHER1_A2QEN (0x1 << 2) ++ ++#define ATMEL_LCDC_OVRCHDR1 0x0104 ++#define LCDC_OVRCHDR1_CHDIS (0x1 << 0) ++#define LCDC_OVRCHDR1_CHRST (0x1 << 8) ++ ++#define ATMEL_LCDC_OVRCHSR1 0x0108 ++#define LCDC_OVRCHSR1_CHSR (0x1 << 0) ++#define LCDC_OVRCHSR1_UPDATESR (0x1 << 1) ++#define LCDC_OVRCHSR1_A2QSR (0x1 << 2) ++ ++#define ATMEL_LCDC_OVRIER1 0x010C ++#define LCDC_OVRIER1_DMA (0x1 << 2) ++#define LCDC_OVRIER1_DSCR (0x1 << 3) ++#define LCDC_OVRIER1_ADD (0x1 << 4) ++#define LCDC_OVRIER1_DONE (0x1 << 5) ++#define LCDC_OVRIER1_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_OVRIDR1 0x0110 ++#define LCDC_OVRIDR1_DMA (0x1 << 2) ++#define LCDC_OVRIDR1_DSCR (0x1 << 3) ++#define LCDC_OVRIDR1_ADD (0x1 << 4) ++#define LCDC_OVRIDR1_DONE (0x1 << 5) ++#define LCDC_OVRIDR1_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_OVRIMR1 0x0114 ++#define LCDC_OVRIMR1_DMA (0x1 << 2) ++#define LCDC_OVRIMR1_DSCR (0x1 << 3) ++#define LCDC_OVRIMR1_ADD (0x1 << 4) ++#define LCDC_OVRIMR1_DONE (0x1 << 5) ++#define LCDC_OVRIMR1_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_OVRISR1 0x0118 ++#define LCDC_OVRISR1_DMA (0x1 << 2) ++#define LCDC_OVRISR1_DSCR (0x1 << 3) ++#define LCDC_OVRISR1_ADD (0x1 << 4) ++#define LCDC_OVRISR1_DONE (0x1 << 5) ++#define LCDC_OVRISR1_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_OVRHEAD1 0x011C ++ ++#define ATMEL_LCDC_OVRADDR1 0x0120 ++ ++#define ATMEL_LCDC_OVRCTRL1 0x0124 ++#define LCDC_OVRCTRL1_DFETCH (0x1 << 0) ++#define LCDC_OVRCTRL1_LFETCH (0x1 << 1) ++#define LCDC_OVRCTRL1_DMAIEN (0x1 << 2) ++#define LCDC_OVRCTRL1_DSCRIEN (0x1 << 3) ++#define LCDC_OVRCTRL1_ADDIEN (0x1 << 4) ++#define LCDC_OVRCTRL1_DONEIEN (0x1 << 5) ++ ++#define ATMEL_LCDC_OVRNEXT1 0x0128 ++ ++#define ATMEL_LCDC_OVR1CFG0 0x012C ++#define LCDC_OVR1CFG0_BLEN_OFFSET 4 ++#define LCDC_OVR1CFG0_BLEN (0x3 << LCDC_OVR1CFG0_BLEN_OFFSET) ++#define LCDC_OVR1CFG0_BLEN_AHB_SINGLE (0x0 << 4) ++#define LCDC_OVR1CFG0_BLEN_AHB_INCR4 (0x1 << 4) ++#define LCDC_OVR1CFG0_BLEN_AHB_INCR8 (0x2 << 4) ++#define LCDC_OVR1CFG0_BLEN_AHB_INCR16 (0x3 << 4) ++#define LCDC_OVR1CFG0_DLBO (0x1 << 8) ++#define LCDC_OVR1CFG0_ROTDIS (0x1 << 12) ++#define LCDC_OVR1CFG0_LOCKDIS (0x1 << 13) ++ ++#define ATMEL_LCDC_OVR1CFG1 0x0130 ++#define LCDC_OVR1CFG1_CLUTEN (0x1 << 0) ++#define LCDC_OVR1CFG1_RGBMODE_OFFSET 4 ++#define LCDC_OVR1CFG1_RGBMODE (0xf << LCDC_OVR1CFG1_RGBMODE_OFFSET) ++#define LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) ++#define LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) ++#define LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) ++#define LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) ++#define LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) ++#define LCDC_OVR1CFG1_CLUTMODE_OFFSET 8 ++#define LCDC_OVR1CFG1_CLUTMODE (0x3 << LCDC_OVR1CFG1_CLUTMODE_OFFSET) ++#define LCDC_OVR1CFG1_CLUTMODE_1BPP (0x0 << 8) ++#define LCDC_OVR1CFG1_CLUTMODE_2BPP (0x1 << 8) ++#define LCDC_OVR1CFG1_CLUTMODE_4BPP (0x2 << 8) ++#define LCDC_OVR1CFG1_CLUTMODE_8BPP (0x3 << 8) ++ ++#define ATMEL_LCDC_OVR1CFG2 0x0134 ++#define LCDC_OVR1CFG2_XOFFSET_OFFSET 0 ++#define LCDC_OVR1CFG2_XOFFSET (0x7ff << LCDC_OVR1CFG2_XOFFSET_OFFSET) ++#define LCDC_OVR1CFG2_YOFFSET_OFFSET 16 ++#define LCDC_OVR1CFG2_YOFFSET (0x7ff << LCDC_OVR1CFG2_YOFFSET_OFFSET) ++ ++#define ATMEL_LCDC_OVR1CFG3 0x0138 ++#define LCDC_OVR1CFG3_XSIZE_OFFSET 0 ++#define LCDC_OVR1CFG3_XSIZE (0x7ff << LCDC_OVR1CFG3_XSIZE_OFFSET) ++#define LCDC_OVR1CFG3_YSIZE_OFFSET 16 ++#define LCDC_OVR1CFG3_YSIZE (0x7ff << LCDC_OVR1CFG3_YSIZE_OFFSET) ++ ++#define ATMEL_LCDC_OVR1CFG4 0x013C ++ ++#define ATMEL_LCDC_OVR1CFG5 0x0140 ++ ++#define ATMEL_LCDC_OVR1CFG6 0x0144 ++#define LCDC_OVR1CFG6_BDEF_OFFSET 0 ++#define LCDC_OVR1CFG6_BDEF (0xff << LCDC_OVR1CFG6_BDEF_OFFSET) ++#define LCDC_OVR1CFG6_GDEF_OFFSET 8 ++#define LCDC_OVR1CFG6_GDEF (0xff << LCDC_OVR1CFG6_GDEF_OFFSET) ++#define LCDC_OVR1CFG6_RDEF_OFFSET 16 ++#define LCDC_OVR1CFG6_RDEF (0xff << LCDC_OVR1CFG6_RDEF_OFFSET) ++ ++#define ATMEL_LCDC_OVR1CFG7 0x0148 ++#define LCDC_OVR1CFG7_BKEY_OFFSET 0 ++#define LCDC_OVR1CFG7_BKEY (0xff << LCDC_OVR1CFG7_BKEY_OFFSET) ++#define LCDC_OVR1CFG7_GKEY_OFFSET 8 ++#define LCDC_OVR1CFG7_GKEY (0xff << LCDC_OVR1CFG7_GKEY_OFFST) ++#define LCDC_OVR1CFG7_RKEY_OFFSET 16 ++#define LCDC_OVR1CFG7_RKEY (0xff << LCDC_OVR1CFG7_RKEY_OFFSET) ++ ++#define ATMEL_LCDC_OVR1CFG8 0x014C ++#define LCDC_OVR1CFG8_BMASK_OFFSET 0 ++#define LCDC_OVR1CFG8_BMASK (0xff << LCDC_OVR1CFG8_BMASK_OFFSET) ++#define LCDC_OVR1CFG8_GMASK_OFFSET 8 ++#define LCDC_OVR1CFG8_GMASK (0xff << LCDC_OVR1CFG8_GMASK_OFFSET) ++#define LCDC_OVR1CFG8_RMASK_OFFSET 16 ++#define LCDC_OVR1CFG8_RMASK (0xff << LCDC_OVR1CFG8_RMASK_OFFSET) ++ ++#define ATMEL_LCDC_OVR1CFG9 0x0150 ++#define LCDC_OVR1CFG9_CRKEY (0x1 << 0) ++#define LCDC_OVR1CFG9_INV (0x1 << 1) ++#define LCDC_OVR1CFG9_ITER2BL (0x1 << 2) ++#define LCDC_OVR1CFG9_ITER (0x1 << 3) ++#define LCDC_OVR1CFG9_REVALPHA (0x1 << 4) ++#define LCDC_OVR1CFG9_GAEN (0x1 << 5) ++#define LCDC_OVR1CFG9_LAEN (0x1 << 6) ++#define LCDC_OVR1CFG9_OVR (0x1 << 7) ++#define LCDC_OVR1CFG9_DMA (0x1 << 8) ++#define LCDC_OVR1CFG9_REP (0x1 << 9) ++#define LCDC_OVR1CFG9_DSTKEY (0x1 << 10) ++#define LCDC_OVR1CFG9_GA_OFFSET 16 ++#define LCDC_OVR1CFG9_GA (0xff << LCDC_OVR1CFG9_GA_OFFSET) ++ ++#define ATMEL_LCDC_HEOCHER 0x0280 ++#define LCDC_HEOCHER_CHEN (0x1 << 0) ++#define LCDC_HEOCHER_UPDATEEN (0x1 << 1) ++#define LCDC_HEOCHER_A2QEN (0x1 << 2) ++ ++#define ATMEL_LCDC_HEOCHDR 0x0284 ++#define LCDC_HEOCHDR_CHDIS (0x1 << 0) ++#define LCDC_HEOCHDR_CHRST (0x1 << 8) ++ ++#define ATMEL_LCDC_HEOCHSR 0x0288 ++#define LCDC_HEOCHSR_CHSR (0x1 << 0) ++#define LCDC_HEOCHSR_UPDATESR (0x1 << 1) ++#define LCDC_HEOCHSR_A2QSR (0x1 << 2) ++ ++#define ATMEL_LCDC_HEOIER 0x028C ++#define LCDC_HEOIER_DMA (0x1 << 2) ++#define LCDC_HEOIER_DSCR (0x1 << 3) ++#define LCDC_HEOIER_ADD (0x1 << 4) ++#define LCDC_HEOIER_DONE (0x1 << 5) ++#define LCDC_HEOIER_OVR (0x1 << 6) ++#define LCDC_HEOIER_UDMA (0x1 << 10) ++#define LCDC_HEOIER_UDSCR (0x1 << 11) ++#define LCDC_HEOIER_UADD (0x1 << 12) ++#define LCDC_HEOIER_UDONE (0x1 << 13) ++#define LCDC_HEOIER_UOVR (0x1 << 14) ++#define LCDC_HEOIER_VDMA (0x1 << 18) ++#define LCDC_HEOIER_VDSCR (0x1 << 19) ++#define LCDC_HEOIER_VADD (0x1 << 20) ++#define LCDC_HEOIER_VDONE (0x1 << 21) ++#define LCDC_HEOIER_VOVR (0x1 << 22) ++ ++#define ATMEL_LCDC_HEOIDR 0x0290 ++#define LCDC_HEOIDR_DMA (0x1 << 2) ++#define LCDC_HEOIDR_DSCR (0x1 << 3) ++#define LCDC_HEOIDR_ADD (0x1 << 4) ++#define LCDC_HEOIDR_DONE (0x1 << 5) ++#define LCDC_HEOIDR_OVR (0x1 << 6) ++#define LCDC_HEOIDR_UDMA (0x1 << 10) ++#define LCDC_HEOIDR_UDSCR (0x1 << 11) ++#define LCDC_HEOIDR_UADD (0x1 << 12) ++#define LCDC_HEOIDR_UDONE (0x1 << 13) ++#define LCDC_HEOIDR_UOVR (0x1 << 14) ++#define LCDC_HEOIDR_VDMA (0x1 << 18) ++#define LCDC_HEOIDR_VDSCR (0x1 << 19) ++#define LCDC_HEOIDR_VADD (0x1 << 20) ++#define LCDC_HEOIDR_VDONE (0x1 << 21) ++#define LCDC_HEOIDR_VOVR (0x1 << 22) ++ ++#define ATMEL_LCDC_HEOIMR 0x0294 ++#define LCDC_HEOIMR_DMA (0x1 << 2) ++#define LCDC_HEOIMR_DSCR (0x1 << 3) ++#define LCDC_HEOIMR_ADD (0x1 << 4) ++#define LCDC_HEOIMR_DONE (0x1 << 5) ++#define LCDC_HEOIMR_OVR (0x1 << 6) ++#define LCDC_HEOIMR_UDMA (0x1 << 10) ++#define LCDC_HEOIMR_UDSCR (0x1 << 11) ++#define LCDC_HEOIMR_UADD (0x1 << 12) ++#define LCDC_HEOIMR_UDONE (0x1 << 13) ++#define LCDC_HEOIMR_UOVR (0x1 << 14) ++#define LCDC_HEOIMR_VDMA (0x1 << 18) ++#define LCDC_HEOIMR_VDSCR (0x1 << 19) ++#define LCDC_HEOIMR_VADD (0x1 << 20) ++#define LCDC_HEOIMR_VDONE (0x1 << 21) ++#define LCDC_HEOIMR_VOVR (0x1 << 22) ++ ++#define ATMEL_LCDC_HEOISR 0x0298 ++#define LCDC_HEOISR_DMA (0x1 << 2) ++#define LCDC_HEOISR_DSCR (0x1 << 3) ++#define LCDC_HEOISR_ADD (0x1 << 4) ++#define LCDC_HEOISR_DONE (0x1 << 5) ++#define LCDC_HEOISR_OVR (0x1 << 6) ++#define LCDC_HEOISR_UDMA (0x1 << 10) ++#define LCDC_HEOISR_UDSCR (0x1 << 11) ++#define LCDC_HEOISR_UADD (0x1 << 12) ++#define LCDC_HEOISR_UDONE (0x1 << 13) ++#define LCDC_HEOISR_UOVR (0x1 << 14) ++#define LCDC_HEOISR_VDMA (0x1 << 18) ++#define LCDC_HEOISR_VDSCR (0x1 << 19) ++#define LCDC_HEOISR_VADD (0x1 << 20) ++#define LCDC_HEOISR_VDONE (0x1 << 21) ++#define LCDC_HEOISR_VOVR (0x1 << 22) ++ ++#define ATMEL_LCDC_HEOHEAD 0x029C ++ ++#define ATMEL_LCDC_HEOADDR 0x02A0 ++ ++#define ATMEL_LCDC_HEOCTRL 0x02A4 ++#define LCDC_HEOCTRL_DFETCH (0x1 << 0) ++#define LCDC_HEOCTRL_LFETCH (0x1 << 1) ++#define LCDC_HEOCTRL_DMAIEN (0x1 << 2) ++#define LCDC_HEOCTRL_DSCRIEN (0x1 << 3) ++#define LCDC_HEOCTRL_ADDIEN (0x1 << 4) ++#define LCDC_HEOCTRL_DONEIEN (0x1 << 5) ++ ++#define ATMEL_LCDC_HEONEXT 0x02A8 ++ ++#define ATMEL_LCDC_HEOUHEAD 0x02AC ++ ++#define ATMEL_LCDC_HEOUADDR 0x02B0 ++ ++#define ATMEL_LCDC_HEOUCTRL 0x02B4 ++#define LCDC_HEOUCTRL_UDFETCH (0x1 << 0) ++#define LCDC_HEOUCTRL_UDMAIEN (0x1 << 2) ++#define LCDC_HEOUCTRL_UDSCRIEN (0x1 << 3) ++#define LCDC_HEOUCTRL_UADDIEN (0x1 << 4) ++#define LCDC_HEOUCTRL_UDONEIEN (0x1 << 5) ++ ++#define ATMEL_LCDC_HEOUNEXT 0x02B8 ++ ++#define ATMEL_LCDC_HEOVHEAD 0x02BC ++ ++#define ATMEL_LCDC_HEOVADDR 0x02C0 ++ ++#define ATMEL_LCDC_HEOVCTRL 0x02C4 ++#define LCDC_HEOVCTRL_VDFETCH (0x1 << 0) ++#define LCDC_HEOVCTRL_VDMAIEN (0x1 << 2) ++#define LCDC_HEOVCTRL_VDSCRIEN (0x1 << 3) ++#define LCDC_HEOVCTRL_VADDIEN (0x1 << 4) ++#define LCDC_HEOVCTRL_VDONEIEN (0x1 << 5) ++ ++#define ATMEL_LCDC_HEOVNEXT 0x02C8 ++ ++#define ATMEL_LCDC_HEOCFG0 0x02CC ++#define LCDC_HEOCFG0_BLEN_OFFSET 4 ++#define LCDC_HEOCFG0_BLEN (0x3 << LCDC_HEOCFG0_BLEN_OFFSET) ++#define LCDC_HEOCFG0_BLEN_AHB_SINGLE (0x0 << 4) ++#define LCDC_HEOCFG0_BLEN_AHB_INCR4 (0x1 << 4) ++#define LCDC_HEOCFG0_BLEN_AHB_INCR8 (0x2 << 4) ++#define LCDC_HEOCFG0_BLEN_AHB_INCR16 (0x3 << 4) ++#define LCDC_HEOCFG0_BLENUV_OFFSET 6 ++#define LCDC_HEOCFG0_BLENUV (0x3 << LCDC_HEOCFG0_BLENUV_OFFSET) ++#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0 << 6) ++#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1 << 6) ++#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2 << 6) ++#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3 << 6) ++#define LCDC_HEOCFG0_DLBO (0x1 << 8) ++#define LCDC_HEOCFG0_ROTDIS (0x1 << 12) ++#define LCDC_HEOCFG0_LOCKDIS (0x1 << 13) ++ ++#define ATMEL_LCDC_HEOCFG1 0x02D0 ++#define LCDC_HEOCFG1_CLUTEN (0x1 << 0) ++#define LCDC_HEOCFG1_YUVEN (0x1 << 1) ++#define LCDC_HEOCFG1_RGBMODE_OFFSET 4 ++#define LCDC_HEOCFG1_RGBMODE (0xf << LCDC_HEOCFG1_RGBMODE_OFFSET) ++#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) ++#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) ++#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) ++#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) ++#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) ++#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) ++#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) ++#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) ++#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) ++#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) ++#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) ++#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) ++#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) ++#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) ++#define LCDC_HEOCFG1_CLUTMODE_OFFSET 8 ++#define LCDC_HEOCFG1_CLUTMODE (0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET) ++#define LCDC_HEOCFG1_CLUTMODE_1BPP (0x0 << 8) ++#define LCDC_HEOCFG1_CLUTMODE_2BPP (0x1 << 8) ++#define LCDC_HEOCFG1_CLUTMODE_4BPP (0x2 << 8) ++#define LCDC_HEOCFG1_CLUTMODE_8BPP (0x3 << 8) ++#define LCDC_HEOCFG1_YUVMODE_OFFSET 12 ++#define LCDC_HEOCFG1_YUVMODE (0xf << LCDC_HEOCFG1_YUVMODE_OFFSET) ++#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0 << 12) ++#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1 << 12) ++#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2 << 12) ++#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3 << 12) ++#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4 << 12) ++#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5 << 12) ++#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6 << 12) ++#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7 << 12) ++#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8 << 12) ++#define LCDC_HEOCFG1_YUV422ROT (0x1 << 16) ++#define LCDC_HEOCFG1_YUV422SWP (0x1 << 17) ++ ++#define ATMEL_LCDC_HEOCFG2 0x02D4 ++#define LCDC_HEOCFG2_XOFFSET_OFFSET 0 ++#define LCDC_HEOCFG2_XOFFSET (0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET) ++#define LCDC_HEOCFG2_YOFFSET_OFFSET 16 ++#define LCDC_HEOCFG2_YOFFSET (0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG3 0x02D8 ++#define LCDC_HEOCFG3_XSIZE_OFFSET 0 ++#define LCDC_HEOCFG3_XSIZE (0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET) ++#define LCDC_HEOCFG3_YSIZE_OFFSET 16 ++#define LCDC_HEOCFG3_YSIZE (0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG4 0x02DC ++#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET 0 ++#define LCDC_HEOCFG4_XMEM_SIZE (0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET) ++#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET 16 ++#define LCDC_HEOCFG4_YMEM_SIZE (0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG5 0x02E0 ++ ++#define ATMEL_LCDC_HEOCFG6 0x02E4 ++ ++#define ATMEL_LCDC_HEOCFG7 0x02E8 ++ ++#define ATMEL_LCDC_HEOCFG8 0x02EC ++ ++#define ATMEL_LCDC_HEOCFG9 0x02F0 ++#define LCDC_HEOCFG9_BDEF_OFFSET 0 ++#define LCDC_HEOCFG9_BDEF (0xff << LCDC_HEOCFG9_BDEF_OFFSET) ++#define LCDC_HEOCFG9_GDEF_OFFSET 8 ++#define LCDC_HEOCFG9_GDEF (0xff << LCDC_HEOCFG9_GDEF_OFFSET) ++#define LCDC_HEOCFG9_RDEF_OFFSET 16 ++#define LCDC_HEOCFG9_RDEF (0xff << LCDC_HEOCFG9_RDEF_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG10 0x02F4 ++#define LCDC_HEOCFG10_BKEY_OFFSET 0 ++#define LCDC_HEOCFG10_BKEY (0xff << LCDC_HEOCFG10_BKEY_OFFSET) ++#define LCDC_HEOCFG10_GKEY_OFFSET 8 ++#define LCDC_HEOCFG10_GKEY (0xff << LCDC_HEOCFG10_GKEY_OFFSET) ++#define LCDC_HEOCFG10_RKEY_OFFSET 16 ++#define LCDC_HEOCFG10_RKEY (0xff << LCDC_HEOCFG10_RKEY_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG11 0x02F8 ++#define LCDC_HEOCFG11_BMASK_OFFSET 0 ++#define LCDC_HEOCFG11_BMASK (0xff << LCDC_HEOCFG11_BMASK_OFFSET) ++#define LCDC_HEOCFG11_GMASK_OFFSET 8 ++#define LCDC_HEOCFG11_GMASK (0xff << LCDC_HEOCFG11_GMASK_OFFSET) ++#define LCDC_HEOCFG11_RMASK_OFFSET 16 ++#define LCDC_HEOCFG11_RMASK (0xff << LCDC_HEOCFG11_RMASK_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG12 0x02FC ++#define LCDC_HEOCFG12_CRKEY (0x1 << 0) ++#define LCDC_HEOCFG12_INV (0x1 << 1) ++#define LCDC_HEOCFG12_ITER2BL (0x1 << 2) ++#define LCDC_HEOCFG12_ITER (0x1 << 3) ++#define LCDC_HEOCFG12_REVALPHA (0x1 << 4) ++#define LCDC_HEOCFG12_GAEN (0x1 << 5) ++#define LCDC_HEOCFG12_LAEN (0x1 << 6) ++#define LCDC_HEOCFG12_OVR (0x1 << 7) ++#define LCDC_HEOCFG12_DMA (0x1 << 8) ++#define LCDC_HEOCFG12_REP (0x1 << 9) ++#define LCDC_HEOCFG12_DSTKEY (0x1 << 10) ++#define LCDC_HEOCFG12_VIDPRI (0x1 << 12) ++#define LCDC_HEOCFG12_GA_OFFSET 16 ++#define LCDC_HEOCFG12_GA (0xff << LCDC_HEOCFG12_GA_OFFSET) ++ ++#define ATMEL_LCDC_HEOCFG13 0x0300 ++#define LCDC_HEOCFG13_XFACTOR_OFFSET 0 ++#define LCDC_HEOCFG13_XFACTOR (0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET) ++#define LCDC_HEOCFG13_YFACTOR_OFFSET 16 ++#define LCDC_HEOCFG13_YFACTOR (0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET) ++#define LCDC_HEOCFG13_SCALEN (0x1 << 31) ++ ++#define ATMEL_LCDC_HEOCFG14 0x0304 ++#define LCDC_HEOCFG14_CSCRY_OFFSET 0 ++#define LCDC_HEOCFG14_CSCRY (0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET) ++#define LCDC_HEOCFG14_CSCRU_OFFSET 10 ++#define LCDC_HEOCFG14_CSCRU (0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET) ++#define LCDC_HEOCFG14_CSCRV_OFFSET 20 ++#define LCDC_HEOCFG14_CSCRV (0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET) ++#define LCDC_HEOCFG14_CSCYOFF (0x1 << 30) ++ ++#define ATMEL_LCDC_HEOCFG15 0x0308 ++#define LCDC_HEOCFG15_CSCGY_OFFSET 0 ++#define LCDC_HEOCFG15_CSCGY (0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET) ++#define LCDC_HEOCFG15_CSCGU_OFFSET 10 ++#define LCDC_HEOCFG15_CSCGU (0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET) ++#define LCDC_HEOCFG15_CSCGV_OFFSET 20 ++#define LCDC_HEOCFG15_CSCGV (0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET) ++#define LCDC_HEOCFG15_CSCUOFF (0x1 << 30) ++ ++#define ATMEL_LCDC_HEOCFG16 0x030C ++#define LCDC_HEOCFG16_CSCBY_OFFSET 0 ++#define LCDC_HEOCFG16_CSCBY (0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET) ++#define LCDC_HEOCFG16_CSCBU_OFFSET 10 ++#define LCDC_HEOCFG16_CSCBU (0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET) ++#define LCDC_HEOCFG16_CSCBV_OFFSET 20 ++#define LCDC_HEOCFG16_CSCBV (0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET) ++#define LCDC_HEOCFG16_CSCVOFF (0x1 << 30) ++ ++#define ATMEL_LCDC_HCRCHER 0x0340 ++#define LCDC_HCRCHER_CHEN (0x1 << 0) ++#define LCDC_HCRCHER_UPDATEEN (0x1 << 1) ++#define LCDC_HCRCHER_A2QEN (0x1 << 2) ++ ++#define ATMEL_LCDC_HCRCHDR 0x0344 ++#define LCDC_HCRCHDR_CHDIS (0x1 << 0) ++#define LCDC_HCRCHDR_CHRST (0x1 << 8) ++ ++#define ATMEL_LCDC_HCRCHSR 0x0348 ++#define LCDC_HCRCHSR_CHSR (0x1 << 0) ++#define LCDC_HCRCHSR_UPDATESR (0x1 << 1) ++#define LCDC_HCRCHSR_A2QSR (0x1 << 2) ++ ++#define ATMEL_LCDC_HCRIER 0x034C ++#define LCDC_HCRIER_DMA (0x1 << 2) ++#define LCDC_HCRIER_DSCR (0x1 << 3) ++#define LCDC_HCRIER_ADD (0x1 << 4) ++#define LCDC_HCRIER_DONE (0x1 << 5) ++#define LCDC_HCRIER_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_HCRIDR 0x0350 ++#define LCDC_HCRIDR_DMA (0x1 << 2) ++#define LCDC_HCRIDR_DSCR (0x1 << 3) ++#define LCDC_HCRIDR_ADD (0x1 << 4) ++#define LCDC_HCRIDR_DONE (0x1 << 5) ++#define LCDC_HCRIDR_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_HCRIMR 0x0354 ++#define LCDC_HCRIMR_DMA (0x1 << 2) ++#define LCDC_HCRIMR_DSCR (0x1 << 3) ++#define LCDC_HCRIMR_ADD (0x1 << 4) ++#define LCDC_HCRIMR_DONE (0x1 << 5) ++#define LCDC_HCRIMR_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_HCRISR 0x0358 ++#define LCDC_HCRISR_DMA (0x1 << 2) ++#define LCDC_HCRISR_DSCR (0x1 << 3) ++#define LCDC_HCRISR_ADD (0x1 << 4) ++#define LCDC_HCRISR_DONE (0x1 << 5) ++#define LCDC_HCRISR_OVR (0x1 << 6) ++ ++#define ATMEL_LCDC_HCRHEAD 0x035C ++ ++#define ATMEL_LCDC_HCRADDR 0x0360 ++ ++#define ATMEL_LCDC_HCRCTRL 0x0364 ++#define LCDC_HCRCTRL_DFETCH (0x1 << 0) ++#define LCDC_HCRCTRL_LFETCH (0x1 << 1) ++#define LCDC_HCRCTRL_DMAIEN (0x1 << 2) ++#define LCDC_HCRCTRL_DSCRIEN (0x1 << 3) ++#define LCDC_HCRCTRL_ADDIEN (0x1 << 4) ++#define LCDC_HCRCTRL_DONEIEN (0x1 << 5) ++ ++#define ATMEL_LCDC_HCRNEXT 0x0368 ++ ++#define ATMEL_LCDC_HCRCFG0 0x036C ++#define LCDC_HCRCFG0_BLEN_OFFSET 4 ++#define LCDC_HCRCFG0_BLEN (0x3 << LCDC_HCRCFG0_BLEN_OFFSET) ++#define LCDC_HCRCFG0_BLEN_AHB_SINGLE (0x0 << 4) ++#define LCDC_HCRCFG0_BLEN_AHB_INCR4 (0x1 << 4) ++#define LCDC_HCRCFG0_BLEN_AHB_INCR8 (0x2 << 4) ++#define LCDC_HCRCFG0_BLEN_AHB_INCR16 (0x3 << 4) ++#define LCDC_HCRCFG0_DLBO (0x1 << 8) ++ ++#define ATMEL_LCDC_HCRCFG1 0x0370 ++#define LCDC_HCRCFG1_CLUTEN (0x1 << 0) ++#define LCDC_HCRCFG1_RGBMODE_OFFSET 4 ++#define LCDC_HCRCFG1_RGBMODE (0xf << LCDC_HCRCFG1_RGBMODE_OFFSET) ++#define LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) ++#define LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) ++#define LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) ++#define LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) ++#define LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) ++#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) ++#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) ++#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) ++#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) ++#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) ++#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) ++#define LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) ++#define LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) ++#define LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) ++#define LCDC_HCRCFG1_CLUTMODE_OFFSET 8 ++#define LCDC_HCRCFG1_CLUTMODE (0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET) ++#define LCDC_HCRCFG1_CLUTMODE_1BPP (0x0 << 8) ++#define LCDC_HCRCFG1_CLUTMODE_2BPP (0x1 << 8) ++#define LCDC_HCRCFG1_CLUTMODE_4BPP (0x2 << 8) ++#define LCDC_HCRCFG1_CLUTMODE_8BPP (0x3 << 8) ++ ++#define ATMEL_LCDC_HCRCFG2 0x0374 ++#define LCDC_HCRCFG2_XOFFSET_OFFSET 0 ++#define LCDC_HCRCFG2_XOFFSET (0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET) ++#define LCDC_HCRCFG2_YOFFSET_OFFSET 16 ++#define LCDC_HCRCFG2_YOFFSET (0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET) ++ ++#define ATMEL_LCDC_HCRCFG3 0x0378 ++#define LCDC_HCRCFG3_XSIZE_OFFSET 0 ++#define LCDC_HCRCFG3_XSIZE (0x7f << LCDC_HCRCFG3_XSIZE_OFFSET) ++#define LCDC_HCRCFG3_YSIZE_OFFSET 16 ++#define LCDC_HCRCFG3_YSIZE (0x7f << LCDC_HCRCFG3_YSIZE_OFFSET) ++ ++#define ATMEL_LCDC_HCRCFG4 0x037C ++ ++#define ATMEL_LCDC_HCRCFG6 0x0384 ++#define LCDC_HCRCFG6_BDEF_OFFSET 0 ++#define LCDC_HCRCFG6_BDEF (0xff << LCDC_HCRCFG6_BDEF_OFFSET) ++#define LCDC_HCRCFG6_GDEF_OFFSET 8 ++#define LCDC_HCRCFG6_GDEF (0xff << LCDC_HCRCFG6_GDEF_OFFSET) ++#define LCDC_HCRCFG6_RDEF_OFFSET 16 ++#define LCDC_HCRCFG6_RDEF (0xff << LCDC_HCRCFG6_RDEF_OFFSET) ++ ++#define ATMEL_LCDC_HCRCFG7 0x0388 ++#define LCDC_HCRCFG7_BKEY_OFFSET 0 ++#define LCDC_HCRCFG7_BKEY (0xff << LCDC_HCRCFG7_BKEY_OFFSET) ++#define LCDC_HCRCFG7_GKEY_OFFSET 8 ++#define LCDC_HCRCFG7_GKEY (0xff << LCDC_HCRCFG7_GKEY_OFFSET) ++#define LCDC_HCRCFG7_RKEY_OFFSET 16 ++#define LCDC_HCRCFG7_RKEY (0xff << LCDC_HCRCFG7_RKEY_OFFSET) ++ ++#define ATMEL_LCDC_HCRCFG8 0x038C ++#define LCDC_HCRCFG8_BMASK_OFFSET 0 ++#define LCDC_HCRCFG8_BMASK (0xff << LCDC_HCRCFG8_BMASK_OFFSET) ++#define LCDC_HCRCFG8_GMASK_OFFSET 8 ++#define LCDC_HCRCFG8_GMASK (0xff << LCDC_HCRCFG8_GMASK_OFFSET) ++#define LCDC_HCRCFG8_RMASK_OFFSET 16 ++#define LCDC_HCRCFG8_RMASK (0xff << LCDC_HCRCFG8_RMASK_OFFSET) ++ ++#define ATMEL_LCDC_HCRCFG9 0x0390 ++#define LCDC_HCRCFG9_CRKEY (0x1 << 0) ++#define LCDC_HCRCFG9_INV (0x1 << 1) ++#define LCDC_HCRCFG9_ITER2BL (0x1 << 2) ++#define LCDC_HCRCFG9_ITER (0x1 << 3) ++#define LCDC_HCRCFG9_REVALPHA (0x1 << 4) ++#define LCDC_HCRCFG9_GAEN (0x1 << 5) ++#define LCDC_HCRCFG9_LAEN (0x1 << 6) ++#define LCDC_HCRCFG9_OVR (0x1 << 7) ++#define LCDC_HCRCFG9_DMA (0x1 << 8) ++#define LCDC_HCRCFG9_REP (0x1 << 9) ++#define LCDC_HCRCFG9_DSTKEY (0x1 << 10) ++#define LCDC_HCRCFG9_GA_OFFSET 16 ++#define LCDC_HCRCFG9_GA_Msk (0xff << LCDC_HCRCFG9_GA_OFFSET) ++ ++#define ATMEL_LCDC_BASECLUT 0x400 ++#define LCDC_BASECLUT_BCLUT_OFFSET 0 ++#define LCDC_BASECLUT_BCLUT (0xff << LCDC_BASECLUT_BCLUT_OFFSET) ++#define LCDC_BASECLUT_GCLUT_OFFSET 8 ++#define LCDC_BASECLUT_GCLUT (0xff << LCDC_BASECLUT_GCLUT_OFFSET) ++#define LCDC_BASECLUT_RCLUT_OFFSET 16 ++#define LCDC_BASECLUT_RCLUT (0xff << LCDC_BASECLUT_RCLUT_OFFSET) ++ ++#define ATMEL_LCDC_OVR1CLUT 0x800 ++#define LCDC_OVR1CLUT_BCLUT_OFFSET 0 ++#define LCDC_OVR1CLUT_BCLUT (0xff << LCDC_OVR1CLUT_BCLUT_OFFSET) ++#define LCDC_OVR1CLUT_GCLUT_OFFSET 8 ++#define LCDC_OVR1CLUT_GCLUT (0xff << LCDC_OVR1CLUT_GCLUT_OFFSET) ++#define LCDC_OVR1CLUT_RCLUT_OFFSET 16 ++#define LCDC_OVR1CLUT_RCLUT (0xff << LCDC_OVR1CLUT_RCLUT_OFFSET) ++#define LCDC_OVR1CLUT_ACLUT_OFFSET 24 ++#define LCDC_OVR1CLUT_ACLUT (0xff << LCDC_OVR1CLUT_ACLUT_OFFSET) ++ ++#define ATMEL_LCDC_HEOCLUT 0x1000 ++#define LCDC_HEOCLUT_BCLUT_OFFSET 0 ++#define LCDC_HEOCLUT_BCLUT (0xff << LCDC_HEOCLUT_BCLUT_OFFSET) ++#define LCDC_HEOCLUT_GCLUT_OFFSET 8 ++#define LCDC_HEOCLUT_GCLUT (0xff << LCDC_HEOCLUT_GCLUT_OFFSET) ++#define LCDC_HEOCLUT_RCLUT_OFFSET 16 ++#define LCDC_HEOCLUT_RCLUT (0xff << LCDC_HEOCLUT_RCLUT_OFFSET) ++#define LCDC_HEOCLUT_ACLUT_OFFSET 24 ++#define LCDC_HEOCLUT_ACLUT (0xff << LCDC_HEOCLUT_ACLUT_OFFSET) ++ ++#define ATMEL_LCDC_HCRCLUT 0x1400 ++#define LCDC_HCRCLUT_BCLUT_OFFSET 0 ++#define LCDC_HCRCLUT_BCLUT (0xff << LCDC_HCRCLUT_BCLUT_OFFSET) ++#define LCDC_HCRCLUT_GCLUT_OFFSET 8 ++#define LCDC_HCRCLUT_GCLUT (0xff << LCDC_HCRCLUT_GCLUT_OFFSET) ++#define LCDC_HCRCLUT_RCLUT_OFFSET 16 ++#define LCDC_HCRCLUT_RCLUT (0xff << LCDC_HCRCLUT_RCLUT_OFFSET) ++#define LCDC_HCRCLUT_ACLUT_OFFSET 24 ++#define LCDC_HCRCLUT_ACLUT (0xff << LCDC_HCRCLUT_ACLUT_OFFSET) ++ ++/* Base layer CLUT */ ++#define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4)) ++ ++ ++#endif /* __ATMEL_HLCDC4_H__ */ +diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c +index d99505b..c35f5c7 100644 +--- a/drivers/video/atmel_lcdfb.c ++++ b/drivers/video/atmel_lcdfb.c +@@ -1,7 +1,7 @@ + /* + * Driver for AT91/AT32 LCD Controller + * +- * Copyright (C) 2007 Atmel Corporation ++ * Copyright (C) 2007-2010 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for +@@ -25,6 +25,7 @@ + #include + + #include