From: Carol Eidt <carol.eidt@microsoft.com>
Date: Thu, 14 Jun 2018 19:24:16 +0000 (-0700)
Subject: ARM: increase small reg set for jitStressRegs=3 (dotnet/coreclr#18462)
X-Git-Tag: submit/tizen/20210909.063632~11030^2~4596
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b5f5c2a589a7f02cd5a8bfc5a3a11ec38cd5d725;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

ARM: increase small reg set for jitStressRegs=3 (dotnet/coreclr#18462)

We may need two registers (base + offset) to set up the target register for a virtual call.

Fix dotnet/coreclr#18228

Commit migrated from https://github.com/dotnet/coreclr/commit/38fc21129e23f6d5ff37755452f4b95f07de6c56
---

diff --git a/src/coreclr/src/jit/lsra.h b/src/coreclr/src/jit/lsra.h
index cc8f1ca..3b54c7b 100644
--- a/src/coreclr/src/jit/lsra.h
+++ b/src/coreclr/src/jit/lsra.h
@@ -787,7 +787,9 @@ private:
 #endif // !UNIX_AMD64_ABI
     static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
 #elif defined(_TARGET_ARM_)
-    static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4);
+    // On ARM, we may need two registers to set up the target register for a virtual call, so we need
+    // to have at least the maximum number of arg registers, plus 2.
+    static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
     static const regMaskTP LsraLimitSmallFPSet  = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
 #elif defined(_TARGET_ARM64_)
     static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);