From: Ville Syrjälä Date: Thu, 24 Jan 2013 13:29:41 +0000 (+0200) Subject: drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset X-Git-Tag: upstream/snapshot3+hdmi~5652^2~36^2~45 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b41fbda15184e0b4c4e0c0c21737e4abcbaff955;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4f4b989..e7b13c2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2707,7 +2707,7 @@ #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) -#define VLV_DPFLIPSTAT 0x70028 +#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) #define PIPEB_LINE_COMPARE_INT_EN (1<<29) #define PIPEB_HLINE_INT_EN (1<<28) #define PIPEB_VBLANK_INT_EN (1<<27) @@ -2721,7 +2721,7 @@ #define SPRITEA_FLIPDONE_INT_EN (1<<17) #define PLANEA_FLIPDONE_INT_EN (1<<16) -#define DPINVGTT 0x7002c /* VLV only */ +#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */ #define CURSORB_INVALID_GTT_INT_EN (1<<23) #define CURSORA_INVALID_GTT_INT_EN (1<<22) #define SPRITED_INVALID_GTT_INT_EN (1<<21)