From: Uros Bizjak <ubizjak@gmail.com>
Date: Fri, 16 Nov 2018 16:42:16 +0000 (+0100)
Subject: re PR target/88051 (internal compiler error: in add_clobbers, at config/i386/sync... 
X-Git-Tag: upstream/12.2.0~28011
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b41835733bc337580a0de6b8ba5de4b00d391fc6;p=platform%2Fupstream%2Fgcc.git

re PR target/88051 (internal compiler error: in add_clobbers, at config/i386/sync.md:1762)

	PR target/88051
	* config/i386/i386.md (floatunsdidf2): Allow only 64bit AVX512F targets.
	* config/i386/sse.md (UNSPEC_MOVDI_TO_SSE): New UNSPEC.
	(movdi_to_sse): Rewrite using UNSPEC_MOVDI_TO_SSE unspec.

From-SVN: r266218
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a6881d2..2362e70 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2018-11-16  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/88051
+	* config/i386/i386.md (floatunsdidf2): Allow only 64bit AVX512F targets.
+	* config/i386/sse.md (UNSPEC_MOVDI_TO_SSE): New UNSPEC.
+	(movdi_to_sse): Rewrite using UNSPEC_MOVDI_TO_SSE unspec.
+
 2018-11-16  Jakub Jelinek  <jakub@redhat.com>
 
 	PR middle-end/88032
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9c359c0..1a3a179 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5194,7 +5194,8 @@
   [(set (match_operand:DF 0 "register_operand")
 	(unsigned_float:DF
 	  (match_operand:DI 1 "nonimmediate_operand")))]
-  "(TARGET_KEEPS_VECTOR_ALIGNED_STACK || TARGET_AVX512F)
+  "((TARGET_64BIT && TARGET_AVX512F)
+    || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
    && TARGET_SSE2 && TARGET_SSE_MATH"
 {
   if (!TARGET_64BIT)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5020c05..18685de 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -21,6 +21,9 @@
   ;; SSE
   UNSPEC_MOVNT
 
+  ;; SSE2
+  UNSPEC_MOVDI_TO_SSE
+
   ;; SSE3
   UNSPEC_LDDQU
 
@@ -1235,10 +1238,10 @@
 ;; from there.
 
 (define_insn_and_split "movdi_to_sse"
-  [(parallel
-    [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
-	  (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
-     (clobber (match_scratch:V4SI 2 "=&x,X"))])]
+  [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
+	(unspec:V4SI [(match_operand:DI 1 "nonimmediate_operand" "r,m")]
+		     UNSPEC_MOVDI_TO_SSE))
+     (clobber (match_scratch:V4SI 2 "=&x,X"))]
   "!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC"
   "#"
   "&& reload_completed"