From: Eric Anholt Date: Mon, 23 Mar 2015 23:34:24 +0000 (-0700) Subject: vc4: Write the alignment of level width consistently in validation. X-Git-Tag: upstream/17.1.0~19841 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b3ea377f8629ada57c67632a89f0d2e9d2faf23c;p=platform%2Fupstream%2Fmesa.git vc4: Write the alignment of level width consistently in validation. 16 / cpp happens to be the same as utile_w on the only raster format supported (4 bytes per pixel), but simulator/hw source code generally talks in terms of utiles. --- diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c b/src/gallium/drivers/vc4/kernel/vc4_validate.c index 0691a8d..568b625 100644 --- a/src/gallium/drivers/vc4/kernel/vc4_validate.c +++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c @@ -164,7 +164,7 @@ check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, switch (tiling_format) { case VC4_TILING_FORMAT_LINEAR: - aligned_width = roundup(width, 16 / cpp); + aligned_width = roundup(width, utile_w); aligned_height = height; break; case VC4_TILING_FORMAT_T: @@ -951,7 +951,7 @@ reloc_tex(struct vc4_exec_info *exec, aligned_height = roundup(level_height, utile_h); break; default: - aligned_width = roundup(level_width, 16 / cpp); + aligned_width = roundup(level_width, utile_w); aligned_height = level_height; break; }