From: Zhigang Gong <zhigang.gong@intel.com>
Date: Sun, 4 May 2014 00:59:41 +0000 (+0800)
Subject: GBE: fixed a regression at "Long" div/rem.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b3042047af9bf3a78783fcca39a0b005c7d9090a;p=contrib%2Fbeignet.git

GBE: fixed a regression at "Long" div/rem.

If the GEN_PREDICATE_ALIGN1_ANY8H/ANY16H or ALL8H/ALL16H
are used, we must make sure those inactive lanes are initialized
correctly. For "ANY" condition, all the inactive lanes need to
be clear to zero. For "ALL" condition, all the inactive lanes
need to be set to 1s. Otherwise, it may cause infinite loop.

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
---

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 62b58bd..369c1bf 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -1525,9 +1525,16 @@ namespace gbe
       p->SHR(g, g, one);
       // condition: m < 64
       p->ADD(m, m, one);
+
       p->push();
-      p->curr.predicate = GEN_PREDICATE_NONE;
       p->curr.noMask = 1;
+      p->curr.execWidth = 1;
+      p->MOV(flagReg, zero);
+      p->pop();
+
+      p->push();
+      p->curr.predicate = GEN_PREDICATE_NONE;
+      p->curr.noMask = 0;
       p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr());
       p->CMP(GEN_CONDITIONAL_L, m, GenRegister::immud(64));