From: Jonathan Marek <jonathan@marek.ca>
Date: Thu, 17 Sep 2020 13:38:57 +0000 (-0400)
Subject: turnip: move A6XX_RB_ALPHA_CONTROL write to init_hw
X-Git-Tag: upstream/21.0.0~5041
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b2fa2d99ae25a3357d1362a4545cecf3e18fff1d;p=platform%2Fupstream%2Fmesa.git

turnip: move A6XX_RB_ALPHA_CONTROL write to init_hw

Its always 0.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5641>
---

diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index 1e9fe23..a645831 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -761,7 +761,6 @@ r3d_setup(struct tu_cmd_buffer *cmd,
 
    tu_cs_emit_regs(cs, A6XX_SP_BLEND_CNTL());
    tu_cs_emit_regs(cs, A6XX_RB_BLEND_CNTL(.sample_mask = 0xffff));
-   tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL());
 
    tu_cs_emit_regs(cs, A6XX_RB_DEPTH_PLANE_CNTL());
    tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL());
@@ -1885,7 +1884,6 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
 
    tu_cs_emit_regs(cs, A6XX_SP_BLEND_CNTL());
    tu_cs_emit_regs(cs, A6XX_RB_BLEND_CNTL(.independent_blend = 1, .sample_mask = 0xffff));
-   tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL());
    for (uint32_t i = 0; i < mrt_count; i++) {
       tu_cs_emit_regs(cs, A6XX_RB_MRT_CONTROL(i,
             .component_enable = COND(clear_rts & (1 << i), 0xf)));
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index a074bad..1ded677 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -798,6 +798,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
 
+   tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL());
+
    /* we don't use this yet.. probably best to disable.. */
    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index f2dbe97..fe87c27 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2372,10 +2372,8 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
          ? ds_info : &dummy_ds_info;
 
    struct tu_cs cs;
-   pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 6);
+   pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 4);
 
-   /* move to hw ctx init? */
-   tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
    tu6_emit_depth_control(&cs, ds_info_depth,
                           builder->create_info->pRasterizationState);
    tu6_emit_stencil_control(&cs, ds_info);