From: Andrew Burgess <andrew.burgess@embecosm.com>
Date: Tue, 6 Mar 2018 13:20:14 +0000 (+0000)
Subject: gdb/riscv: Fix type when reading register from regcache
X-Git-Tag: binutils-2_31~1123
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b2970c238e24e6239760b72c924ee7dd2df9ccd1;p=platform%2Fupstream%2Fbinutils.git

gdb/riscv: Fix type when reading register from regcache

Should use a ULONGEST when reading from the regcache.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_return_value): Change type to ULONGEST for
	reading values from registers.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 88b1172..ff6eb55 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,5 +1,10 @@
 2018-03-06  Andrew Burgess  <andrew.burgess@embecosm.com>
 
+	* riscv-tdep.c (riscv_return_value): Change type to ULONGEST for
+	reading values from registers.
+
+2018-03-06  Andrew Burgess  <andrew.burgess@embecosm.com>
+
 	* riscv-tdep.c (riscv_push_dummy_call): Use core_addr_to_string_nz
 	where appropriate.
 
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 797ca72..3e1ad99 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -2318,7 +2318,7 @@ riscv_return_value (struct gdbarch  *gdbarch,
 	    /* Return value by reference will have its address in A0.  */
 	  case riscv_arg_info::location::by_ref:
 	    {
-	      CORE_ADDR addr;
+	      ULONGEST addr;
 
 	      regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
 					     &addr);