From: Dnyaneshwar Bhadane Date: Tue, 1 Aug 2023 13:53:34 +0000 (+0530) Subject: drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines X-Git-Tag: v6.6.17~3937^2~13^2~17 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b1c5256092b955e656bd70804cd7e001752a79b8;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines Follow consistent naming convention. Replace KBL with KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with IS_KABYLAKE () && IS_GRAPHICS_STEP(). v2: - s/KBL/kbl in the subject prefix(Anusha) v3: - Unrolled wrapper IS_KBL_GRAPHICS_STEP. - Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani) v4: - Removed unused macro. Cc: Tvrtko Ursulin Cc: Jani Nikula Cc: Anusha Srivatsa Signed-off-by: Dnyaneshwar Bhadane Reviewed-by: Anusha Srivatsa Acked-by: Jani Nikula Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-5-dnyaneshwar.bhadane@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index e85eab2..39eab9e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) encoder->get_buf_trans = icl_get_mg_buf_trans; } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { encoder->get_buf_trans = bxt_get_buf_trans; - } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) { + } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KABYLAKE_ULX(i915)) { encoder->get_buf_trans = kbl_y_get_buf_trans; - } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) { + } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KABYLAKE_ULT(i915)) { encoder->get_buf_trans = kbl_u_get_buf_trans; } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { encoder->get_buf_trans = kbl_get_buf_trans; diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 8a3cbb0..a4ff55a 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) vf_flush_wa = true; /* WaForGAMHang:kbl */ - if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0)) + if (IS_KABYLAKE(rq->i915) && IS_GRAPHICS_STEP(rq->i915, 0, STEP_C0)) dc_flush_wa = true; } diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b0b7d44..a8ba843 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -600,7 +600,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, gen9_ctx_workarounds_init(engine, wal); /* WaToEnableHwFixForPushConstHWBug:kbl */ - if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) + if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); @@ -1204,7 +1204,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) gen9_gt_workarounds_init(gt, wal); /* WaDisableDynamicCreditSharing:kbl */ - if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) + if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); @@ -2945,7 +2945,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) struct drm_i915_private *i915 = engine->i915; /* WaKBLVECSSemaphoreWaitPoll:kbl */ - if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { + if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { wa_write(wal, RING_SEMA_WAIT_POLL(engine->mmio_base), 1); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ff853c4b..3cd41f2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -612,9 +612,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) #define IS_SKYLAKE_ULX(i915) \ IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) -#define IS_KBL_ULT(i915) \ +#define IS_KABYLAKE_ULT(i915) \ IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) -#define IS_KBL_ULX(i915) \ +#define IS_KABYLAKE_ULX(i915) \ IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) #define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ INTEL_INFO(i915)->gt == 2) @@ -622,9 +622,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, INTEL_INFO(i915)->gt == 3) #define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ INTEL_INFO(i915)->gt == 4) -#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \ +#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ INTEL_INFO(i915)->gt == 2) -#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \ +#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \ INTEL_INFO(i915)->gt == 3) #define IS_CFL_ULT(i915) \ IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) @@ -649,10 +649,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) -#define IS_KBL_GRAPHICS_STEP(i915, since, until) \ - (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) -#define IS_KBL_DISPLAY_STEP(i915, since, until) \ - (IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until)) #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \ (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index d9600cd..81a4d32 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -456,12 +456,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915) intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); /* WaDisableSDEUnitClockGating:kbl */ - if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0)) + if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* WaDisableGamClockGating:kbl */ - if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0)) + if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);