From: Eric Anholt <eric@anholt.net>
Date: Tue, 21 Nov 2017 23:00:36 +0000 (-0800)
Subject: broadcom/vc5: Fix UIF surface size setup for ARB_fbo's mismatched sizes.
X-Git-Tag: upstream/18.1.0~3849
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b18840ac6e0b6cb4d8a7b7b6a5c504561e3a8696;p=platform%2Fupstream%2Fmesa.git

broadcom/vc5: Fix UIF surface size setup for ARB_fbo's mismatched sizes.

The HW was computing an implicit height for the surface based on the image
size, but that may be smaller than the surface with ARB_fbo mismatched
sizes.  In that case, we need to tell it about the pad, either with the
little 4-bit field in the RT config, or the extended field in
CLEAR_COLORS_PART3.

Fixes piglit arb_framebuffer_object-mixed-buffer-sizes.
---

diff --git a/src/gallium/drivers/vc5/vc5_rcl.c b/src/gallium/drivers/vc5/vc5_rcl.c
index 1fa00b2..f27f7b3 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -285,15 +285,35 @@ vc5_emit_rcl(struct vc5_job *job)
                 if (!psurf)
                         continue;
                 struct vc5_surface *surf = vc5_surface(psurf);
+                struct vc5_resource *rsc = vc5_resource(psurf->texture);
+
+                uint32_t config_pad = 0;
+                uint32_t clear_pad = 0;
+
+                /* XXX: Set the pad for raster. */
+                if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
+                    surf->tiling == VC5_TILING_UIF_XOR) {
+                        int uif_block_height = vc5_utile_height(rsc->cpp) * 2;
+                        uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
+                                                           uif_block_height);
+                        if (surf->padded_height_of_output_image_in_uif_blocks -
+                            implicit_padded_height < 15) {
+                                config_pad = (surf->padded_height_of_output_image_in_uif_blocks -
+                                              implicit_padded_height);
+                        } else {
+                                config_pad = 15;
+                                clear_pad = surf->padded_height_of_output_image_in_uif_blocks;
+                        }
+                }
 
                 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
-                        struct vc5_resource *rsc = vc5_resource(psurf->texture);
                         rt.address = cl_address(rsc->bo, surf->offset);
                         rt.internal_type = surf->internal_type;
                         rt.output_image_format = surf->format;
                         rt.memory_format = surf->tiling;
                         rt.internal_bpp = surf->internal_bpp;
                         rt.render_target_number = i;
+                        rt.pad = config_pad;
 
                         if (job->resolve & PIPE_CLEAR_COLOR0 << i)
                                 rsc->writes++;
@@ -319,9 +339,10 @@ vc5_emit_rcl(struct vc5_job *job)
                         };
                 }
 
-                if (surf->internal_bpp >= INTERNAL_BPP_128) {
+                if (surf->internal_bpp >= INTERNAL_BPP_128 || clear_pad) {
                         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
                                 clear) {
+                                clear.uif_padded_height_in_uif_blocks = clear_pad;
                                 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
                                 clear.render_target_number = i;
                         };