From: Hal Finkel <hfinkel@anl.gov>
Date: Fri, 15 Mar 2013 13:21:21 +0000 (+0000)
Subject: Protect PPC Altivec patterns with a predicate
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b0fac42987600989a477a1e09e29ee10ca4ed5b7;p=platform%2Fupstream%2Fllvm.git

Protect PPC Altivec patterns with a predicate

In preparation for the addition of other SIMD ISA extensions (such as QPX) we
need to make sure that all Altivec patterns are properly predicated on having
Altivec support.

No functionality change intended (one test case needed to be updated b/c it
assumed that Altivec intrinsics would be supported without enabling Altivec
support).

llvm-svn: 177152
---

diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 0cf28ae..0ed7ff2 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -182,6 +182,9 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
 //===----------------------------------------------------------------------===//
 // Instruction Definitions.
 
+def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">;
+let Predicates = [HasAltivec] in {
+
 def DSS      : DSS_Form<822, (outs),
                         (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
                         "dss $STRM", LdStLoad /*FIXME*/, []>;
@@ -733,3 +736,6 @@ def : Pat<(v4f32 (ftrunc (v4f32 VRRC:$vA))),
           (VRFIZ VRRC:$vA)>;
 def : Pat<(v4f32 (fnearbyint (v4f32 VRRC:$vA))),
           (VRFIN VRRC:$vA)>;
+
+} // end HasAltivec
+
diff --git a/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
index 82ef2b8..b6feb5a 100644
--- a/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
+++ b/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc64 | grep dst | count 4
+; RUN: llc < %s -march=ppc64 -mattr=+altivec | grep dst | count 4
 
 define hidden void @_Z4borkPc(i8* %image) {
 entry: