From: Fabio Estevam Date: Fri, 3 May 2013 04:37:11 +0000 (+0000) Subject: mxs: spl_mem_init: Remove erroneous DDR setting X-Git-Tag: v2013.07-rc1~85^2~44 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b0d4bf9f0c061945e5b87150fc364e8794162a10;p=platform%2Fkernel%2Fu-boot.git mxs: spl_mem_init: Remove erroneous DDR setting On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam --- diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 300da0a..df25535 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -279,10 +279,6 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); - - /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ - while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) - ; } #endif