From: Max Filippov Date: Tue, 22 Sep 2015 11:32:03 +0000 (+0300) Subject: spi: xtensa-xtfpga: fix register endianness X-Git-Tag: v4.9.8~3505^2^3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=b0b4855099e301c8603ea37da9a0103a96c2e0b1;p=platform%2Fkernel%2Flinux-rpi3.git spi: xtensa-xtfpga: fix register endianness XTFPGA SPI controller has native endian registers. Fix register acessors so that they work in big-endian configurations. Signed-off-by: Max Filippov Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- diff --git a/drivers/spi/spi-xtensa-xtfpga.c b/drivers/spi/spi-xtensa-xtfpga.c index 2e32ea2..be6155c 100644 --- a/drivers/spi/spi-xtensa-xtfpga.c +++ b/drivers/spi/spi-xtensa-xtfpga.c @@ -34,13 +34,13 @@ struct xtfpga_spi { static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi, unsigned addr, u32 val) { - iowrite32(val, spi->regs + addr); + __raw_writel(val, spi->regs + addr); } static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi, unsigned addr) { - return ioread32(spi->regs + addr); + return __raw_readl(spi->regs + addr); } static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)