From: Guo Ren <guoren@linux.alibaba.com>
Date: Fri, 24 Sep 2021 07:33:38 +0000 (+0800)
Subject: csky: Fixup regs.sr broken in ptrace
X-Git-Tag: accepted/tizen/unified/20230118.172025~6180^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=af89ebaa64de726ca0a39bbb0bf0c81a1f43ad50;p=platform%2Fkernel%2Flinux-rpi.git

csky: Fixup regs.sr broken in ptrace

gpr_get() return the entire pt_regs (include sr) to userspace, if we
don't restore the C bit in gpr_set, it may break the ALU result in
that context. So the C flag bit is part of gpr context, that's why
riscv totally remove the C bit in the ISA. That makes sr reg clear
from userspace to supervisor privilege.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: stable@vger.kernel.org
---

diff --git a/arch/csky/kernel/ptrace.c b/arch/csky/kernel/ptrace.c
index 0105ac8..1a5f54e 100644
--- a/arch/csky/kernel/ptrace.c
+++ b/arch/csky/kernel/ptrace.c
@@ -99,7 +99,8 @@ static int gpr_set(struct task_struct *target,
 	if (ret)
 		return ret;
 
-	regs.sr = task_pt_regs(target)->sr;
+	/* BIT(0) of regs.sr is Condition Code/Carry bit */
+	regs.sr = (regs.sr & BIT(0)) | (task_pt_regs(target)->sr & ~BIT(0));
 #ifdef CONFIG_CPU_HAS_HILO
 	regs.dcsr = task_pt_regs(target)->dcsr;
 #endif