From: Chia-I Wu <olvaffe@gmail.com>
Date: Wed, 8 Feb 2023 23:14:55 +0000 (-0800)
Subject: freedreno: avoid conditional ib in fd6_emit_tile
X-Git-Tag: upstream/23.3.3~13347
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=af7bcc0cdc55e4aa531c999092324c63515658f1;p=platform%2Fupstream%2Fmesa.git

freedreno: avoid conditional ib in fd6_emit_tile

CP_REG_TEST (or any command that reads registers) is slow on a618
(gen1).  Since SQE can early return, we don't necessarily need
emit_conditional_ib in fd6_emit_tile.

We still CP_REG_TEST twice for load and store when there is no clear.
Not sure if we can simply drop emit_conditional_ib instead?

glmark2 score goes from 943 to 1067.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21208>
---

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 38d3f83..22dbb0d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -1439,11 +1439,7 @@ prepare_tile_fini_ib(struct fd_batch *batch) assert_dt
 static void
 fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
 {
-   if (!use_hw_binning(batch)) {
-      fd6_emit_ib(batch->gmem, batch->draw);
-   } else {
-      emit_conditional_ib(batch, tile, batch->draw);
-   }
+   fd6_emit_ib(batch->gmem, batch->draw);
 
    if (batch->tile_epilogue)
       fd6_emit_ib(batch->gmem, batch->tile_epilogue);