From: Jakub Jelinek Date: Sun, 22 May 2016 10:28:06 +0000 (+0200) Subject: sse.md (vec_set_lo_, [...]): Add && condition. X-Git-Tag: upstream/12.2.0~46918 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=af120161421cdc935ff98a0e5038775f22a1ca90;p=platform%2Fupstream%2Fgcc.git sse.md (vec_set_lo_, [...]): Add && condition. * config/i386/sse.md (vec_set_lo_, vec_set_hi_): Add && condition. For !TARGET_AVX512DQ, emit 32x4 instruction instead of 64x2. * gcc.target/i386/avx512dq-vinsert-1.c: New test. * gcc.target/i386/avx512vl-vinsert-1.c: New test. From-SVN: r236569 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 809d9d7..3702823 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2016-05-22 Jakub Jelinek + * config/i386/sse.md (vec_set_lo_, + vec_set_hi_): Add && + condition. For !TARGET_AVX512DQ, emit 32x4 instruction instead + of 64x2. + * config/i386/sse.md (vec_set_lo_v16hi, vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Add alternative with v constraint instead of x and vinserti32x4 insn. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b13dff8..745b6b6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17818,10 +17818,12 @@ (vec_select: (match_operand:VI8F_256 1 "register_operand" "v") (parallel [(const_int 2) (const_int 3)]))))] - "TARGET_AVX" + "TARGET_AVX && " { - if (TARGET_AVX512VL) + if (TARGET_AVX512DQ) return "vinsert64x2\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"; + else if (TARGET_AVX512VL) + return "vinsert32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"; else return "vinsert\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"; } @@ -17838,10 +17840,12 @@ (match_operand:VI8F_256 1 "register_operand" "v") (parallel [(const_int 0) (const_int 1)])) (match_operand: 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX" + "TARGET_AVX && " { - if (TARGET_AVX512VL) + if (TARGET_AVX512DQ) return "vinsert64x2\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"; + else if (TARGET_AVX512VL) + return "vinsert32x4\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"; else return "vinsert\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2805dc8..9572817 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2016-05-22 Jakub Jelinek + * gcc.target/i386/avx512dq-vinsert-1.c: New test. + * gcc.target/i386/avx512vl-vinsert-1.c: New test. + * gcc.target/i386/avx512vl-vinserti32x4-3.c: New test. * gcc.target/i386/avx512dq-vbroadcast-2.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vinsert-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vinsert-1.c new file mode 100644 index 0000000..5d42f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-vinsert-1.c @@ -0,0 +1,100 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512dq -masm=att" } */ + +typedef int V1 __attribute__((vector_size (32))); +typedef long long V2 __attribute__((vector_size (32))); +typedef float V3 __attribute__((vector_size (32))); +typedef double V4 __attribute__((vector_size (32))); + +void +f1 (V1 x, int y) +{ + register V1 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f2 (V1 x, int y) +{ + register V1 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[6] = y; + asm volatile ("" : "+v" (a)); +} + +void +f3 (V2 x, long long y) +{ + register V2 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[1] = y; + asm volatile ("" : "+v" (a)); +} + +void +f4 (V2 x, long long y) +{ + register V2 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f5 (V3 x, float y) +{ + register V3 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f6 (V3 x, float y) +{ + register V3 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[6] = y; + asm volatile ("" : "+v" (a)); +} + +void +f7 (V4 x, double y) +{ + register V4 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[1] = y; + asm volatile ("" : "+v" (a)); +} + +void +f8 (V4 x, double y) +{ + register V4 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vextracti32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 1 } } */ +/* { dg-final { scan-assembler-times "vextractf32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinserti64x2\[^\n\r]*0x0\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinserti64x2\[^\n\r]*0x1\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinsertf64x2\[^\n\r]*0x0\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vinsertf64x2\[^\n\r]*0x1\[^\n\r]*%ymm16" 1 } } */ +/* { dg-final { scan-assembler-times "vextracti64x2\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 1 } } */ +/* { dg-final { scan-assembler-times "vextractf64x2\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vinsert-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vinsert-1.c new file mode 100644 index 0000000..f12260a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vinsert-1.c @@ -0,0 +1,98 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512dq -masm=att" } */ + +typedef int V1 __attribute__((vector_size (32))); +typedef long long V2 __attribute__((vector_size (32))); +typedef float V3 __attribute__((vector_size (32))); +typedef double V4 __attribute__((vector_size (32))); + +void +f1 (V1 x, int y) +{ + register V1 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f2 (V1 x, int y) +{ + register V1 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[6] = y; + asm volatile ("" : "+v" (a)); +} + +void +f3 (V2 x, long long y) +{ + register V2 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[1] = y; + asm volatile ("" : "+v" (a)); +} + +void +f4 (V2 x, long long y) +{ + register V2 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f5 (V3 x, float y) +{ + register V3 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +void +f6 (V3 x, float y) +{ + register V3 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[6] = y; + asm volatile ("" : "+v" (a)); +} + +void +f7 (V4 x, double y) +{ + register V4 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[1] = y; + asm volatile ("" : "+v" (a)); +} + +void +f8 (V4 x, double y) +{ + register V4 a __asm ("xmm16"); + a = x; + asm volatile ("" : "+v" (a)); + a[3] = y; + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 2 } } */ +/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 2 } } */ +/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 2 } } */ +/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 2 } } */ +/* { dg-final { scan-assembler-times "vextracti32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 2 } } */ +/* { dg-final { scan-assembler-times "vextractf32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 2 } } */ +/* { dg-final { scan-assembler-not "vinserti64x2" } } */ +/* { dg-final { scan-assembler-not "vinsertf64x2" } } */ +/* { dg-final { scan-assembler-not "vextracti64x2" } } */ +/* { dg-final { scan-assembler-not "vextracti64x2" } } */