From: Simon Pilgrim Date: Fri, 27 Apr 2018 13:32:42 +0000 (+0000) Subject: [X86] Replace some system instruction instregex single matches with instrs entry... X-Git-Tag: llvmorg-7.0.0-rc1~7236 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=aef5ca72998b6afbd16de39503c318214f7fc19d;p=platform%2Fupstream%2Fllvm.git [X86] Replace some system instruction instregex single matches with instrs entry. NFCI. llvm-svn: 331034 --- diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index bc20bd8..72044bf 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -513,10 +513,10 @@ def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[BWWriteResGroup14], (instregex "LFENCE", - "MFENCE", - "WAIT", - "XGETBV")>; +def: InstRW<[BWWriteResGroup14], (instrs LFENCE, + MFENCE, + WAIT, + XGETBV)>; def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { let Latency = 2; @@ -604,13 +604,10 @@ def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>; +def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr", - "PUSH64i8", - "STOSB", - "STOSL", - "STOSQ", - "STOSW")>; + "PUSH64i8")>; def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { let Latency = 3; @@ -829,7 +826,7 @@ def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> { let NumMicroOps = 4; let ResourceCycles = [1,3]; } -def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>; +def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { let Latency = 5; @@ -1774,7 +1771,7 @@ def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { let NumMicroOps = 12; let ResourceCycles = [2,1,4,5]; } -def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>; +def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { let Latency = 15; @@ -1895,9 +1892,7 @@ def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort2 let NumMicroOps = 8; let ResourceCycles = [1,1,1,1,1,1,2]; } -def: InstRW<[BWWriteResGroup167], (instregex "INSB", - "INSL", - "INSW")>; +def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; def BWWriteResGroup168 : SchedWriteRes<[BWPort0,BWFPDivider]> { let Latency = 16; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 2c0d8d8..c2ea8b1 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -379,7 +379,7 @@ def HWWriteXLAT : SchedWriteRes<[]> { let Latency = 7; let NumMicroOps = 3; } -def : InstRW<[HWWriteXLAT], (instregex "XLAT")>; +def : InstRW<[HWWriteXLAT], (instrs XLAT)>; // PUSHA. def HWWritePushA : SchedWriteRes<[]> { @@ -1147,13 +1147,10 @@ def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r)>; +def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr", - "PUSH64i8", - "STOSB", - "STOSL", - "STOSQ", - "STOSW")>; + "PUSH64i8")>; def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { let Latency = 7; @@ -1200,10 +1197,10 @@ def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[HWWriteResGroup30], (instregex "LFENCE")>; -def: InstRW<[HWWriteResGroup30], (instregex "MFENCE")>; -def: InstRW<[HWWriteResGroup30], (instrs WAIT)>; -def: InstRW<[HWWriteResGroup30], (instregex "XGETBV")>; +def: InstRW<[HWWriteResGroup30], (instrs LFENCE, + MFENCE, + WAIT, + XGETBV)>; def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> { let Latency = 2; @@ -1813,7 +1810,7 @@ def HWWriteResGroup82 : SchedWriteRes<[HWPort015,HWPort0156]> { let NumMicroOps = 4; let ResourceCycles = [1,3]; } -def: InstRW<[HWWriteResGroup82], (instregex "VZEROUPPER")>; +def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { let Latency = 4; @@ -2264,16 +2261,14 @@ def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort2 let NumMicroOps = 8; let ResourceCycles = [1,1,1,1,1,1,2]; } -def: InstRW<[HWWriteResGroup144], (instregex "INSB", - "INSL", - "INSW")>; +def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; def HWWriteResGroup145 : SchedWriteRes<[HWPort5]> { let Latency = 16; let NumMicroOps = 16; let ResourceCycles = [16]; } -def: InstRW<[HWWriteResGroup145], (instregex "VZEROALL")>; +def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { let Latency = 22; @@ -2287,7 +2282,7 @@ def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01 let NumMicroOps = 15; let ResourceCycles = [2,1,2,4,2,4]; } -def: InstRW<[HWWriteResGroup147], (instregex "XCH_F")>; +def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { let Latency = 18; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 426d8fa..55475f7 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -499,10 +499,10 @@ def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SBWriteResGroup11], (instregex "SCASB", - "SCASL", - "SCASQ", - "SCASW")>; +def: InstRW<[SBWriteResGroup11], (instrs SCASB, + SCASL, + SCASQ, + SCASW)>; def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { let Latency = 2; @@ -801,10 +801,7 @@ def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup40], (instregex "STOSB", - "STOSL", - "STOSQ", - "STOSW")>; +def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { let Latency = 5; @@ -1070,8 +1067,7 @@ def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SBWriteResGroup63], (instregex "LODSB", - "LODSW")>; +def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { let Latency = 7; @@ -1239,10 +1235,10 @@ def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { let NumMicroOps = 5; let ResourceCycles = [2,3]; } -def: InstRW<[SBWriteResGroup83], (instregex "CMPSB", - "CMPSL", - "CMPSQ", - "CMPSW")>; +def: InstRW<[SBWriteResGroup83], (instrs CMPSB, + CMPSL, + CMPSQ, + CMPSW)>; def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { let Latency = 8; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index fb16fa8..bd7c37d 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -627,9 +627,9 @@ def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKLWriteResGroup17], (instregex "LFENCE", - "WAIT", - "XGETBV")>; +def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,SKLPort237]> { let Latency = 2; @@ -714,13 +714,10 @@ def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r)>; +def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr", - "PUSH64i8", - "STOSB", - "STOSL", - "STOSQ", - "STOSW")>; + "PUSH64i8")>; def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { let Latency = 3; @@ -856,7 +853,7 @@ def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SKLWriteResGroup41], (instregex "MFENCE")>; +def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { let Latency = 3; @@ -1004,7 +1001,7 @@ def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> { let NumMicroOps = 4; let ResourceCycles = [1,3]; } -def: InstRW<[SKLWriteResGroup56], (instregex "VZEROUPPER")>; +def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { let Latency = 4; @@ -2235,7 +2232,7 @@ def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { let NumMicroOps = 16; let ResourceCycles = [16]; } -def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>; +def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { let Latency = 17; @@ -2256,7 +2253,7 @@ def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKL let NumMicroOps = 15; let ResourceCycles = [2,1,2,4,2,4]; } -def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>; +def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { let Latency = 18; @@ -2350,9 +2347,7 @@ def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SK let NumMicroOps = 8; let ResourceCycles = [1,1,1,1,1,1,2]; } -def: InstRW<[SKLWriteResGroup192], (instregex "INSB", - "INSL", - "INSW")>; +def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { let Latency = 20; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 509ebf2..b74b8f3 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -1091,9 +1091,9 @@ def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKXWriteResGroup17], (instregex "LFENCE", - "WAIT", - "XGETBV")>; +def: InstRW<[SKXWriteResGroup17], (instrs LFENCE, + WAIT, + XGETBV)>; def SKXWriteResGroup18 : SchedWriteRes<[SKXPort0,SKXPort237]> { let Latency = 2; @@ -1198,13 +1198,10 @@ def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r)>; +def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, + STOSB, STOSL, STOSQ, STOSW)>; def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr", - "PUSH64i8", - "STOSB", - "STOSL", - "STOSQ", - "STOSW")>; + "PUSH64i8")>; def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { let Latency = 2; @@ -1545,7 +1542,7 @@ def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[SKXWriteResGroup43], (instregex "MFENCE")>; +def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>; def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> { let Latency = 3; @@ -1850,7 +1847,7 @@ def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> { let NumMicroOps = 4; let ResourceCycles = [1,3]; } -def: InstRW<[SKXWriteResGroup56], (instregex "VZEROUPPER")>; +def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>; def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> { let Latency = 4; @@ -4423,7 +4420,7 @@ def SKXWriteResGroup200 : SchedWriteRes<[SKXPort0156]> { let NumMicroOps = 16; let ResourceCycles = [16]; } -def: InstRW<[SKXWriteResGroup200], (instregex "VZEROALL")>; +def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>; def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { let Latency = 17; @@ -4444,7 +4441,7 @@ def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKX let NumMicroOps = 15; let ResourceCycles = [2,1,2,4,2,4]; } -def: InstRW<[SKXWriteResGroup202], (instregex "XCH_F")>; +def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>; def SKXWriteResGroup203 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { let Latency = 18; @@ -4578,9 +4575,7 @@ def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SK let NumMicroOps = 8; let ResourceCycles = [1,1,1,1,1,1,2]; } -def: InstRW<[SKXWriteResGroup219], (instregex "INSB", - "INSL", - "INSW")>; +def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>; def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { let Latency = 20; diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index 87b43ee..9dd23b6 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -467,10 +467,9 @@ def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; } -def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, +def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m, MMX_EMMS)>; -def : InstRW<[AtomWrite01_5], (instregex "ST_FP80m", - "MMX_PH(ADD|SUB)S?Wrr")>; +def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { let Latency = 6; diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index ee1a004..9836677 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -325,7 +325,7 @@ def ZnWriteXCHGrm : SchedWriteRes<[ZnAGU, ZnALU]> { } def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>; -def : InstRW<[WriteMicrocoded], (instregex "XLAT")>; +def : InstRW<[WriteMicrocoded], (instrs XLAT)>; // POP16. // r. @@ -732,7 +732,7 @@ def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>; def ZnWriteFXCH : SchedWriteRes<[ZnFPU]>; // FXCHG. -def : InstRW<[ZnWriteFXCH], (instregex "XCH_F")>; +def : InstRW<[ZnWriteFXCH], (instrs XCH_F)>; // FILD. def ZnWriteFILD : SchedWriteRes<[ZnAGU, ZnFPU3]> { @@ -1649,9 +1649,9 @@ def : InstRW<[ZnWriteRSQRTPSYLd], (instregex "VRSQRTPSYm")>; //-- Other instructions --// // VZEROUPPER. -def : InstRW<[WriteMicrocoded], (instregex "VZEROUPPER")>; +def : InstRW<[WriteMicrocoded], (instrs VZEROUPPER)>; // VZEROALL. -def : InstRW<[WriteMicrocoded], (instregex "VZEROALL")>; +def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>; } // SchedModel