From: Thomas Lively Date: Mon, 21 Nov 2022 20:40:14 +0000 (-0800) Subject: [WebAssembly] Update relaxed-simd instruction names X-Git-Tag: upstream/17.0.6~26946 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ae96b5bd2dd0c5f7317724f4977b4ff489afe7f3;p=platform%2Fupstream%2Fllvm.git [WebAssembly] Update relaxed-simd instruction names Including builtin and intrinsic names. These should be the final names for the proposal. https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md Reviewed By: aheejin, maratyszcza Differential Revision: https://reviews.llvm.org/D138249 --- diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def index 723645c..9064ded1 100644 --- a/clang/include/clang/Basic/BuiltinsWebAssembly.def +++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def @@ -162,15 +162,15 @@ TARGET_BUILTIN(__builtin_wasm_trunc_sat_s_zero_f64x2_i32x4, "V4iV2d", "nc", "sim TARGET_BUILTIN(__builtin_wasm_trunc_sat_u_zero_f64x2_i32x4, "V4UiV2d", "nc", "simd128") // Relaxed SIMD builtins (experimental) -TARGET_BUILTIN(__builtin_wasm_fma_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_fms_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_fma_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_fms_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd") TARGET_BUILTIN(__builtin_wasm_relaxed_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "relaxed-simd") @@ -186,8 +186,8 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2, "V4UiV2d", "nc", TARGET_BUILTIN(__builtin_wasm_relaxed_q15mulr_s_i16x8, "V8sV8sV8s", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_dot_i8x16_i7x16_s_i16x8, "V8sV16ScV16Sc", "nc", "relaxed-simd") -TARGET_BUILTIN(__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4, "V4iV16ScV16ScV4i", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8, "V8sV16ScV16Sc", "nc", "relaxed-simd") +TARGET_BUILTIN(__builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4, "V4iV16ScV16ScV4i", "nc", "relaxed-simd") TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f", "nc", "relaxed-simd") #undef BUILTIN diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index e45f118..7ae5508 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -19043,22 +19043,22 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_shuffle); return Builder.CreateCall(Callee, Ops); } - case WebAssembly::BI__builtin_wasm_fma_f32x4: - case WebAssembly::BI__builtin_wasm_fms_f32x4: - case WebAssembly::BI__builtin_wasm_fma_f64x2: - case WebAssembly::BI__builtin_wasm_fms_f64x2: { + case WebAssembly::BI__builtin_wasm_relaxed_madd_f32x4: + case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f32x4: + case WebAssembly::BI__builtin_wasm_relaxed_madd_f64x2: + case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f64x2: { Value *A = EmitScalarExpr(E->getArg(0)); Value *B = EmitScalarExpr(E->getArg(1)); Value *C = EmitScalarExpr(E->getArg(2)); unsigned IntNo; switch (BuiltinID) { - case WebAssembly::BI__builtin_wasm_fma_f32x4: - case WebAssembly::BI__builtin_wasm_fma_f64x2: - IntNo = Intrinsic::wasm_fma; + case WebAssembly::BI__builtin_wasm_relaxed_madd_f32x4: + case WebAssembly::BI__builtin_wasm_relaxed_madd_f64x2: + IntNo = Intrinsic::wasm_relaxed_madd; break; - case WebAssembly::BI__builtin_wasm_fms_f32x4: - case WebAssembly::BI__builtin_wasm_fms_f64x2: - IntNo = Intrinsic::wasm_fms; + case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f32x4: + case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f64x2: + IntNo = Intrinsic::wasm_relaxed_nmadd; break; default: llvm_unreachable("unexpected builtin ID"); @@ -19066,15 +19066,15 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee = CGM.getIntrinsic(IntNo, A->getType()); return Builder.CreateCall(Callee, {A, B, C}); } - case WebAssembly::BI__builtin_wasm_laneselect_i8x16: - case WebAssembly::BI__builtin_wasm_laneselect_i16x8: - case WebAssembly::BI__builtin_wasm_laneselect_i32x4: - case WebAssembly::BI__builtin_wasm_laneselect_i64x2: { + case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i8x16: + case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i16x8: + case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i32x4: + case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i64x2: { Value *A = EmitScalarExpr(E->getArg(0)); Value *B = EmitScalarExpr(E->getArg(1)); Value *C = EmitScalarExpr(E->getArg(2)); Function *Callee = - CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType()); + CGM.getIntrinsic(Intrinsic::wasm_relaxed_laneselect, A->getType()); return Builder.CreateCall(Callee, {A, B, C}); } case WebAssembly::BI__builtin_wasm_relaxed_swizzle_i8x16: { @@ -19136,18 +19136,19 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_relaxed_q15mulr_signed); return Builder.CreateCall(Callee, {LHS, RHS}); } - case WebAssembly::BI__builtin_wasm_dot_i8x16_i7x16_s_i16x8: { + case WebAssembly::BI__builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8: { Value *LHS = EmitScalarExpr(E->getArg(0)); Value *RHS = EmitScalarExpr(E->getArg(1)); - Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_dot_i8x16_i7x16_signed); + Function *Callee = + CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_i8x16_i7x16_signed); return Builder.CreateCall(Callee, {LHS, RHS}); } - case WebAssembly::BI__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4: { + case WebAssembly::BI__builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4: { Value *LHS = EmitScalarExpr(E->getArg(0)); Value *RHS = EmitScalarExpr(E->getArg(1)); Value *Acc = EmitScalarExpr(E->getArg(2)); Function *Callee = - CGM.getIntrinsic(Intrinsic::wasm_dot_i8x16_i7x16_add_signed); + CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_i8x16_i7x16_add_signed); return Builder.CreateCall(Callee, {LHS, RHS, Acc}); } case WebAssembly::BI__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4: { diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c index 9d742e7..5dfb26f 100644 --- a/clang/test/CodeGen/builtins-wasm.c +++ b/clang/test/CodeGen/builtins-wasm.c @@ -661,58 +661,58 @@ i8x16 shuffle(i8x16 x, i8x16 y) { // WEBASSEMBLY-NEXT: ret } -f32x4 fma_f32x4(f32x4 a, f32x4 b, f32x4 c) { - return __builtin_wasm_fma_f32x4(a, b, c); - // WEBASSEMBLY: call <4 x float> @llvm.wasm.fma.v4f32( +f32x4 madd_f32x4(f32x4 a, f32x4 b, f32x4 c) { + return __builtin_wasm_relaxed_madd_f32x4(a, b, c); + // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.madd.v4f32( // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c) // WEBASSEMBLY-NEXT: ret } -f32x4 fms_f32x4(f32x4 a, f32x4 b, f32x4 c) { - return __builtin_wasm_fms_f32x4(a, b, c); - // WEBASSEMBLY: call <4 x float> @llvm.wasm.fms.v4f32( +f32x4 nmadd_f32x4(f32x4 a, f32x4 b, f32x4 c) { + return __builtin_wasm_relaxed_nmadd_f32x4(a, b, c); + // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.nmadd.v4f32( // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c) // WEBASSEMBLY-NEXT: ret } -f64x2 fma_f64x2(f64x2 a, f64x2 b, f64x2 c) { - return __builtin_wasm_fma_f64x2(a, b, c); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.fma.v2f64( +f64x2 madd_f64x2(f64x2 a, f64x2 b, f64x2 c) { + return __builtin_wasm_relaxed_madd_f64x2(a, b, c); + // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.madd.v2f64( // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c) // WEBASSEMBLY-NEXT: ret } -f64x2 fms_f64x2(f64x2 a, f64x2 b, f64x2 c) { - return __builtin_wasm_fms_f64x2(a, b, c); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.fms.v2f64( +f64x2 nmadd_f64x2(f64x2 a, f64x2 b, f64x2 c) { + return __builtin_wasm_relaxed_nmadd_f64x2(a, b, c); + // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.nmadd.v2f64( // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c) // WEBASSEMBLY-NEXT: ret } i8x16 laneselect_i8x16(i8x16 a, i8x16 b, i8x16 c) { - return __builtin_wasm_laneselect_i8x16(a, b, c); - // WEBASSEMBLY: call <16 x i8> @llvm.wasm.laneselect.v16i8( + return __builtin_wasm_relaxed_laneselect_i8x16(a, b, c); + // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8( // WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b, <16 x i8> %c) // WEBASSEMBLY-NEXT: ret } i16x8 laneselect_i16x8(i16x8 a, i16x8 b, i16x8 c) { - return __builtin_wasm_laneselect_i16x8(a, b, c); - // WEBASSEMBLY: call <8 x i16> @llvm.wasm.laneselect.v8i16( + return __builtin_wasm_relaxed_laneselect_i16x8(a, b, c); + // WEBASSEMBLY: call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16( // WEBASSEMBLY-SAME: <8 x i16> %a, <8 x i16> %b, <8 x i16> %c) // WEBASSEMBLY-NEXT: ret } i32x4 laneselect_i32x4(i32x4 a, i32x4 b, i32x4 c) { - return __builtin_wasm_laneselect_i32x4(a, b, c); - // WEBASSEMBLY: call <4 x i32> @llvm.wasm.laneselect.v4i32( + return __builtin_wasm_relaxed_laneselect_i32x4(a, b, c); + // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32( // WEBASSEMBLY-SAME: <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) // WEBASSEMBLY-NEXT: ret } i64x2 laneselect_i64x2(i64x2 a, i64x2 b, i64x2 c) { - return __builtin_wasm_laneselect_i64x2(a, b, c); - // WEBASSEMBLY: call <2 x i64> @llvm.wasm.laneselect.v2i64( + return __builtin_wasm_relaxed_laneselect_i64x2(a, b, c); + // WEBASSEMBLY: call <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64( // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c) // WEBASSEMBLY-NEXT: ret } @@ -782,15 +782,15 @@ i16x8 relaxed_q15mulr_s_i16x8(i16x8 a, i16x8 b) { } i16x8 dot_i8x16_i7x16_s_i16x8(i8x16 a, i8x16 b) { - return __builtin_wasm_dot_i8x16_i7x16_s_i16x8(a, b); - // WEBASSEMBLY: call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed( + return __builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8(a, b); + // WEBASSEMBLY: call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed( // WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b) // WEBASSEMBLY-NEXT: ret } i32x4 dot_i8x16_i7x16_add_s_i32x4(i8x16 a, i8x16 b, i32x4 c) { - return __builtin_wasm_dot_i8x16_i7x16_add_s_i32x4(a, b, c); - // WEBASSEMBLY: call <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed( + return __builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4(a, b, c); + // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed( // WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b, <4 x i32> %c) // WEBASSEMBLY-NEXT: ret } diff --git a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td index b8750ab..aa007d9 100644 --- a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td +++ b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td @@ -245,16 +245,16 @@ def int_wasm_extadd_pairwise_unsigned : // Relaxed SIMD intrinsics (experimental) //===----------------------------------------------------------------------===// -def int_wasm_fma : +def int_wasm_relaxed_madd : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>; -def int_wasm_fms : +def int_wasm_relaxed_nmadd : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>; -def int_wasm_laneselect : +def int_wasm_relaxed_laneselect : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>; @@ -298,12 +298,12 @@ def int_wasm_relaxed_q15mulr_signed: [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem, IntrSpeculatable]>; -def int_wasm_dot_i8x16_i7x16_signed: +def int_wasm_relaxed_dot_i8x16_i7x16_signed: DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem, IntrSpeculatable]>; -def int_wasm_dot_i8x16_i7x16_add_signed: +def int_wasm_relaxed_dot_i8x16_i7x16_add_signed: DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 995fb1d..a6e14fa 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -1380,26 +1380,26 @@ defm "" : RelaxedConvert; //===----------------------------------------------------------------------===// -// Relaxed Fused Multiply- Add and Subtract (FMA/FMS) +// Relaxed (Negative) Multiply-Add (madd/nmadd) //===----------------------------------------------------------------------===// -multiclass SIMDFM simdopA, bits<32> simdopS> { - defm FMA_#vec : +multiclass SIMDMADD simdopA, bits<32> simdopS> { + defm MADD_#vec : RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), - [(set (vec.vt V128:$dst), (int_wasm_fma + [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], - vec.prefix#".relaxed_fma\t$dst, $a, $b, $c", - vec.prefix#".relaxed_fma", simdopA>; - defm FMS_#vec : + vec.prefix#".relaxed_madd\t$dst, $a, $b, $c", + vec.prefix#".relaxed_madd", simdopA>; + defm NMADD_#vec : RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), - [(set (vec.vt V128:$dst), (int_wasm_fms + [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], - vec.prefix#".relaxed_fms\t$dst, $a, $b, $c", - vec.prefix#".relaxed_fms", simdopS>; + vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c", + vec.prefix#".relaxed_nmadd", simdopS>; } -defm "" : SIMDFM; -defm "" : SIMDFM; +defm "" : SIMDMADD; +defm "" : SIMDMADD; //===----------------------------------------------------------------------===// // Laneselect @@ -1408,7 +1408,7 @@ defm "" : SIMDFM; multiclass SIMDLANESELECT op> { defm LANESELECT_#vec : RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins), - [(set (vec.vt V128:$dst), (int_wasm_laneselect + [(set (vec.vt V128:$dst), (int_wasm_relaxed_laneselect (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))], vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c", vec.prefix#".relaxed_laneselect", op>; @@ -1456,18 +1456,18 @@ defm RELAXED_Q15MULR_S : defm RELAXED_DOT : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), - [(set (v8i16 V128:$dst), (int_wasm_dot_i8x16_i7x16_signed + [(set (v8i16 V128:$dst), (int_wasm_relaxed_dot_i8x16_i7x16_signed (v16i8 V128:$lhs), (v16i8 V128:$rhs)))], - "i16x8.dot_i8x16_i7x16_s\t$dst, $lhs, $rhs", - "i16x8.dot_i8x16_i7x16_s", 0x112>; + "i16x8.relaxed_dot_i8x16_i7x16_s\t$dst, $lhs, $rhs", + "i16x8.relaxed_dot_i8x16_i7x16_s", 0x112>; defm RELAXED_DOT_ADD : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc), (outs), (ins), - [(set (v4i32 V128:$dst), (int_wasm_dot_i8x16_i7x16_add_signed + [(set (v4i32 V128:$dst), (int_wasm_relaxed_dot_i8x16_i7x16_add_signed (v16i8 V128:$lhs), (v16i8 V128:$rhs), (v4i32 V128:$acc)))], - "i32x4.dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc", - "i32x4.dot_i8x16_i7x16_add_s", 0x113>; + "i32x4.relaxed_dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc", + "i32x4.relaxed_dot_i8x16_i7x16_add_s", 0x113>; //===----------------------------------------------------------------------===// // Relaxed BFloat16 dot product diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll index 7423ca3..427e682 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll @@ -184,9 +184,9 @@ define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { ; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}} ; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { - %v = call <16 x i8> @llvm.wasm.laneselect.v16i8( + %v = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8( <16 x i8> %a, <16 x i8> %b, <16 x i8> %c ) ret <16 x i8> %v @@ -360,9 +360,9 @@ define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { ; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}} ; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) +declare <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { - %v = call <8 x i16> @llvm.wasm.laneselect.v8i16( + %v = call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16( <8 x i16> %a, <8 x i16> %b, <8 x i16> %c ) ret <8 x i16> %v @@ -382,11 +382,11 @@ define <8 x i16> @relaxed_q15mulr_s_i16x8(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8: ; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}} -; CHECK-NEXT: i16x8.dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>) define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) { - %v = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed( + %v = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed( <16 x i8> %a, <16 x i8> %b ) ret <8 x i16> %v @@ -542,9 +542,9 @@ define <4 x i32> @trunc_sat_u_zero_v4i32_2(<2 x double> %x) { ; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}} ; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { - %v = call <4 x i32> @llvm.wasm.laneselect.v4i32( + %v = call <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32( <4 x i32> %a, <4 x i32> %b, <4 x i32> %c ) ret <4 x i32> %v @@ -594,13 +594,13 @@ define <4 x i32> @relaxed_trunc_u_zero(<2 x double> %x) { ; CHECK-LABEL: dot_i8x16_i7x16_add_s_i32x4: ; CHECK-NEXT: .functype dot_i8x16_i7x16_add_s_i32x4 (v128, v128, v128) -> (v128){{$}} -; CHECK-NEXT: i32x4.dot_i8x16_i7x16_add_s $push[[R:[0-9]+]]=, $0, $1, $2{{$}} +; CHECK-NEXT: i32x4.relaxed_dot_i8x16_i7x16_add_s $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(<16 x i8>, <16 x i8>, - <4 x i32>) +declare <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed( + <16 x i8>, <16 x i8>, <4 x i32>) define <4 x i32> @dot_i8x16_i7x16_add_s_i32x4(<16 x i8> %a, <16 x i8> %b, <4 x i32> %c) { - %v = call <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed( + %v = call <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed( <16 x i8> %a, <16 x i8> %b, <4 x i32> %c ) ret <4 x i32> %v @@ -655,9 +655,9 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { ; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}} ; CHECK-NEXT: i64x2.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) +declare <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { - %v = call <2 x i64> @llvm.wasm.laneselect.v2i64( + %v = call <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64( <2 x i64> %a, <2 x i64> %b, <2 x i64> %c ) ret <2 x i64> %v @@ -738,25 +738,25 @@ define <4 x float> @nearest_v4f32(<4 x float> %a) { ret <4 x float> %v } -; CHECK-LABEL: fma_v4f32: -; CHECK-NEXT: .functype fma_v4f32 (v128, v128, v128) -> (v128){{$}} -; CHECK-NEXT: f32x4.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} +; CHECK-LABEL: madd_v4f32: +; CHECK-NEXT: .functype madd_v4f32 (v128, v128, v128) -> (v128){{$}} +; CHECK-NEXT: f32x4.relaxed_madd $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) -define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { - %v = call <4 x float> @llvm.wasm.fma.v4f32( +declare <4 x float> @llvm.wasm.relaxed.madd.v4f32(<4 x float>, <4 x float>, <4 x float>) +define <4 x float> @madd_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { + %v = call <4 x float> @llvm.wasm.relaxed.madd.v4f32( <4 x float> %a, <4 x float> %b, <4 x float> %c ) ret <4 x float> %v } -; CHECK-LABEL: fms_v4f32: -; CHECK-NEXT: .functype fms_v4f32 (v128, v128, v128) -> (v128){{$}} -; CHECK-NEXT: f32x4.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} +; CHECK-LABEL: nmadd_v4f32: +; CHECK-NEXT: .functype nmadd_v4f32 (v128, v128, v128) -> (v128){{$}} +; CHECK-NEXT: f32x4.relaxed_nmadd $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>) -define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { - %v = call <4 x float> @llvm.wasm.fms.v4f32( +declare <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(<4 x float>, <4 x float>, <4 x float>) +define <4 x float> @nmadd_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { + %v = call <4 x float> @llvm.wasm.relaxed.nmadd.v4f32( <4 x float> %a, <4 x float> %b, <4 x float> %c ) ret <4 x float> %v @@ -875,25 +875,27 @@ define <2 x double> @nearest_v2f64(<2 x double> %a) { ret <2 x double> %v } -; CHECK-LABEL: fma_v2f64: -; CHECK-NEXT: .functype fma_v2f64 (v128, v128, v128) -> (v128){{$}} -; CHECK-NEXT: f64x2.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} +; CHECK-LABEL: madd_v2f64: +; CHECK-NEXT: .functype madd_v2f64 (v128, v128, v128) -> (v128){{$}} +; CHECK-NEXT: f64x2.relaxed_madd $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <2 x double> @llvm.wasm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) -define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { - %v = call <2 x double> @llvm.wasm.fma.v2f64( +declare <2 x double> @llvm.wasm.relaxed.madd.v2f64( + <2 x double>, <2 x double>, <2 x double>) +define <2 x double> @madd_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { + %v = call <2 x double> @llvm.wasm.relaxed.madd.v2f64( <2 x double> %a, <2 x double> %b, <2 x double> %c ) ret <2 x double> %v } -; CHECK-LABEL: fms_v2f64: -; CHECK-NEXT: .functype fms_v2f64 (v128, v128, v128) -> (v128){{$}} -; CHECK-NEXT: f64x2.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} +; CHECK-LABEL: nmadd_v2f64: +; CHECK-NEXT: .functype nmadd_v2f64 (v128, v128, v128) -> (v128){{$}} +; CHECK-NEXT: f64x2.relaxed_nmadd $push[[R:[0-9]+]]=, $0, $1, $2{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}} -declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>) -define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { - %v = call <2 x double> @llvm.wasm.fms.v2f64( +declare <2 x double> @llvm.wasm.relaxed.nmadd.v2f64( + <2 x double>, <2 x double>, <2 x double>) +define <2 x double> @nmadd_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { + %v = call <2 x double> @llvm.wasm.relaxed.nmadd.v2f64( <2 x double> %a, <2 x double> %b, <2 x double> %c ) ret <2 x double> %v diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s index e50e56b..c6c5549 100644 --- a/llvm/test/MC/WebAssembly/simd-encodings.s +++ b/llvm/test/MC/WebAssembly/simd-encodings.s @@ -794,17 +794,17 @@ main: # CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0x84,0x02] i32x4.relaxed_trunc_f64x2_u_zero - # CHECK: f32x4.relaxed_fma # encoding: [0xfd,0x85,0x02] - f32x4.relaxed_fma + # CHECK: f32x4.relaxed_madd # encoding: [0xfd,0x85,0x02] + f32x4.relaxed_madd - # CHECK: f32x4.relaxed_fms # encoding: [0xfd,0x86,0x02] - f32x4.relaxed_fms + # CHECK: f32x4.relaxed_nmadd # encoding: [0xfd,0x86,0x02] + f32x4.relaxed_nmadd - # CHECK: f64x2.relaxed_fma # encoding: [0xfd,0x87,0x02] - f64x2.relaxed_fma + # CHECK: f64x2.relaxed_madd # encoding: [0xfd,0x87,0x02] + f64x2.relaxed_madd - # CHECK: f64x2.relaxed_fms # encoding: [0xfd,0x88,0x02] - f64x2.relaxed_fms + # CHECK: f64x2.relaxed_nmadd # encoding: [0xfd,0x88,0x02] + f64x2.relaxed_nmadd # CHECK: i8x16.relaxed_laneselect # encoding: [0xfd,0x89,0x02] i8x16.relaxed_laneselect @@ -833,10 +833,10 @@ main: # CHECK: i16x8.relaxed_q15mulr_s # encoding: [0xfd,0x91,0x02] i16x8.relaxed_q15mulr_s - # CHECK: i16x8.dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02] - i16x8.dot_i8x16_i7x16_s + # CHECK: i16x8.relaxed_dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02] + i16x8.relaxed_dot_i8x16_i7x16_s - # CHECK: i32x4.dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02] - i32x4.dot_i8x16_i7x16_add_s + # CHECK: i32x4.relaxed_dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02] + i32x4.relaxed_dot_i8x16_i7x16_add_s end_function