From: Stephen Boyd <sboyd@codeaurora.org>
Date: Tue, 31 Oct 2017 00:59:10 +0000 (-0700)
Subject: Merge tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Tag: v4.19~2132^2~21
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ae74ac0828868af3295395be7bc892e0d0aba376;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'clk-v4.15-exynos-pm' of git://git./linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - An addition of separate driver for the Exynos 4412 ISP CMU, needed
   to model and properly handle the clock controller's dependencies
   on the ISP power domain.
 - Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
   resume} ops to suppress compiler warnings with CONFIG_PM disabled.

* tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Add a separate driver for Exynos4412 ISP clocks
  clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
  clk: samsung: Instantiate Exynos4412 ISP clocks only when available
  clk: samsung: exynos5433: mark PM functions as __maybe_unused
---

ae74ac0828868af3295395be7bc892e0d0aba376
diff --cc drivers/clk/samsung/clk-exynos4.c
index f452abc,bdd6824..134f25f
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@@ -1193,12 -1194,22 +1203,8 @@@ static struct samsung_gate_clock exynos
  			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
  	GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
  			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
- 	GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
- 	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
- 	GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
- 		0),
  };
  
 -static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
 -	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
 -	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
 -	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
 -};
 -
 -static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
 -	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
 -};
 -
 -static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
 -	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
 -};
 -
  /*
   * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
   * resides in chipid register space, outside of the clock controller memory
@@@ -1506,12 -1539,33 +1514,21 @@@ static void __init exynos4_clk_init(str
  		samsung_clk_register_fixed_factor(ctx,
  			exynos4x12_fixed_factor_clks,
  			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
+ 
+ 		of_address_to_resource(np, 0, &res);
+ 		if (resource_size(&res) > 0x18000) {
+ 			samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
+ 				ARRAY_SIZE(exynos4x12_isp_div_clks));
+ 			samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
+ 				ARRAY_SIZE(exynos4x12_isp_gate_clks));
+ 		}
+ 
 -		if (of_machine_is_compatible("samsung,exynos4412")) {
 -			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
 -				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
 -				e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
 -				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
 -		} else {
 -			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
 -				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
 -				e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
 -				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
 -		}
 +		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
 +			mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
 +			e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
 +			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
  	}
  
 -	samsung_clk_register_alias(ctx, exynos4_aliases,
 -			ARRAY_SIZE(exynos4_aliases));
 -
  	if (soc == EXYNOS4X12)
  		exynos4x12_core_down_clock();
  	exynos4_clk_sleep_init();