From: Stefan Roese Date: Tue, 23 Oct 2018 10:25:16 +0000 (+0200) Subject: arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA X-Git-Tag: v2018.11~18^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ae4c38a5384033c7f5584e33cce1adc511fff333;p=platform%2Fkernel%2Fu-boot.git arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: Stefan Roese --- diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index 065e443..965c384 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -151,11 +151,11 @@ spi1: spi@10680 { status = "okay"; - fpga@2 { + fpga@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-generic-device"; - reg = <2>; /* Chip select 2 */ + reg = <0>; /* Chip select 0 */ spi-max-frequency = <27777777>; }; };