From: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat, 30 Apr 2022 09:01:52 +0000 (-0700)
Subject: intel/dev: Enable first set of DG2 PCI IDs
X-Git-Tag: upstream/22.3.5~9037
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ad565f6b70d9c4f2af34fe531d01ecf0eaa08500;p=platform%2Fupstream%2Fmesa.git

intel/dev: Enable first set of DG2 PCI IDs

Mostly Matt Roper's kernel patch commit message:

The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now.

The remaining DG2 IDs for add-in cards will be enabled in a future
patch once some additional required functionality has fully landed.

Ref: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
---

diff --git a/include/pci_ids/iris_pci_ids.h b/include/pci_ids/iris_pci_ids.h
index b3bb52c..9f460de 100644
--- a/include/pci_ids/iris_pci_ids.h
+++ b/include/pci_ids/iris_pci_ids.h
@@ -221,15 +221,14 @@ CHIPSET(0x4907, sg1, "SG1", "Intel(R) Graphics")
 CHIPSET(0x4908, dg1, "DG1", "Intel(R) Graphics")
 CHIPSET(0x4909, dg1, "DG1", "Intel(R) Graphics")
 
-/* Waiting on i915 upstream support */
-#if 0
-CHIPSET(0x4f80, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x4f81, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x4f82, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x4f83, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x4f84, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x4f87, dg2_g11, "DG2", "Intel(R) Graphics")
-CHIPSET(0x4f88, dg2_g11, "DG2", "Intel(R) Graphics")
+/* Commented devices are waiting on i915 upstream support */
+/* CHIPSET(0x4f80, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x4f81, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x4f82, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x4f83, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x4f84, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x4f87, dg2_g11, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x4f88, dg2_g11, "DG2", "Intel(R) Graphics") */
 CHIPSET(0x5690, dg2_g10, "DG2", "Intel(R) Graphics")
 CHIPSET(0x5691, dg2_g10, "DG2", "Intel(R) Graphics")
 CHIPSET(0x5692, dg2_g10, "DG2", "Intel(R) Graphics")
@@ -238,17 +237,16 @@ CHIPSET(0x5694, dg2_g11, "DG2", "Intel(R) Graphics")
 CHIPSET(0x5695, dg2_g11, "DG2", "Intel(R) Graphics")
 CHIPSET(0x5696, dg2_g12, "DG2", "Intel(R) Graphics")
 CHIPSET(0x5697, dg2_g12, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a1, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a2, dg2_g10, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a3, dg2_g12, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a4, dg2_g12, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a5, dg2_g11, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56a6, dg2_g11, "DG2", "Intel(R) Graphics")
+/* CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56a1, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56a2, dg2_g10, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56a3, dg2_g12, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56a4, dg2_g12, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56a5, dg2_g11, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56a6, dg2_g11, "DG2", "Intel(R) Graphics") */
 CHIPSET(0x56b0, dg2_g11, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Graphics")
+/* CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Graphics") */
 CHIPSET(0x56b2, dg2_g12, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Graphics")
-CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Graphics")
-#endif
+/* CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics") */
+/* CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Graphics") */
+/* CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Graphics") */
diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c
index b69831f..45381a4 100644
--- a/src/intel/dev/intel_device_info.c
+++ b/src/intel/dev/intel_device_info.c
@@ -71,6 +71,7 @@ static const struct {
    { "adl", 0x4680 },
    { "sg1", 0x4907 },
    { "rpl", 0xa780 },
+   { "dg2", 0x5690 },
 };
 
 /**
@@ -1072,17 +1073,17 @@ static const struct intel_device_info intel_device_info_sg1 = {
    .has_coarse_pixel_primitive_and_cb = true,                   \
    .has_mesh_shading = true
 
-UNUSED static const struct intel_device_info intel_device_info_dg2_g10 = {
+static const struct intel_device_info intel_device_info_dg2_g10 = {
    DG2_FEATURES,
    .platform = INTEL_PLATFORM_DG2_G10,
 };
 
-UNUSED static const struct intel_device_info intel_device_info_dg2_g11 = {
+static const struct intel_device_info intel_device_info_dg2_g11 = {
    DG2_FEATURES,
    .platform = INTEL_PLATFORM_DG2_G11,
 };
 
-UNUSED static const struct intel_device_info intel_device_info_dg2_g12 = {
+static const struct intel_device_info intel_device_info_dg2_g12 = {
    DG2_FEATURES,
    .platform = INTEL_PLATFORM_DG2_G12,
 };