From: Marek Olšák <marek.olsak@amd.com>
Date: Tue, 22 Mar 2022 06:13:20 +0000 (-0400)
Subject: radeonsi: initialize line stipple config registers
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ad4b575a8c9cab065db3c802ff281e2242679a2c;p=platform%2Fupstream%2Fmesa.git

radeonsi: initialize line stipple config registers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15965>
---

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 54f0001..d7cd93d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5448,6 +5448,14 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
                      S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
    }
 
+   if (sctx->chip_class >= GFX7) {
+      si_pm4_set_reg(pm4, R_030A00_PA_SU_LINE_STIPPLE_VALUE, 0);
+      si_pm4_set_reg(pm4, R_030A04_PA_SC_LINE_STIPPLE_STATE, 0);
+   } else {
+      si_pm4_set_reg(pm4, R_008A60_PA_SU_LINE_STIPPLE_VALUE, 0);
+      si_pm4_set_reg(pm4, R_008B10_PA_SC_LINE_STIPPLE_STATE, 0);
+   }
+
    if (sctx->chip_class <= GFX7 || !has_clear_state) {
       si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
       si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);