From: Vitaly Buka Date: Fri, 2 Sep 2022 02:02:25 +0000 (-0700) Subject: [msan] Use no-origin functions when possible X-Git-Tag: upstream/17.0.6~34658 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ad2b356f8584e80e6e4dedd66e1d47ead08a10bd;p=platform%2Fupstream%2Fllvm.git [msan] Use no-origin functions when possible Saves 1.8% of .text size on CTMark Reviewed By: kda Differential Revision: https://reviews.llvm.org/D133077 --- diff --git a/compiler-rt/lib/msan/msan.cpp b/compiler-rt/lib/msan/msan.cpp index 8f2d734..3e3bc3c 100644 --- a/compiler-rt/lib/msan/msan.cpp +++ b/compiler-rt/lib/msan/msan.cpp @@ -225,10 +225,6 @@ static void InitializeFlags() { if (f->store_context_size < 1) f->store_context_size = 1; } -void PrintWarning(uptr pc, uptr bp) { - PrintWarningWithOrigin(pc, bp, __msan_origin_tls); -} - void PrintWarningWithOrigin(uptr pc, uptr bp, u32 origin) { if (msan_expect_umr) { // Printf("Expected UMR\n"); @@ -386,7 +382,7 @@ MSAN_MAYBE_STORE_ORIGIN(u64, 8) void __msan_warning() { GET_CALLER_PC_BP_SP; (void)sp; - PrintWarning(pc, bp); + PrintWarningWithOrigin(pc, bp, 0); if (__msan::flags()->halt_on_error) { if (__msan::flags()->print_stats) ReportStats(); @@ -398,7 +394,7 @@ void __msan_warning() { void __msan_warning_noreturn() { GET_CALLER_PC_BP_SP; (void)sp; - PrintWarning(pc, bp); + PrintWarningWithOrigin(pc, bp, 0); if (__msan::flags()->print_stats) ReportStats(); Printf("Exiting\n"); diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index d1aae72..635da6c 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -783,10 +783,16 @@ void MemorySanitizer::createUserspaceApi(Module &M) { // Create the callback. // FIXME: this function should have "Cold" calling conv, // which is not yet implemented. - StringRef WarningFnName = Recover ? "__msan_warning_with_origin" - : "__msan_warning_with_origin_noreturn"; - WarningFn = - M.getOrInsertFunction(WarningFnName, IRB.getVoidTy(), IRB.getInt32Ty()); + if (TrackOrigins) { + StringRef WarningFnName = Recover ? "__msan_warning_with_origin" + : "__msan_warning_with_origin_noreturn"; + WarningFn = + M.getOrInsertFunction(WarningFnName, IRB.getVoidTy(), IRB.getInt32Ty()); + } else { + StringRef WarningFnName = + Recover ? "__msan_warning" : "__msan_warning_noreturn"; + WarningFn = M.getOrInsertFunction(WarningFnName, IRB.getVoidTy()); + } // Create the global TLS variables. RetvalTLS = @@ -1238,7 +1244,10 @@ struct MemorySanitizerVisitor : public InstVisitor { if (!Origin) Origin = (Value *)IRB.getInt32(0); assert(Origin->getType()->isIntegerTy()); - IRB.CreateCall(MS.WarningFn, Origin)->setCannotMerge(); + if (MS.CompileKernel || MS.TrackOrigins) + IRB.CreateCall(MS.WarningFn, Origin)->setCannotMerge(); + else + IRB.CreateCall(MS.WarningFn)->setCannotMerge(); // FIXME: Insert UnreachableInst if !MS.Recover? // This may invalidate some of the following checks and needs to be done // at the very end. diff --git a/llvm/test/Instrumentation/MemorySanitizer/atomics.ll b/llvm/test/Instrumentation/MemorySanitizer/atomics.ll index 63ff41c..a38b49e 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/atomics.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/atomics.ll @@ -1,6 +1,6 @@ -; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning" -; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning" -; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=2 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning" +; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,NOORIGINS --implicit-check-not="call void @__msan_warning" +; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,ORIGINS --implicit-check-not="call void @__msan_warning" +; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=2 -S -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,ORIGINS --implicit-check-not="call void @__msan_warning" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -62,7 +62,8 @@ entry: ; CHECK: store i32 0, ; CHECK: icmp ; CHECK: br -; CHECK: @__msan_warning_with_origin +; NOORIGINS: @__msan_warning_noreturn() +; ORIGINS: @__msan_warning_with_origin_noreturn( ; CHECK: cmpxchg {{.*}} seq_cst seq_cst ; CHECK: store i32 0, {{.*}} @__msan_retval_tls ; CHECK: ret i32 @@ -81,7 +82,8 @@ entry: ; CHECK: store i32 0, ; CHECK: icmp ; CHECK: br -; CHECK: @__msan_warning_with_origin +; NOORIGINS: @__msan_warning_noreturn() +; ORIGINS: @__msan_warning_with_origin_noreturn( ; CHECK: cmpxchg {{.*}} release monotonic ; CHECK: store i32 0, {{.*}} @__msan_retval_tls ; CHECK: ret i32 diff --git a/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll index 477d8fb..e0c832c 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll @@ -84,7 +84,7 @@ define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], i8 7) @@ -109,7 +109,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) #0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 7) @@ -132,7 +132,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[A2:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 0) @@ -140,7 +140,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i256 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[A3:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A2]], i8 1) @@ -148,7 +148,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i256 [[TMP10]], 0 ; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF0]] ; CHECK: 11: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 12: ; CHECK-NEXT: [[A4:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A3]], i8 2) @@ -156,7 +156,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i256 [[TMP13]], 0 ; CHECK-NEXT: br i1 [[_MSCMP5]], label [[TMP14:%.*]], label [[TMP15:%.*]], !prof [[PROF0]] ; CHECK: 14: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 15: ; CHECK-NEXT: [[A5:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A4]], i8 3) @@ -164,7 +164,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i256 [[TMP16]], 0 ; CHECK-NEXT: br i1 [[_MSCMP6]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF0]] ; CHECK: 17: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 18: ; CHECK-NEXT: [[A6:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A5]], i8 4) @@ -172,7 +172,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i256 [[TMP19]], 0 ; CHECK-NEXT: br i1 [[_MSCMP7]], label [[TMP20:%.*]], label [[TMP21:%.*]], !prof [[PROF0]] ; CHECK: 20: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 21: ; CHECK-NEXT: [[A7:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A6]], i8 5) @@ -180,7 +180,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i256 [[TMP22]], 0 ; CHECK-NEXT: br i1 [[_MSCMP8]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF0]] ; CHECK: 23: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 24: ; CHECK-NEXT: [[A8:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A7]], i8 6) @@ -188,7 +188,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i256 [[TMP25]], 0 ; CHECK-NEXT: br i1 [[_MSCMP9]], label [[TMP26:%.*]], label [[TMP27:%.*]], !prof [[PROF0]] ; CHECK: 26: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 27: ; CHECK-NEXT: [[A9:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A8]], i8 7) @@ -196,7 +196,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP10:%.*]] = icmp ne i256 [[TMP28]], 0 ; CHECK-NEXT: br i1 [[_MSCMP10]], label [[TMP29:%.*]], label [[TMP30:%.*]], !prof [[PROF0]] ; CHECK: 29: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 30: ; CHECK-NEXT: [[A10:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A9]], i8 8) @@ -204,7 +204,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP11:%.*]] = icmp ne i256 [[TMP31]], 0 ; CHECK-NEXT: br i1 [[_MSCMP11]], label [[TMP32:%.*]], label [[TMP33:%.*]], !prof [[PROF0]] ; CHECK: 32: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 33: ; CHECK-NEXT: [[A11:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A10]], i8 9) @@ -212,7 +212,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP12:%.*]] = icmp ne i256 [[TMP34]], 0 ; CHECK-NEXT: br i1 [[_MSCMP12]], label [[TMP35:%.*]], label [[TMP36:%.*]], !prof [[PROF0]] ; CHECK: 35: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 36: ; CHECK-NEXT: [[A12:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A11]], i8 10) @@ -220,7 +220,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP37]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP38:%.*]], label [[TMP39:%.*]], !prof [[PROF0]] ; CHECK: 38: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 39: ; CHECK-NEXT: [[A13:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A12]], i8 11) @@ -228,7 +228,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP13:%.*]] = icmp ne i256 [[TMP40]], 0 ; CHECK-NEXT: br i1 [[_MSCMP13]], label [[TMP41:%.*]], label [[TMP42:%.*]], !prof [[PROF0]] ; CHECK: 41: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 42: ; CHECK-NEXT: [[A14:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A13]], i8 12) @@ -236,7 +236,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP14:%.*]] = icmp ne i256 [[TMP43]], 0 ; CHECK-NEXT: br i1 [[_MSCMP14]], label [[TMP44:%.*]], label [[TMP45:%.*]], !prof [[PROF0]] ; CHECK: 44: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 45: ; CHECK-NEXT: [[A15:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A14]], i8 13) @@ -244,7 +244,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP15:%.*]] = icmp ne i256 [[TMP46]], 0 ; CHECK-NEXT: br i1 [[_MSCMP15]], label [[TMP47:%.*]], label [[TMP48:%.*]], !prof [[PROF0]] ; CHECK: 47: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 48: ; CHECK-NEXT: [[A16:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A15]], i8 14) @@ -252,7 +252,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP16:%.*]] = icmp ne i256 [[TMP49]], 0 ; CHECK-NEXT: br i1 [[_MSCMP16]], label [[TMP50:%.*]], label [[TMP51:%.*]], !prof [[PROF0]] ; CHECK: 50: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 51: ; CHECK-NEXT: [[A17:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A16]], i8 15) @@ -260,7 +260,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP17:%.*]] = icmp ne i256 [[TMP52]], 0 ; CHECK-NEXT: br i1 [[_MSCMP17]], label [[TMP53:%.*]], label [[TMP54:%.*]], !prof [[PROF0]] ; CHECK: 53: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 54: ; CHECK-NEXT: [[A18:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A17]], i8 16) @@ -268,7 +268,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP18:%.*]] = icmp ne i256 [[TMP55]], 0 ; CHECK-NEXT: br i1 [[_MSCMP18]], label [[TMP56:%.*]], label [[TMP57:%.*]], !prof [[PROF0]] ; CHECK: 56: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 57: ; CHECK-NEXT: [[A19:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A18]], i8 17) @@ -276,7 +276,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP19:%.*]] = icmp ne i256 [[TMP58]], 0 ; CHECK-NEXT: br i1 [[_MSCMP19]], label [[TMP59:%.*]], label [[TMP60:%.*]], !prof [[PROF0]] ; CHECK: 59: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 60: ; CHECK-NEXT: [[A20:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A19]], i8 18) @@ -284,7 +284,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP20:%.*]] = icmp ne i256 [[TMP61]], 0 ; CHECK-NEXT: br i1 [[_MSCMP20]], label [[TMP62:%.*]], label [[TMP63:%.*]], !prof [[PROF0]] ; CHECK: 62: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 63: ; CHECK-NEXT: [[A21:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A20]], i8 19) @@ -292,7 +292,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP21:%.*]] = icmp ne i256 [[TMP64]], 0 ; CHECK-NEXT: br i1 [[_MSCMP21]], label [[TMP65:%.*]], label [[TMP66:%.*]], !prof [[PROF0]] ; CHECK: 65: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 66: ; CHECK-NEXT: [[A22:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A21]], i8 20) @@ -300,7 +300,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP22:%.*]] = icmp ne i256 [[TMP67]], 0 ; CHECK-NEXT: br i1 [[_MSCMP22]], label [[TMP68:%.*]], label [[TMP69:%.*]], !prof [[PROF0]] ; CHECK: 68: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 69: ; CHECK-NEXT: [[A23:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A22]], i8 21) @@ -308,7 +308,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP23:%.*]] = icmp ne i256 [[TMP70]], 0 ; CHECK-NEXT: br i1 [[_MSCMP23]], label [[TMP71:%.*]], label [[TMP72:%.*]], !prof [[PROF0]] ; CHECK: 71: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 72: ; CHECK-NEXT: [[A24:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A23]], i8 22) @@ -316,7 +316,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP24:%.*]] = icmp ne i256 [[TMP73]], 0 ; CHECK-NEXT: br i1 [[_MSCMP24]], label [[TMP74:%.*]], label [[TMP75:%.*]], !prof [[PROF0]] ; CHECK: 74: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 75: ; CHECK-NEXT: [[A25:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A24]], i8 23) @@ -324,7 +324,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP25:%.*]] = icmp ne i256 [[TMP76]], 0 ; CHECK-NEXT: br i1 [[_MSCMP25]], label [[TMP77:%.*]], label [[TMP78:%.*]], !prof [[PROF0]] ; CHECK: 77: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 78: ; CHECK-NEXT: [[A26:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A25]], i8 24) @@ -332,7 +332,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP26:%.*]] = icmp ne i256 [[TMP79]], 0 ; CHECK-NEXT: br i1 [[_MSCMP26]], label [[TMP80:%.*]], label [[TMP81:%.*]], !prof [[PROF0]] ; CHECK: 80: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 81: ; CHECK-NEXT: [[A27:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A26]], i8 25) @@ -340,7 +340,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP27:%.*]] = icmp ne i256 [[TMP82]], 0 ; CHECK-NEXT: br i1 [[_MSCMP27]], label [[TMP83:%.*]], label [[TMP84:%.*]], !prof [[PROF0]] ; CHECK: 83: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 84: ; CHECK-NEXT: [[A28:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A27]], i8 26) @@ -348,7 +348,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP28:%.*]] = icmp ne i256 [[TMP85]], 0 ; CHECK-NEXT: br i1 [[_MSCMP28]], label [[TMP86:%.*]], label [[TMP87:%.*]], !prof [[PROF0]] ; CHECK: 86: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 87: ; CHECK-NEXT: [[A29:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A28]], i8 27) @@ -356,7 +356,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP29:%.*]] = icmp ne i256 [[TMP88]], 0 ; CHECK-NEXT: br i1 [[_MSCMP29]], label [[TMP89:%.*]], label [[TMP90:%.*]], !prof [[PROF0]] ; CHECK: 89: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 90: ; CHECK-NEXT: [[A30:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A29]], i8 28) @@ -364,7 +364,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP30:%.*]] = icmp ne i256 [[TMP91]], 0 ; CHECK-NEXT: br i1 [[_MSCMP30]], label [[TMP92:%.*]], label [[TMP93:%.*]], !prof [[PROF0]] ; CHECK: 92: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 93: ; CHECK-NEXT: [[A31:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A30]], i8 29) @@ -372,7 +372,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP31:%.*]] = icmp ne i256 [[TMP94]], 0 ; CHECK-NEXT: br i1 [[_MSCMP31]], label [[TMP95:%.*]], label [[TMP96:%.*]], !prof [[PROF0]] ; CHECK: 95: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 96: ; CHECK-NEXT: [[A32:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A31]], i8 30) @@ -380,7 +380,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x floa ; CHECK-NEXT: [[_MSCMP32:%.*]] = icmp ne i256 [[TMP97]], 0 ; CHECK-NEXT: br i1 [[_MSCMP32]], label [[TMP98:%.*]], label [[TMP99:%.*]], !prof [[PROF0]] ; CHECK: 98: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 99: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A32]], i8 31) @@ -432,7 +432,7 @@ define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> [[A0:%.*]]) @@ -453,7 +453,7 @@ define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> [[A0:%.*]]) @@ -474,7 +474,7 @@ define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> [[A0:%.*]]) @@ -495,7 +495,7 @@ define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> [[A0:%.*]]) @@ -516,7 +516,7 @@ define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> [[A0:%.*]]) @@ -541,7 +541,7 @@ define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) #0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 7) @@ -629,7 +629,7 @@ define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* [[A0]]) @@ -653,7 +653,7 @@ define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x i64> %mask) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.maskload.pd(i8* [[A0:%.*]], <2 x i64> [[MASK:%.*]]) @@ -677,7 +677,7 @@ define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x i64> %mask) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* [[A0:%.*]], <4 x i64> [[MASK:%.*]]) @@ -701,7 +701,7 @@ define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x i32> %mask) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.maskload.ps(i8* [[A0:%.*]], <4 x i32> [[MASK:%.*]]) @@ -725,7 +725,7 @@ define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x i32> %mask) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* [[A0:%.*]], <8 x i32> [[MASK:%.*]]) @@ -753,7 +753,7 @@ define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x i64> %mask, <2 x double> %a ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx.maskstore.pd(i8* [[A0:%.*]], <2 x i64> [[MASK:%.*]], <2 x double> [[A2:%.*]]) @@ -780,7 +780,7 @@ define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x i64> %mask, <4 x double ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx.maskstore.pd.256(i8* [[A0:%.*]], <4 x i64> [[MASK:%.*]], <4 x double> [[A2:%.*]]) @@ -807,7 +807,7 @@ define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2 ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx.maskstore.ps(i8* [[A0:%.*]], <4 x i32> [[MASK:%.*]], <4 x float> [[A2:%.*]]) @@ -834,7 +834,7 @@ define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x i32> %mask, <8 x float> ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx.maskstore.ps.256(i8* [[A0:%.*]], <8 x i32> [[MASK:%.*]], <8 x float> [[A2:%.*]]) @@ -918,7 +918,7 @@ define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> [[A0:%.*]]) @@ -939,7 +939,7 @@ define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> [[A0:%.*]]) @@ -964,7 +964,7 @@ define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) @@ -989,7 +989,7 @@ define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) @@ -1014,7 +1014,7 @@ define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) @@ -1049,7 +1049,7 @@ define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> [[A0:%.*]], i32 7) @@ -1070,7 +1070,7 @@ define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> [[A0:%.*]], i32 7) @@ -1108,7 +1108,7 @@ define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[A0:%.*]], <2 x i64> [[A1:%.*]]) @@ -1133,7 +1133,7 @@ define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A0:%.*]], <4 x i64> [[A1:%.*]]) @@ -1153,7 +1153,7 @@ define <4 x double> @test_x86_avx_vpermilvar_pd_256_2(<4 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A0:%.*]], <4 x i64> ) @@ -1176,7 +1176,7 @@ define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) # ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0:%.*]], <4 x i32> [[A1:%.*]]) @@ -1194,7 +1194,7 @@ define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A2:%.*]] = load <4 x i32>, <4 x i32>* [[A1:%.*]], align 16 @@ -1209,7 +1209,7 @@ define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] ; CHECK: 10: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0:%.*]], <4 x i32> [[A2]]) @@ -1235,7 +1235,7 @@ define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[A0:%.*]], <8 x i32> [[A1:%.*]]) @@ -1260,7 +1260,7 @@ define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) @@ -1285,7 +1285,7 @@ define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) @@ -1310,7 +1310,7 @@ define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) @@ -1335,7 +1335,7 @@ define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) @@ -1360,7 +1360,7 @@ define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) @@ -1385,7 +1385,7 @@ define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) #0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) @@ -1410,7 +1410,7 @@ define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) @@ -1435,7 +1435,7 @@ define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) @@ -1460,7 +1460,7 @@ define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) @@ -1485,7 +1485,7 @@ define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) @@ -1510,7 +1510,7 @@ define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) @@ -1535,7 +1535,7 @@ define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) @@ -1584,7 +1584,7 @@ define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <4 x i64>* [[CAST]] to i64 @@ -1610,7 +1610,7 @@ define void @movnt_ps(i8* %p, <8 x float> %a) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <8 x float>* [[CAST]] to i64 @@ -1637,7 +1637,7 @@ define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR8]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <4 x double>* [[CAST]] to i64 diff --git a/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll index 174eb1d..37644bf 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll @@ -162,7 +162,7 @@ define i32 @test_x86_avx2_pmovmskb(<32 x i8> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> [[A0:%.*]]) @@ -491,7 +491,7 @@ define <16 x i16> @test_x86_avx2_psrl_w_load(<16 x i16> %a0, <8 x i16>* %p) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 16 @@ -686,7 +686,7 @@ define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(<32 x i8>* %ptr, <32 x i8> ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, <32 x i8>* [[PTR:%.*]], align 32 @@ -799,7 +799,7 @@ define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]], i8 7) @@ -819,7 +819,7 @@ define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(<32 x i8>* %ptr, <32 x i8> %a1 ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, <32 x i8>* [[PTR:%.*]], align 32 @@ -834,7 +834,7 @@ define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(<32 x i8>* %ptr, <32 x i8> %a1 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] ; CHECK: 10: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> [[A0]], <32 x i8> [[A1:%.*]], i8 7) @@ -973,7 +973,7 @@ define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x i32> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.permps(<8 x float> [[A0:%.*]], <8 x i32> [[A1:%.*]]) @@ -997,7 +997,7 @@ define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* [[A0:%.*]], <2 x i64> [[A1:%.*]]) @@ -1021,7 +1021,7 @@ define <4 x i64> @test_x86_avx2_maskload_q_256(i8* %a0, <4 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* [[A0:%.*]], <4 x i64> [[A1:%.*]]) @@ -1045,7 +1045,7 @@ define <4 x i32> @test_x86_avx2_maskload_d(i8* %a0, <4 x i32> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* [[A0:%.*]], <4 x i32> [[A1:%.*]]) @@ -1069,7 +1069,7 @@ define <8 x i32> @test_x86_avx2_maskload_d_256(i8* %a0, <8 x i32> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* [[A0:%.*]], <8 x i32> [[A1:%.*]]) @@ -1097,7 +1097,7 @@ define void @test_x86_avx2_maskstore_q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) #0 ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q(i8* [[A0:%.*]], <2 x i64> [[A1:%.*]], <2 x i64> [[A2:%.*]]) @@ -1124,7 +1124,7 @@ define void @test_x86_avx2_maskstore_q_256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2 ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q.256(i8* [[A0:%.*]], <4 x i64> [[A1:%.*]], <4 x i64> [[A2:%.*]]) @@ -1151,7 +1151,7 @@ define void @test_x86_avx2_maskstore_d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) #0 ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d(i8* [[A0:%.*]], <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) @@ -1178,7 +1178,7 @@ define void @test_x86_avx2_maskstore_d_256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2 ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: ; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d.256(i8* [[A0:%.*]], <8 x i32> [[A1:%.*]], <8 x i32> [[A2:%.*]]) @@ -1555,7 +1555,7 @@ define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, i8* %a1, <4 x i ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2) @@ -1588,7 +1588,7 @@ define <4 x double> @test_x86_avx2_gather_d_pd_256(<4 x double> %a0, i8* %a1, <4 ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2) @@ -1621,7 +1621,7 @@ define <2 x double> @test_x86_avx2_gather_q_pd(<2 x double> %a0, i8* %a1, <2 x i ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2) @@ -1654,7 +1654,7 @@ define <4 x double> @test_x86_avx2_gather_q_pd_256(<4 x double> %a0, i8* %a1, <4 ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2) @@ -1687,7 +1687,7 @@ define <4 x float> @test_x86_avx2_gather_d_ps(<4 x float> %a0, i8* %a1, <4 x i32 ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) @@ -1720,7 +1720,7 @@ define <8 x float> @test_x86_avx2_gather_d_ps_256(<8 x float> %a0, i8* %a1, <8 x ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], i8* [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 2) @@ -1753,7 +1753,7 @@ define <4 x float> @test_x86_avx2_gather_q_ps(<4 x float> %a0, i8* %a1, <2 x i64 ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) @@ -1786,7 +1786,7 @@ define <4 x float> @test_x86_avx2_gather_q_ps_256(<4 x float> %a0, i8* %a1, <4 x ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) @@ -1819,7 +1819,7 @@ define <2 x i64> @test_x86_avx2_gather_d_q(<2 x i64> %a0, i8* %a1, <4 x i32> %id ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2) @@ -1852,7 +1852,7 @@ define <4 x i64> @test_x86_avx2_gather_d_q_256(<4 x i64> %a0, i8* %a1, <4 x i32> ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2) @@ -1885,7 +1885,7 @@ define <2 x i64> @test_x86_avx2_gather_q_q(<2 x i64> %a0, i8* %a1, <2 x i64> %id ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2) @@ -1918,7 +1918,7 @@ define <4 x i64> @test_x86_avx2_gather_q_q_256(<4 x i64> %a0, i8* %a1, <4 x i64> ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2) @@ -1951,7 +1951,7 @@ define <4 x i32> @test_x86_avx2_gather_d_d(<4 x i32> %a0, i8* %a1, <4 x i32> %id ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) @@ -1984,7 +1984,7 @@ define <8 x i32> @test_x86_avx2_gather_d_d_256(<8 x i32> %a0, i8* %a1, <8 x i32> ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> [[A0:%.*]], i8* [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x i32> [[MASK:%.*]], i8 2) @@ -2017,7 +2017,7 @@ define <4 x i32> @test_x86_avx2_gather_q_d(<4 x i32> %a0, i8* %a1, <2 x i64> %id ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) @@ -2050,7 +2050,7 @@ define <4 x i32> @test_x86_avx2_gather_q_d_256(<4 x i32> %a0, i8* %a1, <4 x i64> ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) @@ -2085,7 +2085,7 @@ define <8 x float> @test_gather_mask(<8 x float> %a0, float* %a, <8 x i32> %idx ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF0]] ; CHECK: 9: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 10: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], i8* [[A_I8]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 4) @@ -2093,7 +2093,7 @@ define <8 x float> @test_gather_mask(<8 x float> %a0, float* %a, <8 x i32> %idx ; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP5]], 0 ; CHECK-NEXT: br i1 [[_MSCMP6]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF0]] ; CHECK: 11: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 12: ; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint <8 x float>* [[OUT_PTR]] to i64 @@ -2135,7 +2135,7 @@ define <2 x i64> @test_mask_demanded_bits(<2 x i64> %a0, i8* %a1, <2 x i64> %idx ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK1]], i8 2) diff --git a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll index b3c054a..8a9846f 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll @@ -43,7 +43,7 @@ entry: ; CHECK: icmp ; CHECK: br i1 ; CHECK: {{^[0-9]+}}: -; CHECK: call void @__msan_warning_with_origin_noreturn +; CHECK: call void @__msan_warning_noreturn() ; CHECK: {{^[0-9]+}}: ; CHECK: xor ; CHECK: store diff --git a/llvm/test/Instrumentation/MemorySanitizer/csr.ll b/llvm/test/Instrumentation/MemorySanitizer/csr.ll index 63f789f..160ebbb 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/csr.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/csr.ll @@ -1,5 +1,6 @@ ; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s --implicit-check-not="call void @__msan_warning" ; RUN: opt < %s -msan-check-access-address=1 -S -passes=msan 2>&1 | FileCheck %s --check-prefix=ADDR --implicit-check-not="call void @__msan_warning" + ; REQUIRES: x86-registered-target target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" @@ -24,7 +25,7 @@ entry: ; ADDR: %[[A:.*]] = load i64, i64* getelementptr inbounds {{.*}} @__msan_param_tls, i32 0, i32 0), align 8 ; ADDR: %[[B:.*]] = icmp ne i64 %[[A]], 0 ; ADDR: br i1 %[[B]], label {{.*}}, label -; ADDR: call void @__msan_warning_with_origin_noreturn(i32 0) +; ADDR: call void @__msan_warning_noreturn() ; ADDR: call void @llvm.x86.sse.stmxcsr( ; ADDR: ret void @@ -40,7 +41,7 @@ entry: ; CHECK: %[[A:.*]] = load i32, i32* %{{.*}}, align 1 ; CHECK: %[[B:.*]] = icmp ne i32 %[[A]], 0 ; CHECK: br i1 %[[B]], label {{.*}}, label -; CHECK: call void @__msan_warning_with_origin_noreturn(i32 0) +; CHECK: call void @__msan_warning_noreturn() ; CHECK: call void @llvm.x86.sse.ldmxcsr( ; CHECK: ret void @@ -51,6 +52,6 @@ entry: ; ADDR: %[[D:.*]] = icmp ne i32 %[[C]], 0 ; ADDR: %[[E:.*]] = or i1 %[[B]], %[[D]] ; ADDR: br i1 %[[E]], label {{.*}}, label -; ADDR: call void @__msan_warning_with_origin_noreturn(i32 0) +; ADDR: call void @__msan_warning_noreturn() ; ADDR: call void @llvm.x86.sse.ldmxcsr( ; ADDR: ret void diff --git a/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll b/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll index b1d6340..8dd81b4 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll @@ -51,7 +51,7 @@ entry: ; ADDR: %[[MASKBAD:.*]] = icmp ne i4 %[[MASKSHADOWFLAT]], 0 ; ADDR: %[[OR:.*]] = or i1 %[[ADDRBAD]], %[[MASKBAD]] ; ADDR: br i1 %[[OR]], label {{.*}}, label {{.*}} -; ADDR: call void @__msan_warning_with_origin_noreturn(i32 0) +; ADDR: call void @__msan_warning_noreturn() ; ADDR: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask) ; ADDR: ret void @@ -89,7 +89,7 @@ entry: ; ADDR: %[[MASKBAD:.*]] = icmp ne i4 %[[MASKSHADOWFLAT]], 0 ; ADDR: %[[OR:.*]] = or i1 %[[ADDRBAD]], %[[MASKBAD]] ; ADDR: br i1 %[[OR]], label {{.*}}, label {{.*}} -; ADDR: call void @__msan_warning_with_origin_noreturn(i32 0) +; ADDR: call void @__msan_warning_noreturn() ; ADDR: = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v) ; ADDR: ret <4 x double> diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll index 419344f..9a9ff61 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -msan-check-access-address=0 -S -passes='module(msan-module),function(msan)' 2>&1 | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="call void @__msan_warning" -; RUN: opt < %s --passes='module(msan-module),function(msan)' -msan-check-access-address=0 -S | FileCheck -allow-deprecated-dag-overlap %s --implicit-check-not="call void @__msan_warning" +; RUN: opt < %s -msan-check-access-address=0 -S -passes='module(msan-module),function(msan)' 2>&1 | FileCheck -allow-deprecated-dag-overlap %s --check-prefixes=CHECK,NOORIGINS --implicit-check-not="call void @__msan_warning" +; RUN: opt < %s --passes='module(msan-module),function(msan)' -msan-check-access-address=0 -S | FileCheck -allow-deprecated-dag-overlap %s --check-prefixes=CHECK,NOORIGINS --implicit-check-not="call void @__msan_warning" ; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes='module(msan-module),function(msan)' 2>&1 | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CHECK,ORIGINS %s --implicit-check-not="call void @__msan_warning" ; RUN: opt < %s -passes='module(msan-module),function(msan)' -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CHECK,ORIGINS %s --implicit-check-not="call void @__msan_warning" ; RUN: opt < %s -passes='module(msan-module),function(msan)' -msan-instrumentation-with-call-threshold=0 -msan-track-origins=1 -S | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CHECK-CALLS %s --implicit-check-not="call void @__msan_warning" @@ -90,8 +90,8 @@ declare void @foo(...) ; CHECK: %0 = load i32, ; CHECK: = load ; ORIGINS: %[[ORIGIN:.*]] = load -; CHECK: call void @__msan_warning_with_origin_noreturn(i32 -; ORIGINS-SAME %[[ORIGIN]]) +; NOORIGINS: call void @__msan_warning_noreturn() +; ORIGINS: call void @__msan_warning_with_origin_noreturn(i32 %[[ORIGIN]]) ; CHECK-CONT: ; CHECK-NEXT: unreachable ; CHECK: br i1 %tobool @@ -143,7 +143,8 @@ entry: } ; CHECK-LABEL: @FuncWithPhi -; CHECK: call void @__msan_warning_with_origin_noreturn(i32 +; NOORIGINS: call void @__msan_warning_noreturn() +; ORIGINS: call void @__msan_warning_with_origin_noreturn(i32 ; CHECK: = phi ; CHECK-NEXT: = phi ; CHECK: store @@ -447,7 +448,8 @@ entry: ; CHECK-LABEL: @Div ; CHECK: icmp -; CHECK: call void @__msan_warning_with_origin +; NOORIGINS: call void @__msan_warning_noreturn() +; ORIGINS: call void @__msan_warning_with_origin_noreturn(i32 ; CHECK-NOT: icmp ; CHECK: udiv ; CHECK-NOT: icmp @@ -494,9 +496,9 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-LABEL: @ICmpSLTZero ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory { @@ -506,9 +508,9 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-LABEL: @ICmpSGEZero ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sge -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory { @@ -518,9 +520,9 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-LABEL: @ICmpSGTZero ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sgt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory { @@ -530,9 +532,9 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-LABEL: @ICmpSLEZero ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sle -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 @@ -545,9 +547,9 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-LABEL: @ICmpSLTAllOnes ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_memory { @@ -557,9 +559,9 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-LABEL: @ICmpSGEAllOnes ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sge -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_memory { @@ -569,9 +571,9 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-LABEL: @ICmpSGTAllOnes ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sgt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_memory { @@ -581,9 +583,9 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-LABEL: @ICmpSLEAllOnes ; CHECK: icmp slt -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sle -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 @@ -597,9 +599,9 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x i32*> %x) nounwind uwtable readnone sa ; CHECK-LABEL: @ICmpSLT_vector_Zero ; CHECK: icmp slt <2 x i64> -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp slt <2 x i32*> -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret <2 x i1> ; Check that we propagate shadow for x<=-1, x>0, etc (i.e. sign bit tests) @@ -612,9 +614,9 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone ; CHECK-LABEL: @ICmpSLT_vector_AllOnes ; CHECK: icmp slt <2 x i32> -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp slt <2 x i32> -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret <2 x i1> @@ -629,11 +631,11 @@ entry: ; CHECK-LABEL: @ICmpUGTConst ; CHECK: icmp ugt i32 -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp ugt i32 -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: icmp ugt i32 -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 @@ -675,7 +677,8 @@ define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) sanitize_memory { ; CHECK-LABEL: @ExtractElement ; CHECK: extractelement -; CHECK: call void @__msan_warning_with_origin +; NOORIGINS: call void @__msan_warning_noreturn() +; ORIGINS: call void @__msan_warning_with_origin_noreturn(i32 ; CHECK: extractelement ; CHECK: ret i32 @@ -686,7 +689,8 @@ define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) sanitize_memor ; CHECK-LABEL: @InsertElement ; CHECK: insertelement -; CHECK: call void @__msan_warning_with_origin +; NOORIGINS: call void @__msan_warning_noreturn() +; ORIGINS: call void @__msan_warning_with_origin_noreturn(i32 ; CHECK: insertelement ; CHECK: ret <4 x i32> @@ -698,7 +702,7 @@ define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) sanitize_memory ; CHECK-LABEL: @ShuffleVector ; CHECK: shufflevector -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: shufflevector ; CHECK: ret <4 x i32> @@ -712,11 +716,11 @@ define i32 @BSwap(i32 %x) nounwind uwtable readnone sanitize_memory { declare i32 @llvm.bswap.i32(i32) nounwind readnone ; CHECK-LABEL: @BSwap -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: @llvm.bswap.i32 -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: @llvm.bswap.i32 -; CHECK-NOT: call void @__msan_warning_with_origin +; CHECK-NOT: call void @__msan_warning ; CHECK: ret i32 ; Test handling of vectors of pointers. diff --git a/llvm/test/Instrumentation/MemorySanitizer/return_from_main.ll b/llvm/test/Instrumentation/MemorySanitizer/return_from_main.ll index c088d94..d9b831e 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/return_from_main.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/return_from_main.ll @@ -15,5 +15,5 @@ declare i32 @f() sanitize_memory ; CHECK: call i32 @f() ; CHECK: store i32 0, {{.*}} @__msan_retval_tls ; CHECK: br i1 -; CHECK: call void @__msan_warning_with_origin_noreturn(i32 0) +; CHECK: call void @__msan_warning_noreturn() ; CHECK: ret i32 diff --git a/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll index 9f5e0f4..8e5fecf 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll @@ -164,7 +164,7 @@ define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR5:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[A0:%.*]]) @@ -185,7 +185,7 @@ define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR5]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[A0:%.*]]) @@ -211,7 +211,7 @@ define void @test_x86_sse_ldmxcsr(i8* %a0) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR5]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: call void @llvm.x86.sse.ldmxcsr(i8* [[A0]]) @@ -298,7 +298,7 @@ define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR5]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> [[A0:%.*]]) @@ -379,7 +379,7 @@ define void @test_x86_sse_stmxcsr(i8* %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR5]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: call void @llvm.x86.sse.stmxcsr(i8* [[A0]]) diff --git a/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll index 74083b4..a1b937c 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll @@ -164,7 +164,7 @@ define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]]) @@ -185,7 +185,7 @@ define <2 x i64> @test_mm_cvtpd_epi32_zext(<2 x double> %a0) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]]) @@ -208,7 +208,7 @@ define <2 x i64> @test_mm_cvtpd_epi32_zext_load(<2 x double>* %p0) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] ; CHECK: 2: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: ; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, <2 x double>* [[P0:%.*]], align 16 @@ -220,7 +220,7 @@ define <2 x i64> @test_mm_cvtpd_epi32_zext_load(<2 x double>* %p0) nounwind #0 { ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0]]) @@ -245,7 +245,7 @@ define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]]) @@ -265,7 +265,7 @@ define <4 x float> @test_x86_sse2_cvtpd2ps_zext(<2 x double> %a0) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]]) @@ -285,7 +285,7 @@ define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(<2 x double>* %p0) nounwind ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] ; CHECK: 2: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: ; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, <2 x double>* [[P0:%.*]], align 16 @@ -297,7 +297,7 @@ define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(<2 x double>* %p0) nounwind ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0]]) @@ -319,7 +319,7 @@ define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> [[A0:%.*]]) @@ -340,7 +340,7 @@ define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[A0:%.*]]) @@ -363,7 +363,7 @@ define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) #0 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1:%.*]]) @@ -384,7 +384,7 @@ define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, <2 x double>* % ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, <2 x double>* [[P1:%.*]], align 16 @@ -397,7 +397,7 @@ define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, <2 x double>* % ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] ; CHECK: 10: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]]) @@ -418,7 +418,7 @@ define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, <2 x do ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, <2 x double>* [[P1:%.*]], align 16 @@ -431,7 +431,7 @@ define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, <2 x do ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] ; CHECK: 10: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]]) @@ -452,7 +452,7 @@ define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]]) @@ -473,7 +473,7 @@ define <2 x i64> @test_mm_cvttpd_epi32_zext(<2 x double> %a0) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]]) @@ -496,7 +496,7 @@ define <2 x i64> @test_mm_cvttpd_epi32_zext_load(<2 x double>* %p0) nounwind #0 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] ; CHECK: 2: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: ; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, <2 x double>* [[P0:%.*]], align 16 @@ -508,7 +508,7 @@ define <2 x i64> @test_mm_cvttpd_epi32_zext_load(<2 x double>* %p0) nounwind #0 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0]]) @@ -533,7 +533,7 @@ define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> [[A0:%.*]]) @@ -554,7 +554,7 @@ define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[A0:%.*]]) @@ -641,7 +641,7 @@ define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[A0:%.*]]) @@ -812,7 +812,7 @@ define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> [[A0:%.*]]) @@ -1141,7 +1141,7 @@ define <8 x i16> @test_x86_sse2_psrl_w_load(<8 x i16> %a0, <8 x i16>* %p) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 16 @@ -1367,7 +1367,7 @@ define void @clflush(i8* %p) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] ; CHECK: 2: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR6]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: ; CHECK-NEXT: tail call void @llvm.x86.sse2.clflush(i8* [[P:%.*]]) diff --git a/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll index 7d593d7..4681c0c 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll @@ -52,7 +52,7 @@ define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) #0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7) @@ -77,7 +77,7 @@ define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 7) @@ -102,7 +102,7 @@ define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) #0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 17) @@ -128,7 +128,7 @@ define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]], i8 7) @@ -148,7 +148,7 @@ define <8 x i16> @test_x86_sse41_mpsadbw_load_op0(<16 x i8>* %ptr, <16 x i8> %a1 ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A0:%.*]] = load <16 x i8>, <16 x i8>* [[PTR:%.*]], align 16 @@ -163,7 +163,7 @@ define <8 x i16> @test_x86_sse41_mpsadbw_load_op0(<16 x i8>* %ptr, <16 x i8> %a1 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] ; CHECK: 10: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> [[A0]], <16 x i8> [[A1:%.*]], i8 7) @@ -252,7 +252,7 @@ define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse41.ptestc(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) @@ -277,7 +277,7 @@ define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) @@ -302,7 +302,7 @@ define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse41.ptestz(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) @@ -323,7 +323,7 @@ define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> [[A0:%.*]], i32 7) @@ -344,7 +344,7 @@ define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> [[A0:%.*]], i32 7) @@ -381,7 +381,7 @@ define <2 x double> @test_x86_sse41_round_sd_load(<2 x double> %a0, <2 x double> ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A1B:%.*]] = load <2 x double>, <2 x double>* [[A1:%.*]], align 16 @@ -408,7 +408,7 @@ define <4 x float> @test_x86_sse41_round_ss_load(<4 x float> %a0, <4 x float>* % ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 0) #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[A1B:%.*]] = load <4 x float>, <4 x float>* [[A1:%.*]], align 16 diff --git a/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll b/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll index 67bc9cd..52acbfe 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll @@ -22,7 +22,7 @@ entry: ; CHECK: [[S:%[_01-9a-z]+]] = extractelement <2 x i64> {{.*}}, i32 0 ; CHECK: icmp ne {{.*}}[[S]], 0 ; CHECK: br -; CHECK: call void @__msan_warning_with_origin_noreturn +; CHECK: call void @__msan_warning_noreturn() ; CHECK: call i32 @llvm.x86.sse2.cvtsd2si ; CHECK: store i32 0, {{.*}} @__msan_retval_tls ; CHECK: ret i32 @@ -41,7 +41,7 @@ entry: ; CHECK: [[S:%[_01-9a-z]+]] = or i32 ; CHECK: icmp ne {{.*}}[[S]], 0 ; CHECK: br -; CHECK: call void @__msan_warning_with_origin_noreturn +; CHECK: call void @__msan_warning_noreturn() ; CHECK: call x86_mmx @llvm.x86.sse.cvtps2pi ; CHECK: store i64 0, {{.*}} @__msan_retval_tls ; CHECK: ret x86_mmx @@ -58,7 +58,7 @@ entry: ; CHECK: extractelement <4 x i32> {{.*}}, i32 0 ; CHECK: icmp ne i32 {{.*}}, 0 ; CHECK: br -; CHECK: call void @__msan_warning_with_origin_noreturn +; CHECK: call void @__msan_warning_noreturn() ; CHECK: call i32 @llvm.x86.avx512.vcvtss2usi32 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls ; CHECK: ret i32