From: Seung-Woo Kim Date: Thu, 16 May 2024 07:57:59 +0000 (+0900) Subject: Set platform.core.cpu.arch and platform.core.fpu.arch features of VisionFive2 X-Git-Tag: accepted/tizen/unified/x/20240516.161256^0 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ad2844923585c2a57bf28836d435eeb0b0053209;p=tools%2Fbuilding-blocks.git Set platform.core.cpu.arch and platform.core.fpu.arch features of VisionFive2 The VisionFive2 board has jh7110 soc with u74 core, and it is riscv64 cpu arch having rvf and rvd floating point extensions. Set platform.core.cpu.arch and platform.core.fpu.arch features with the cpu information. The features are used in tct-systeminfo-tizen-tests of web tct. Change-Id: I5a9a84bd233a409bf46c22b02848f1e4aefefe74 Signed-off-by: Seung-Woo Kim --- diff --git a/packaging/platform-preset-boards-visionfive2-hal-backend.inc b/packaging/platform-preset-boards-visionfive2-hal-backend.inc index bcf3d3f..18b9aa3 100644 --- a/packaging/platform-preset-boards-visionfive2-hal-backend.inc +++ b/packaging/platform-preset-boards-visionfive2-hal-backend.inc @@ -65,8 +65,10 @@ Firstly select HAL Backends to add to your image. %tizen_hal_feature tizen.org/feature/usb.host true %tizen_hal_feature tizen.org/feature/download true %tizen_hal_feature tizen.org/feature/platform.core.abi riscv_64 +%tizen_hal_feature tizen.org/feature/platform.core.cpu.arch riscv64 %tizen_hal_feature tizen.org/feature/platform.core.cpu.arch.riscv32 false %tizen_hal_feature tizen.org/feature/platform.core.cpu.arch.riscv64 true +%tizen_hal_feature tizen.org/feature/platform.core.fpu.arch rvfd ### VISIONFIVE2-Power ### %package sub2-Preset_boards-VISIONFIVE2_HAL_Backend-Power