From: rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 15 Sep 2005 00:05:53 +0000 (+0000)
Subject:         * config/ia64/vect.md (addv2sf3, subv2sf3): Rewrite as expand.
X-Git-Tag: upstream/4.9.2~58635
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=acde5e690528b7c53894487dd8c841f032cf691c;p=platform%2Fupstream%2Flinaro-gcc.git

    * config/ia64/vect.md (addv2sf3, subv2sf3): Rewrite as expand.
        (addv2sf3_1, addv2sf3_2, subv2sf3_1, subv2sf3_2): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@104287 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 57a314c..a3dd760 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2005-09-14  Richard Henderson  <rth@redhat.com>
+
+	* config/ia64/vect.md (addv2sf3, subv2sf3): Rewrite as expand.
+	(addv2sf3_1, addv2sf3_2, subv2sf3_1, subv2sf3_2): New.
+
 2005-09-14  Andrew Pinski  <pinskia@physics.uc.edu>
 
 	* config/i386/i386.c (contains_128bit_aligned_vector_p): Add break
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index dc6e0f7..88e9eb2 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -793,30 +793,96 @@
   "fpnegabs %0 = %1"
   [(set_attr "itanium_class" "fmisc")])
 
+;; In order to convince combine to merge plus and mult to a useful fpma,
+;; we need a couple of extra patterns.
 (define_expand "addv2sf3"
-  [(set (match_operand:V2SF 0 "fr_register_operand" "")
-	(plus:V2SF
-	  (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
-		     (match_dup 3))
-	  (match_operand:V2SF 2 "fr_register_operand" "")))]
+  [(parallel
+    [(set (match_operand:V2SF 0 "fr_register_operand" "")
+	  (plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
+		     (match_operand:V2SF 2 "fr_register_operand" "")))
+     (use (match_dup 3))])]
   ""
 {
   rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
   operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
 })
 
+;; The split condition here could be combine_completed, if we had such.
+(define_insn_and_split "*addv2sf3_1"
+  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
+	(plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
+		   (match_operand:V2SF 2 "fr_register_operand" "f")))
+   (use (match_operand:V2SF 3 "fr_register_operand" "f"))]
+  ""
+  "#"
+  "reload_completed"
+  [(set (match_dup 0)
+	(plus:V2SF
+	  (mult:V2SF (match_dup 1) (match_dup 3))
+	  (match_dup 2)))]
+  "")
+
+(define_insn_and_split "*addv2sf3_2"
+  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
+	(plus:V2SF
+	  (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
+		     (match_operand:V2SF 2 "fr_register_operand" "f"))
+	  (match_operand:V2SF 3 "fr_register_operand" "f")))
+    (use (match_operand:V2SF 4 "" "X"))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0)
+	(plus:V2SF
+	  (mult:V2SF (match_dup 1) (match_dup 2))
+	  (match_dup 3)))]
+  "")
+
+;; In order to convince combine to merge minus and mult to a useful fpms,
+;; we need a couple of extra patterns.
 (define_expand "subv2sf3"
-  [(set (match_operand:V2SF 0 "fr_register_operand" "")
-	(minus:V2SF
-	  (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
-		     (match_dup 3))
-	  (match_operand:V2SF 2 "fr_register_operand" "")))]
+  [(parallel
+    [(set (match_operand:V2SF 0 "fr_register_operand" "")
+	  (minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
+		      (match_operand:V2SF 2 "fr_register_operand" "")))
+     (use (match_dup 3))])]
   ""
 {
   rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
   operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
 })
 
+;; The split condition here could be combine_completed, if we had such.
+(define_insn_and_split "*subv2sf3_1"
+  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
+	(minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
+		    (match_operand:V2SF 2 "fr_register_operand" "f")))
+   (use (match_operand:V2SF 3 "fr_register_operand" "f"))]
+  ""
+  "#"
+  "reload_completed"
+  [(set (match_dup 0)
+	(minus:V2SF
+	  (mult:V2SF (match_dup 1) (match_dup 3))
+	  (match_dup 2)))]
+  "")
+
+(define_insn_and_split "*subv2sf3_2"
+  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
+	(minus:V2SF
+	  (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
+		     (match_operand:V2SF 2 "fr_register_operand" "f"))
+	  (match_operand:V2SF 3 "fr_register_operand" "f")))
+    (use (match_operand:V2SF 4 "" "X"))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0)
+	(minus:V2SF
+	  (mult:V2SF (match_dup 1) (match_dup 2))
+	  (match_dup 3)))]
+  "")
+
 (define_insn "mulv2sf3"
   [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
 	(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")