From: Alison Wang Date: Fri, 22 Apr 2016 02:37:25 +0000 (+0800) Subject: armv8: fsl-layerscape: Remove unnecessary flushing dcache X-Git-Tag: v2016.07-rc1~173^2~16 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=acb8f5e914814ac6c697edb86701958da251a223;p=platform%2Fkernel%2Fu-boot.git armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang Reviewed-by: York Sun --- diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d939900..9a5a6b5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -396,9 +396,6 @@ static inline void final_mmu_setup(void) flush_dcache_range((ulong)level0_table, (ulong)level0_table + gd->arch.tlb_size); -#ifdef CONFIG_SYS_DPAA_FMAN - flush_dcache_all(); -#endif /* point TTBR to the new table */ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES);