From: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Date: Sat, 1 Jul 2017 06:11:58 +0000 (+0200)
Subject: i965: Add support for control register
X-Git-Tag: upstream/18.1.0~3418
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ac8d4734f695b718ae072c2ad961a2cc546b21e0;p=platform%2Fupstream%2Fmesa.git

i965: Add support for control register

Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.

From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
 subsection "Control Register" (page 754):

"Subregister cr0.0:ud contains normal operation control fields such as the
 floating-point mode ... "

Floating-point Rounding mode is changed at bits 5:4 of cr0.0:

"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
  00b = Round to Nearest or Even (RTNE)
  01b = Round Up, toward +inf (RU)
  10b = Round Down, toward -inf (RD)
  11b = Round Toward Zero (RTZ)"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index a039c6f..17d5b97 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -817,6 +817,12 @@ brw_notification_reg(void)
 }
 
 static inline struct brw_reg
+brw_cr0_reg(unsigned subnr)
+{
+   return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr);
+}
+
+static inline struct brw_reg
 brw_sr0_reg(unsigned subnr)
 {
    return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr);