From: Chris Wilson Date: Mon, 1 Oct 2012 13:27:04 +0000 (+0100) Subject: drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a X-Git-Tag: v3.7-rc3~22^2~8^2~34 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ac82ea2e97a32f9c49d0746874b4cd1d8904d10f;p=profile%2Fivi%2Fkernel-x86-ivi.git drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a A side-effect of commit 7d54a904285b6e780291b91a518267bec5591913 Author: Chris Wilson Date: Fri Aug 10 10:18:10 2012 +0100 drm/i915: Apply post-sync write for pipe control invalidates was that only a request to emit invalidate flush would result in the TLB being invalidated (since it requires synchronisation and so incurs a performance penalty). However, the stated w/a for hardware contexts is that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a itself did not request the TLBs to be invalidated... Note this w/a does not prevent the hard system hang I experience when using hw contexts (with rc6 enabled) on SNB GT1. Signed-off-by: Chris Wilson Cc: Ben Widawsky Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 4aa7ecf..b8d9fbb 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -328,7 +328,7 @@ mi_set_context(struct intel_ring_buffer *ring, * itlb_before_ctx_switch. */ if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { - ret = ring->flush(ring, 0, 0); + ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); if (ret) return ret; }