From: geoffk Date: Tue, 23 Dec 2003 08:12:41 +0000 (+0000) Subject: * config/rs6000/rs6000.md: Change many instances of '! X-Git-Tag: upstream/4.9.2~74480 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ac365bcb0c55a8645b17179ce976e1218e628d45;p=platform%2Fupstream%2Flinaro-gcc.git * config/rs6000/rs6000.md: Change many instances of '! TARGET_POWERPC64' to 'TARGET_32BIT' when the pattern being guarded was guarded only because it changed CR0 or the carry bit in XER. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@74966 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f87dbac..768fce9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2003-12-22 Geoffrey Keating + + * config/rs6000/rs6000.md: Change many instances of '! + TARGET_POWERPC64' to 'TARGET_32BIT' when the pattern being guarded + was guarded only because it changed CR0 or the carry bit in XER. + 2003-12-23 Eric Botcazou PR optimization/13394 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 50c3595..402c08c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1020,7 +1020,7 @@ (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ {cax.|add.} %3,%1,%2 {ai.|addic.} %3,%1,%2 @@ -1035,7 +1035,7 @@ (match_operand:SI 2 "reg_or_short_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) @@ -1052,7 +1052,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ {cax.|add.} %0,%1,%2 {ai.|addic.} %0,%1,%2 @@ -1068,7 +1068,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) @@ -1109,7 +1109,7 @@ (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r,r"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ nor. %2,%1,%1 #" @@ -1121,7 +1121,7 @@ (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 2) (not:SI (match_dup 1))) (set (match_dup 0) @@ -1135,7 +1135,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (not:SI (match_dup 1)))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ nor. %0,%1,%1 #" @@ -1148,7 +1148,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (not:SI (match_dup 1)))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (not:SI (match_dup 1))) (set (match_dup 2) @@ -1191,7 +1191,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "TARGET_POWERPC && ! TARGET_POWERPC64" + "TARGET_POWERPC && TARGET_32BIT" "@ subf. %3,%2,%1 #" @@ -1204,7 +1204,7 @@ (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) @@ -1235,7 +1235,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (minus:SI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC && ! TARGET_POWERPC64" + "TARGET_POWERPC && TARGET_32BIT" "@ subf. %0,%2,%1 #" @@ -1250,7 +1250,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) @@ -1563,7 +1563,7 @@ (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r,r"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ neg. %2,%1 #" @@ -1575,7 +1575,7 @@ (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 2) (neg:SI (match_dup 1))) (set (match_dup 0) @@ -1589,7 +1589,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (neg:SI (match_dup 1)))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ neg. %0,%1 #" @@ -1602,7 +1602,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (neg:SI (match_dup 1)))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (neg:SI (match_dup 1))) (set (match_dup 2) @@ -2225,7 +2225,7 @@ (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ and. %3,%1,%2 {andil.|andi.} %3,%1,%b2 @@ -2304,7 +2304,7 @@ (and:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ and. %0,%1,%2 {andil.|andi.} %0,%1,%b2 @@ -2516,7 +2516,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r,r")]) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ %q4. %3,%1,%2 #" @@ -2530,7 +2530,7 @@ (match_operand:SI 2 "gpc_reg_operand" "")]) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) @@ -2545,7 +2545,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 4))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ %q4. %0,%1,%2 #" @@ -2560,7 +2560,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 4))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) @@ -2604,7 +2604,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r,r")]) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ %q4. %3,%2,%1 #" @@ -2618,7 +2618,7 @@ (match_operand:SI 2 "gpc_reg_operand" "")]) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) @@ -2633,7 +2633,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 4))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ %q4. %0,%2,%1 #" @@ -2648,7 +2648,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 4))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) @@ -2670,7 +2670,7 @@ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ %q4. %3,%1,%2 #" @@ -2684,7 +2684,7 @@ (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) @@ -2699,7 +2699,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 4))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ %q4. %0,%1,%2 #" @@ -2714,7 +2714,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 4))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) @@ -3618,7 +3618,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWER && ! TARGET_POWERPC64" + "! TARGET_POWER && TARGET_32BIT" "@ {sl|slw}%I2. %3,%1,%h2 #" @@ -3631,7 +3631,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" + "! TARGET_POWER && TARGET_32BIT && reload_completed" [(set (match_dup 3) (ashift:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) @@ -3680,7 +3680,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashift:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWER && ! TARGET_POWERPC64" + "! TARGET_POWER && TARGET_32BIT" "@ {sl|slw}%I2. %0,%1,%h2 #" @@ -3694,7 +3694,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (ashift:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" + "! TARGET_POWER && TARGET_32BIT && reload_completed" [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) @@ -3851,7 +3851,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) (const_int 0))) (clobber (match_scratch:SI 3 "=X,r,X,r"))] - "! TARGET_POWER && ! TARGET_POWERPC64" + "! TARGET_POWER && TARGET_32BIT" "@ mr. %1,%1 {sr|srw}%I2. %3,%1,%h2 @@ -3866,7 +3866,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" + "! TARGET_POWER && TARGET_32BIT && reload_completed" [(set (match_dup 3) (lshiftrt:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) @@ -3917,7 +3917,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWER && ! TARGET_POWERPC64" + "! TARGET_POWER && TARGET_32BIT" "@ mr. %0,%1 {sr|srw}%I2. %0,%1,%h2 @@ -3933,7 +3933,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" + "! TARGET_POWER && TARGET_32BIT && reload_completed" [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) @@ -7739,7 +7739,7 @@ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ {cmpi|cmpwi} %2,%0,0 mr. %0,%1 @@ -7752,7 +7752,7 @@ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (compare:CC (match_dup 0) @@ -11286,7 +11286,7 @@ (const_int 0))) (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "@ mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 #" @@ -11301,7 +11301,7 @@ (const_int 0))) (set (match_operand:SI 3 "gpc_reg_operand" "") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (match_op_dup 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) @@ -12018,7 +12018,7 @@ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] - "! TARGET_POWERPC64" + "TARGET_32BIT" "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" [(set_attr "length" "12")]) @@ -14169,7 +14169,7 @@ (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:SI 4 ""))] - "! TARGET_POWERPC64 && reload_completed" + "TARGET_32BIT && reload_completed" [(parallel [(set (match_dup 3) (compare:CC (plus:SI (match_dup 1) (const_int -1)) @@ -14195,7 +14195,7 @@ (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:SI 4 ""))] - "! TARGET_POWERPC64 && reload_completed + "TARGET_32BIT && reload_completed && ! gpc_reg_operand (operands[0], SImode)" [(parallel [(set (match_dup 3) (compare:CC (plus:SI (match_dup 1) @@ -14267,63 +14267,6 @@ " { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], const0_rtx); }") - -; These two are for 64-bit hardware running 32-bit mode. -; We don't use the add. instruction in this mode. -(define_split - [(set (pc) - (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:SI 1 "gpc_reg_operand" "") - (const_int 1)]) - (match_operand 5 "" "") - (match_operand 6 "" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) - (const_int -1))) - (clobber (match_scratch:CC 3 "")) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWERPC64 && TARGET_32BIT && reload_completed" - [(set (match_dup 0) - (plus:SI (match_dup 1) - (const_int -1))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0))) - (set (pc) (if_then_else (match_dup 7) - (match_dup 5) - (match_dup 6)))] - " -{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], - const0_rtx); }") - -(define_split - [(set (pc) - (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:SI 1 "gpc_reg_operand" "") - (const_int 1)]) - (match_operand 5 "" "") - (match_operand 6 "" ""))) - (set (match_operand:SI 0 "nonimmediate_operand" "") - (plus:SI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "")) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWERPC64 && TARGET_32BIT && reload_completed - && ! gpc_reg_operand (operands[0], SImode)" - [(set (match_dup 4) - (plus:SI (match_dup 1) - (const_int -1))) - (set (match_dup 3) - (compare:CC (match_dup 4) - (const_int 0))) - (set (match_dup 0) - (match_dup 4)) - (set (pc) (if_then_else (match_dup 7) - (match_dup 5) - (match_dup 6)))] - " -{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], - const0_rtx); }") - (define_insn "trap" [(trap_if (const_int 1) (const_int 0))]