From: Rafael Antognolli Date: Wed, 12 Feb 2020 19:17:28 +0000 (-0800) Subject: drm/i915/tgl: Add Wa_1808121037 to tgl. X-Git-Tag: v5.10.7~1861^2~24^2~900 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ac204c1b34a2f0443265198a5e53795431794bd2;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/tgl: Add Wa_1808121037 to tgl. It's not clear whether this workaround is final yet, but the BSpec indicates that userspace needs to set bit 9 of this register on demand: "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2501 Signed-off-by: Rafael Antognolli [mattrope: Tweaked comment while applying] Signed-off-by: Matt Roper Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20200212191728.25227-1-rafael.antognolli@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index ba86511..887e0dc 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1261,6 +1261,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg_ext(w, PS_INVOCATION_COUNT, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4); + + /* Wa_1808121037:tgl */ + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break;