From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 17 May 2010 16:24:04 +0000 (+0100)
Subject: Merge branch 'devel-stable' into devel
X-Git-Tag: upstream/snapshot3+hdmi~14598^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ac1d426e825ab5778995f2f6f053ca2e6b45c622;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

Merge branch 'devel-stable' into devel

Conflicts:
	arch/arm/Kconfig
	arch/arm/include/asm/system.h
	arch/arm/mm/Kconfig
---

ac1d426e825ab5778995f2f6f053ca2e6b45c622
diff --cc arch/arm/Kconfig
index 2b3157b,ae0ecda..492f813
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -239,8 -253,7 +239,9 @@@ config ARCH_REALVIE
  	select GENERIC_TIME
  	select GENERIC_CLOCKEVENTS
  	select ARCH_WANT_OPTIONAL_GPIOLIB
 +	select PLAT_VERSATILE
 +	select ARM_TIMER_SP804
+ 	select GPIO_PL061 if GPIOLIB
  	help
  	  This enables support for ARM Ltd RealView boards.
  
diff --cc arch/arm/include/asm/system.h
index 02f5d99,4ace45e..5f4f480
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@@ -137,10 -139,12 +139,12 @@@ extern unsigned int user_debug
  #define dmb() __asm__ __volatile__ ("" : : : "memory")
  #endif
  
- #if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
- #define mb()		dmb()
+ #ifdef CONFIG_ARCH_HAS_BARRIERS
+ #include <mach/barriers.h>
 -#elif __LINUX_ARM_ARCH__ >= 7 || defined(CONFIG_SMP)
++#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+ #define mb()		do { dsb(); outer_sync(); } while (0)
  #define rmb()		dmb()
- #define wmb()		dmb()
+ #define wmb()		mb()
  #else
  #define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  #define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
diff --cc arch/arm/mach-versatile/core.c
index 60baba6,3b1a4ee..3dff864
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@@ -28,7 -28,11 +28,8 @@@
  #include <linux/amba/clcd.h>
  #include <linux/amba/pl061.h>
  #include <linux/amba/mmci.h>
 -#include <linux/clocksource.h>
 -#include <linux/clockchips.h>
 -#include <linux/cnt32_to_63.h>
  #include <linux/io.h>
+ #include <linux/gfp.h>
  
  #include <asm/clkdev.h>
  #include <asm/system.h>
diff --cc arch/arm/mm/Kconfig
index 3302730,3e62aae..346ae14
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@@ -754,10 -762,10 +762,11 @@@ config CACHE_FEROCEON_L2_WRITETHROUG
  config CACHE_L2X0
  	bool "Enable the L2x0 outer cache controller"
  	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 -		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
 +		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
 +		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
  	default y
  	select OUTER_CACHE
+ 	select OUTER_CACHE_SYNC
  	help
  	  This option enables the L2x0 PrimeCell.
  
@@@ -783,21 -791,8 +792,27 @@@ config ARM_L1_CACHE_SHIF
  	default 6 if ARM_L1_CACHE_SHIFT_6
  	default 5
  
 +config ARM_DMA_MEM_BUFFERABLE
 +	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
 +	default y if CPU_V6 || CPU_V7
 +	help
 +	  Historically, the kernel has used strongly ordered mappings to
 +	  provide DMA coherent memory.  With the advent of ARMv7, mapping
 +	  memory with differing types results in unpredictable behaviour,
 +	  so on these CPUs, this option is forced on.
 +
 +	  Multiple mappings with differing attributes is also unpredictable
 +	  on ARMv6 CPUs, but since they do not have aggressive speculative
 +	  prefetch, no harm appears to occur.
 +
 +	  However, drivers may be missing the necessary barriers for ARMv6,
 +	  and therefore turning this on may result in unpredictable driver
 +	  behaviour.  Therefore, we offer this as an option.
 +
 +	  You are recommended say 'Y' here and debug any affected drivers.
++
+ config ARCH_HAS_BARRIERS
+ 	bool
+ 	help
+ 	  This option allows the use of custom mandatory barriers
+ 	  included via the mach/barriers.h file.
diff --cc arch/arm/mm/cache-l2x0.c
index 78f0fc8,21ad68b..9819869
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@@ -252,8 -234,7 +261,9 @@@ void __init l2x0_init(void __iomem *bas
  	outer_cache.inv_range = l2x0_inv_range;
  	outer_cache.clean_range = l2x0_clean_range;
  	outer_cache.flush_range = l2x0_flush_range;
+ 	outer_cache.sync = l2x0_cache_sync;
  
 -	printk(KERN_INFO "L2X0 cache controller enabled\n");
 +	printk(KERN_INFO "%s cache controller enabled\n", type);
 +	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
 +			 ways, cache_id, aux);
  }
diff --cc arch/arm/mm/init.c
index 105d1d4,0ed29bf..1ba6cf5
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@@ -15,7 -15,9 +15,8 @@@
  #include <linux/mman.h>
  #include <linux/nodemask.h>
  #include <linux/initrd.h>
 -#include <linux/sort.h>
  #include <linux/highmem.h>
+ #include <linux/gfp.h>
  
  #include <asm/mach-types.h>
  #include <asm/sections.h>