From: Calvin Johnson Date: Thu, 8 Mar 2018 10:00:34 +0000 (+0530) Subject: armv8: layerscape: csu: enable ns access to PFE registers X-Git-Tag: v2018.05-rc1~11^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ac0ba47b9cce15280883c7f196dc9a9a3297afb4;p=platform%2Fkernel%2Fu-boot.git armv8: layerscape: csu: enable ns access to PFE registers Enable all types of non-secure access to PFE block registers. Signed-off-by: Calvin Johnson Signed-off-by: Anjaneyulu Jagarlmudi Acked-by: Joe Hershberger --- diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index f46f1d866a..fe97a930e5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -26,6 +26,7 @@ enum csu_cslx_ind { CSU_CSLX_PCIE3_IO, CSU_CSLX_USB3 = 20, CSU_CSLX_USB2, + CSU_CSLX_PFE = 23, CSU_CSLX_SERDES = 32, CSU_CSLX_QDMA, CSU_CSLX_LPUART2, @@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = { {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, {CSU_CSLX_USB3, CSU_ALL_RW}, {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_PFE, CSU_ALL_RW}, {CSU_CSLX_SERDES, CSU_ALL_RW}, {CSU_CSLX_QDMA, CSU_ALL_RW}, {CSU_CSLX_LPUART2, CSU_ALL_RW},