From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 10 Mar 2020 17:47:08 +0000 (+0800)
Subject: ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
X-Git-Tag: v5.10.7~3015^2~9^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=abe076fb0dfd34e4b8b397946d5e1dab2d7fe953;p=platform%2Fkernel%2Flinux-rpi.git

ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3

When the SPI device nodes were added, SPI2 and SPI3 had incorrect
register base addresses.

Fix the base address for both of them.

Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Reported-by: JuanEsf <juanesf91@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index bb606ea..43c9239 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -689,10 +689,10 @@
 			#size-cells = <0>;
 		};
 
-		spi2: spi@1c07000 {
+		spi2: spi@1c17000 {
 			compatible = "allwinner,sun8i-r40-spi",
 				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c07000 0x1000>;
+			reg = <0x01c17000 0x1000>;
 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
 			clock-names = "ahb", "mod";
@@ -702,10 +702,10 @@
 			#size-cells = <0>;
 		};
 
-		spi3: spi@1c0f000 {
+		spi3: spi@1c1f000 {
 			compatible = "allwinner,sun8i-r40-spi",
 				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c0f000 0x1000>;
+			reg = <0x01c1f000 0x1000>;
 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
 			clock-names = "ahb", "mod";