From: Icenowy Zheng Date: Thu, 2 Feb 2023 07:28:14 +0000 (+0800) Subject: dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx X-Git-Tag: v6.6.7~3511^2~1^2~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=abd873afc889c0b4348ec4b567d83f97df8edaf6;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not compliant to the newcoming ACLINT spec) because of lack of mtime register. Add a compatible string formatted like the C9xx-specific PLIC compatible, and do not allow a SiFive one as fallback because they're not really compliant. Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Reviewed-by: Samuel Holland Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230202072814.319903-1-uwu@icenowy.me Signed-off-by: Daniel Lezcano --- diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index bbad241..aada695 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -20,6 +20,10 @@ description: property of "/cpus" DT node. The "timebase-frequency" DT property is described in Documentation/devicetree/bindings/riscv/cpus.yaml + T-Head C906/C910 CPU cores include an implementation of CLINT too, however + their implementation lacks a memory-mapped MTIME register, thus not + compatible with SiFive ones. + properties: compatible: oneOf: @@ -30,6 +34,10 @@ properties: - canaan,k210-clint - const: sifive,clint0 - items: + - enum: + - allwinner,sun20i-d1-clint + - const: thead,c900-clint + - items: - const: sifive,clint0 - const: riscv,clint0 deprecated: true