From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Date: Wed, 27 Jul 2011 11:22:38 +0000 (+0200)
Subject: MIPS: make cache operation mode configurable
X-Git-Tag: v2011.09-rc1~96^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ab2a98b11716364bc5a8c43cdfa7fee176cda1d8;p=kernel%2Fu-boot.git

MIPS: make cache operation mode configurable

Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
---

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index e829b02..9c1b2f7 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -27,6 +27,10 @@
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
 	/*
 	 * For the moment disable interrupts, mark the kernel mode and
 	 * set ST0_KX so that the CPU does not spit fire when using
@@ -249,7 +253,7 @@ reset:
 	 nop
 
 	/* ... and enable them */
-	li	t0, CONF_CM_CACHABLE_NONCOHERENT
+	li	t0, CONFIG_SYS_MIPS_CACHE_MODE
 	mtc0	t0, CP0_CONFIG
 #endif