From: Chen Zheng <czhengsz@cn.ibm.com>
Date: Wed, 26 Jun 2019 12:02:43 +0000 (+0000)
Subject: [HardwareLoops] NFC - move loop with irreducible control flow checking logic to Harew... 
X-Git-Tag: llvmorg-9.0.0-rc1~1999
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=aa999528966781ae84e508b5a29cc4be7ea0368f;p=platform%2Fupstream%2Fllvm.git

[HardwareLoops] NFC - move loop with irreducible control flow checking logic to HarewareLoopInfo.

llvm-svn: 364415
---

diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index c5dbd956bea8..1e41fd584c6e 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -96,6 +96,7 @@ struct HardwareLoopInfo {
   bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI,
                                DominatorTree &DT, bool ForceNestedLoop = false,
                                bool ForceHardwareLoopPHI = false);
+  bool canAnalyze(LoopInfo &LI);
 };
 
 /// This pass provides access to the codegen interfaces that are needed
@@ -473,8 +474,7 @@ public:
 
   /// Query the target whether it would be profitable to convert the given loop
   /// into a hardware loop.
-  bool isHardwareLoopProfitable(Loop *L, LoopInfo &LI,
-                                ScalarEvolution &SE,
+  bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
                                 AssumptionCache &AC,
                                 TargetLibraryInfo *LibInfo,
                                 HardwareLoopInfo &HWLoopInfo) const;
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 5fde34434578..6dbdaeeae5f8 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -42,6 +42,16 @@ struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
 };
 }
 
+bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
+  // If the loop has irreducible control flow, it can not be converted to
+  // Hardware loop.
+  LoopBlocksRPO RPOT(L);  
+  RPOT.perform(&LI);
+  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
+    return false;
+  return true;
+}
+
 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
                                                LoopInfo &LI, DominatorTree &DT,
                                                bool ForceNestedLoop,
@@ -218,14 +228,8 @@ bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
 }
 
 bool TargetTransformInfo::isHardwareLoopProfitable(
-  Loop *L, LoopInfo &LI, ScalarEvolution &SE, AssumptionCache &AC,
+  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
-  // If the loop has irreducible control flow, it can not be converted to
-  // Hardware loop.
-  LoopBlocksRPO RPOT(L);  
-  RPOT.perform(&LI);
-  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
-    return false;
   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
 }
 
diff --git a/llvm/lib/CodeGen/HardwareLoops.cpp b/llvm/lib/CodeGen/HardwareLoops.cpp
index 3d900e3b7f52..8bf973a7eadd 100644
--- a/llvm/lib/CodeGen/HardwareLoops.cpp
+++ b/llvm/lib/CodeGen/HardwareLoops.cpp
@@ -198,7 +198,10 @@ bool HardwareLoops::TryConvertLoop(Loop *L) {
       return true; // Stop search.
 
   HardwareLoopInfo HWLoopInfo(L);
-  if (TTI->isHardwareLoopProfitable(L, *LI, *SE, *AC, LibInfo, HWLoopInfo) ||
+  if (!HWLoopInfo.canAnalyze(*LI))
+    return false;
+
+  if (TTI->isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo) ||
       ForceHardwareLoops) {
 
     // Allow overriding of the counter width and loop decrement value.