From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Fri, 25 Mar 2022 17:11:38 +0000 (-0700)
Subject: Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel... 
X-Git-Tag: v6.6.17~7916
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=aa5b537b0ecc16992577b013f11112d54c7ce869;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'riscv-for-linus-5.18-mw0' of git://git./linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - Support for Sv57-based virtual memory.

 - Various improvements for the MicroChip PolarFire SOC and the
   associated Icicle dev board, which should allow upstream kernels to
   boot without any additional modifications.

 - An improved memmove() implementation.

 - Support for the new Ssconfpmf and SBI PMU extensions, which allows
   for a much more useful perf implementation on RISC-V systems.

 - Support for restartable sequences.

* tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits)
  rseq/selftests: Add support for RISC-V
  RISC-V: Add support for restartable sequence
  MAINTAINERS: Add entry for RISC-V PMU drivers
  Documentation: riscv: Remove the old documentation
  RISC-V: Add sscofpmf extension support
  RISC-V: Add perf platform driver based on SBI PMU extension
  RISC-V: Add RISC-V SBI PMU extension definitions
  RISC-V: Add a simple platform driver for RISC-V legacy perf
  RISC-V: Add a perf core library for pmu drivers
  RISC-V: Add CSR encodings for all HPMCOUNTERS
  RISC-V: Remove the current perf implementation
  RISC-V: Improve /proc/cpuinfo output for ISA extensions
  RISC-V: Do no continue isa string parsing without correct XLEN
  RISC-V: Implement multi-letter ISA extension probing framework
  RISC-V: Extract multi-letter extension names from "riscv, isa"
  RISC-V: Minimal parser for "riscv, isa" strings
  RISC-V: Correctly print supported extensions
  riscv: Fixed misaligned memory access. Fixed pointer comparison.
  MAINTAINERS: update riscv/microchip entry
  riscv: dts: microchip: add new peripherals to icicle kit device tree
  ...
---

aa5b537b0ecc16992577b013f11112d54c7ce869
diff --cc arch/riscv/kernel/Makefile
index ffc87e7,fb63b46..e0133d1
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@@ -51,9 -51,6 +51,8 @@@ obj-$(CONFIG_MODULE_SECTIONS)	+= module
  obj-$(CONFIG_FUNCTION_TRACER)	+= mcount.o ftrace.o
  obj-$(CONFIG_DYNAMIC_FTRACE)	+= mcount-dyn.o
  
 +obj-$(CONFIG_TRACE_IRQFLAGS)	+= trace_irq.o
 +
- obj-$(CONFIG_RISCV_BASE_PMU)	+= perf_event.o
  obj-$(CONFIG_PERF_EVENTS)	+= perf_callchain.o
  obj-$(CONFIG_HAVE_PERF_REGS)	+= perf_regs.o
  obj-$(CONFIG_RISCV_SBI)		+= sbi.o
diff --cc arch/riscv/mm/kasan_init.c
index cd1a145,3c99b24..a22e418
--- a/arch/riscv/mm/kasan_init.c
+++ b/arch/riscv/mm/kasan_init.c
@@@ -111,13 -111,12 +111,15 @@@ static void __init kasan_populate_pud(p
  		 * pt_ops facility.
  		 */
  		base_pud = pt_ops.get_pud_virt(pfn_to_phys(_pgd_pfn(*pgd)));
+ 	} else if (pgd_none(*pgd)) {
+ 		base_pud = memblock_alloc(PTRS_PER_PUD * sizeof(pud_t), PAGE_SIZE);
  	} else {
  		base_pud = (pud_t *)pgd_page_vaddr(*pgd);
 -		if (base_pud == lm_alias(kasan_early_shadow_pud))
 +		if (base_pud == lm_alias(kasan_early_shadow_pud)) {
  			base_pud = memblock_alloc(PTRS_PER_PUD * sizeof(pud_t), PAGE_SIZE);
 +			memcpy(base_pud, (void *)kasan_early_shadow_pud,
 +			       sizeof(pud_t) * PTRS_PER_PUD);
 +		}
  	}
  
  	pudp = base_pud + pud_index(vaddr);