From: Peng Ju Zhou Date: Thu, 22 Apr 2021 03:25:42 +0000 (+0800) Subject: drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c X-Git-Tag: accepted/tizen/unified/20230118.172025~6864^2~19^2~135 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a9dc23bee25378be306d5b9b83f2e731db89128c;p=platform%2Fkernel%2Flinux-rpi.git drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 75008cc..de85577 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -633,7 +633,9 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, if (entry->and_mask == 0xffffffff) { tmp = entry->or_mask; } else { - tmp = RREG32(reg); + tmp = (entry->hwip == GC_HWIP) ? + RREG32_SOC15_IP(GC, reg) : RREG32(reg); + tmp &= ~(entry->and_mask); tmp |= (entry->or_mask & entry->and_mask); } @@ -644,7 +646,8 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) WREG32_RLC(reg, tmp); else - WREG32(reg, tmp); + (entry->hwip == GC_HWIP) ? + WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); }